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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id r2sm20263856wma.1.2019.10.22.06.32.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Oct 2019 06:32:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=VQV5FCBK+kBKKN7cw2HOegQIhSxfiRcO/BOW8D/eYOc=; b=aa5dwVgzlasXISGNrziOqMe0yxooTPHy5i1Q6TRlHvjYDMP3m1drDJQFN5QT/XQv0J 9WZF2/9VgOEZBEvI67MS9D0ub/OvWI+EDO7tg3yqlPSslzkgJczsW6bPKKoIOtgCYIfm ZOGZ+rdXEpA/CVnxtiBvwp+8+7HvnokwkA3B08euaBKszT832A752itu4dL73MkawLN+ ujkdhnxzqRilOiCuktVCY7rwrn0OeiaYqZGikPPAVaB/NWcqga8n+/JQaTtrvW4rTX4u 70H+EYxge9UwJGiUsDURez0ksQl8hN5nBIH4KLl95t3ELhqaKJewia2oqqACskjojHBv AV5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VQV5FCBK+kBKKN7cw2HOegQIhSxfiRcO/BOW8D/eYOc=; b=n2+tUvlw7nrUvvT4aOIXDtgInAn2m0vrzy4cO5uZFLJ8agOul7uQjYXfYmH4To7a4m KampQsfjmAXU4vlJb3HIG+7cYyOlv6Kh6N2/FjG8V4ZdOWi4yC7l/p7O0ZSF/dIlI/QD xVDK1SKY1PLFzuY4D0VGDRsOcRE5EQfLPNZklbHxJKb1ozaY8QGCsOfmwljbzXFMqvtx IdB8ReMvPLAJoVwp4gRmeG/kBz2D3yO5FgkPBly7AFUoORqYHKPXGAew74u7PmHUhuOI W2qBn2V8tB08uokDffb58ZWKNxxULQCsZwFOvPMzxni4ahABy9sP0ujCUEXuKGzLFN8l eoTQ== X-Gm-Message-State: APjAAAXUqOLQS5RlM8r2bpwCs3mEw7zrsGg8catpB6BqYHcLen9UHiyq 7x3kXfxMMwiLQRYChIcLlipuirtVo/s= X-Google-Smtp-Source: APXvYqzu1qpHbhz8Ocw9Cmci6sLNR9WANJYbGTuDL6ttt63TyE+Uck2IOTN7wnzsEsOsTGEUpWQFAA== X-Received: by 2002:a7b:c924:: with SMTP id h4mr3210630wml.46.1571751175554; Tue, 22 Oct 2019 06:32:55 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 34/41] hw/sd/sdhci: Add dummy Samsung SDHCI controller Date: Tue, 22 Oct 2019 14:31:27 +0100 Message-Id: <20191022133134.14487-35-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191022133134.14487-1-peter.maydell@linaro.org> References: <20191022133134.14487-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Philippe Mathieu-Daud=C3=A9 The Linux kernel access few S3C-specific registers [1] to set some clock. We don't care about this part for device emulation [2]. Add a dummy device to properly ignore these accesses, so we can focus on the important registers missing. [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree= /drivers/mmc/host/sdhci-s3c-regs.h?h=3Dcc014f3 [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree= /drivers/mmc/host/sdhci-s3c.c?h=3Dv5.3#n263 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Krzysztof Kozlowski Message-id: 20191005154748.21718-4-f4bug@amsat.org Signed-off-by: Peter Maydell --- include/hw/sd/sdhci.h | 2 ++ hw/sd/sdhci.c | 65 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 67 insertions(+) diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h index cbf415e43ab..c6868c96994 100644 --- a/include/hw/sd/sdhci.h +++ b/include/hw/sd/sdhci.h @@ -116,4 +116,6 @@ typedef struct SDHCIState { =20 #define TYPE_IMX_USDHC "imx-usdhc" =20 +#define TYPE_S3C_SDHCI "s3c-sdhci" + #endif /* SDHCI_H */ diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index 82ec5c1b4a4..88404d0e9d5 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -1761,11 +1761,76 @@ static const TypeInfo imx_usdhc_info =3D { .instance_init =3D imx_usdhc_init, }; =20 +/* --- qdev Samsung s3c --- */ + +#define S3C_SDHCI_CONTROL2 0x80 +#define S3C_SDHCI_CONTROL3 0x84 +#define S3C_SDHCI_CONTROL4 0x8c + +static uint64_t sdhci_s3c_read(void *opaque, hwaddr offset, unsigned size) +{ + uint64_t ret; + + switch (offset) { + case S3C_SDHCI_CONTROL2: + case S3C_SDHCI_CONTROL3: + case S3C_SDHCI_CONTROL4: + /* ignore */ + ret =3D 0; + break; + default: + ret =3D sdhci_read(opaque, offset, size); + break; + } + + return ret; +} + +static void sdhci_s3c_write(void *opaque, hwaddr offset, uint64_t val, + unsigned size) +{ + switch (offset) { + case S3C_SDHCI_CONTROL2: + case S3C_SDHCI_CONTROL3: + case S3C_SDHCI_CONTROL4: + /* ignore */ + break; + default: + sdhci_write(opaque, offset, val, size); + break; + } +} + +static const MemoryRegionOps sdhci_s3c_mmio_ops =3D { + .read =3D sdhci_s3c_read, + .write =3D sdhci_s3c_write, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 4, + .unaligned =3D false + }, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + +static void sdhci_s3c_init(Object *obj) +{ + SDHCIState *s =3D SYSBUS_SDHCI(obj); + + s->io_ops =3D &sdhci_s3c_mmio_ops; +} + +static const TypeInfo sdhci_s3c_info =3D { + .name =3D TYPE_S3C_SDHCI , + .parent =3D TYPE_SYSBUS_SDHCI, + .instance_init =3D sdhci_s3c_init, +}; + static void sdhci_register_types(void) { type_register_static(&sdhci_sysbus_info); type_register_static(&sdhci_bus_info); type_register_static(&imx_usdhc_info); + type_register_static(&sdhci_s3c_info); } =20 type_init(sdhci_register_types) --=20 2.20.1