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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id r2sm20263856wma.1.2019.10.22.06.32.36 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Oct 2019 06:32:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=xlxLXlWG2xF7OJitSg1PRqbCTnK1/cIa18eJM5Ccjb0=; b=k4wZ9g5/JvmlDhDXNJp7RlyG1tmSfDmztgXuvNEUifzdBDkrRlVydz2bPwfBt+BLoG N8wyBStwFjy6ic4T5zcHmJqksltm8TkbQSrsw8HRZawA3jv9HKnHJb/A/M7ydoDPL5Q0 jInKy8YKajLrSjcttSEsSqGGvggoCqxyFAQFxhZfCc5/rcQVjXe/0AIaiHe5VNQSZ+A5 NSZphuk3PjXuY3gSYKDKxTOWFkO4PqZcqs6qNqcWHvMADh5kr850cFq7ZNeL8Z5T6iPT zybwBothfYLKFPUSHT9HC4Fy/g+n8Rkw08Fb6/X6Mgd4qa4nLvQWp/P5csH/7ygT0A3J nsXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xlxLXlWG2xF7OJitSg1PRqbCTnK1/cIa18eJM5Ccjb0=; b=q5JyMQNW0z2JqAz1ij0xKFNLvWTzl19uqeS9gBHRSbj0EHUZMSObTZ4sGTrRIDSBcn Oy9mGnVIL3OMgeMo4kKyt9kk6+a41BXw8OPfzgtvD8yw+7EnUX8reBh+IW/Eyu0D0gBt 9FmsWenMH98uVUK6gUq+O7c1UY9fX+ldMd5CUKLqMSez0alUS81ClJpewcOzOmDEnCNQ Cz/3/5EHam1/nRqwHozxLCkJUQr9I4x7j2a9Z3s7heN4Y0+1daFfmEhbz0TO8Lny25n+ /ASp/rrnUjjRwzZ9GEQkmvWPA9ejrRBPtkGMMcKkPvFF8Xg7x95mcPFITg5j1JO3PZl3 NCMw== X-Gm-Message-State: APjAAAXB42SX4N0Oixcqnqek1vudJ0p+8bTajPU5Kvlz5OWc43JUMLSq yCGYhTQVsSLSvgjdrAj6LkoFKlnwPR0= X-Google-Smtp-Source: APXvYqzJNUGNBdJBJuk6YWfGetwn+1hg3bpfcZgD7wpqNxyfRsuBPC/7E9xqdkVpmKzlhfvdVgTI2A== X-Received: by 2002:adf:8289:: with SMTP id 9mr3805661wrc.0.1571751158146; Tue, 22 Oct 2019 06:32:38 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 26/41] target/arm: Rebuild hflags at EL changes Date: Tue, 22 Oct 2019 14:31:19 +0100 Message-Id: <20191022133134.14487-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191022133134.14487-1-peter.maydell@linaro.org> References: <20191022133134.14487-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::435 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Richard Henderson Begin setting, but not relying upon, env->hflags. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Message-id: 20191018174431.1784-17-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- linux-user/syscall.c | 1 + target/arm/cpu.c | 1 + target/arm/helper-a64.c | 3 +++ target/arm/helper.c | 2 ++ target/arm/machine.c | 1 + target/arm/op_helper.c | 1 + 6 files changed, 9 insertions(+) diff --git a/linux-user/syscall.c b/linux-user/syscall.c index f1ab81b9177..530c8433036 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -9984,6 +9984,7 @@ static abi_long do_syscall1(void *cpu_env, int num, a= bi_long arg1, aarch64_sve_narrow_vq(env, vq); } env->vfp.zcr_el[1] =3D vq - 1; + arm_rebuild_hflags(env); ret =3D vq * 16; } return ret; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 13813fb2135..ab3e1a03616 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -406,6 +406,7 @@ static void arm_cpu_reset(CPUState *s) =20 hw_breakpoint_update_all(cpu); hw_watchpoint_update_all(cpu); + arm_rebuild_hflags(env); } =20 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index bca80bdc38b..b4cd680fc48 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -1025,6 +1025,7 @@ void HELPER(exception_return)(CPUARMState *env, uint6= 4_t new_pc) } else { env->regs[15] =3D new_pc & ~0x3; } + helper_rebuild_hflags_a32(env, new_el); qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to " "AArch32 EL%d PC 0x%" PRIx32 "\n", cur_el, new_el, env->regs[15]); @@ -1036,10 +1037,12 @@ void HELPER(exception_return)(CPUARMState *env, uin= t64_t new_pc) } aarch64_restore_sp(env, new_el); env->pc =3D new_pc; + helper_rebuild_hflags_a64(env, new_el); qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to " "AArch64 EL%d PC 0x%" PRIx64 "\n", cur_el, new_el, env->pc); } + /* * Note that cur_el can never be 0. If new_el is 0, then * el0_a64 is return_to_aa64, else el0_a64 is ignored. diff --git a/target/arm/helper.c b/target/arm/helper.c index b2d701cf004..aae7b62458f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7998,6 +7998,7 @@ static void take_aarch32_exception(CPUARMState *env, = int new_mode, env->regs[14] =3D env->regs[15] + offset; } env->regs[15] =3D newpc; + arm_rebuild_hflags(env); } =20 static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs) @@ -8345,6 +8346,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) pstate_write(env, PSTATE_DAIF | new_mode); env->aarch64 =3D 1; aarch64_restore_sp(env, new_el); + helper_rebuild_hflags_a64(env, new_el); =20 env->pc =3D addr; =20 diff --git a/target/arm/machine.c b/target/arm/machine.c index 5c36707a7c9..eb28b2381bb 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -756,6 +756,7 @@ static int cpu_post_load(void *opaque, int version_id) if (!kvm_enabled()) { pmu_op_finish(&cpu->env); } + arm_rebuild_hflags(&cpu->env); =20 return 0; } diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 0fd4bd02385..ccc2cecb467 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -404,6 +404,7 @@ void HELPER(cpsr_write_eret)(CPUARMState *env, uint32_t= val) * state. Do the masking now. */ env->regs[15] &=3D (env->thumb ? ~1 : ~3); + arm_rebuild_hflags(env); =20 qemu_mutex_lock_iothread(); arm_call_el_change_hook(env_archcpu(env)); --=20 2.20.1