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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id r2sm20263856wma.1.2019.10.22.06.32.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Oct 2019 06:32:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=GSepKuBdExAvu93R1VSsheMCP0CVd7/15avmFDHul9k=; b=Cu3apOc5mDK9FyIqAQNVtQUXMl94slUh8V1K1GQ/fK117UuOaTKcxgPA8XYf0RUogQ CWXUac3OW+YxXgdEIJGa87LAY3+DP19Jwf9Lnt/gxz6UpdwQ8vox+qTikFWn95DAC7F+ EijFyh4S07tMhM2LhC9/zT6v93LHw5pKmhn4LWBpfX8lJwaMigAsyHL65Z1yl39N2mmW ePVrXGt9xIGg5p9gbeLh8UY0RYpXaQqxvA6LsNWDHHyEG95USYExhTn0ILJJA/3EbbB+ R5UD1zGszxoD9W0EcEF7QkXy/UrGitO5hhKQ269q5hIaLH14RiQ8j24UTI2BuxtzobrK DGWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GSepKuBdExAvu93R1VSsheMCP0CVd7/15avmFDHul9k=; b=YuWqKO313LmDYjUCDeSuVIThSEuhMI2KVzTjudSIOWKQIJ4HRw7oIpreVLRNUG1fvH u5bjkAg+drLud5TpQVBeC161k1U7Aoc8E5+ulJCy8HrR0nuE3iCjWGR6jkL5HQk6p00u y0leMlJPmFCckKrH3d83MFEyaBHEWwfz9RseqjC9NOczCvK7s2AJQj0nHJoMzjmFOVl3 fGZsoXOsCo4jWm9Md2qn0DZXIdRONsl+HNAC9REj5AwUNKUFQ3WpYtWK93+qppAetCiK tgSQwKkGTrleXzs7LlzvpUqsjNnTJI7hNLjP5Ay2wPiY7HSJBsshR6yAv9l5lcaSuB5A x94Q== X-Gm-Message-State: APjAAAVOVyeBgH5NI0/LkETcTmO5yxd3f5fh7poL/+Nf4mILMX1yTxcq D6ySYHgJ5xUXozoeqxwETiC1L5tL6FU= X-Google-Smtp-Source: APXvYqyOYy6htDb3Y5W+97zmQGRjfikMHXpm/zi9KVk7/joQc3vW7VKMjeZ2hfOA0jJSTVI6yZavTw== X-Received: by 2002:adf:d84c:: with SMTP id k12mr3781298wrl.235.1571751150694; Tue, 22 Oct 2019 06:32:30 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/41] target/arm: Add arm_rebuild_hflags Date: Tue, 22 Oct 2019 14:31:15 +0100 Message-Id: <20191022133134.14487-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191022133134.14487-1-peter.maydell@linaro.org> References: <20191022133134.14487-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Richard Henderson This function assumes nothing about the current state of the cpu, and writes the computed value to env->hflags. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Message-id: 20191018174431.1784-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 6 ++++++ target/arm/helper.c | 30 ++++++++++++++++++++++-------- 2 files changed, 28 insertions(+), 8 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 9909ff89d4f..d844ea21d8d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3297,6 +3297,12 @@ void arm_register_pre_el_change_hook(ARMCPU *cpu, AR= MELChangeHookFn *hook, void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void *opaque); =20 +/** + * arm_rebuild_hflags: + * Rebuild the cached TBFLAGS for arbitrary changed processor state. + */ +void arm_rebuild_hflags(CPUARMState *env); + /** * aa32_vfp_dreg: * Return a pointer to the Dn register within env in 32-bit mode. diff --git a/target/arm/helper.c b/target/arm/helper.c index 89aa6fd9339..85de96d071a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11198,17 +11198,35 @@ static uint32_t rebuild_hflags_a64(CPUARMState *e= nv, int el, int fp_el, return rebuild_hflags_common(env, fp_el, mmu_idx, flags); } =20 +static uint32_t rebuild_hflags_internal(CPUARMState *env) +{ + int el =3D arm_current_el(env); + int fp_el =3D fp_exception_el(env, el); + ARMMMUIdx mmu_idx =3D arm_mmu_idx(env); + + if (is_a64(env)) { + return rebuild_hflags_a64(env, el, fp_el, mmu_idx); + } else if (arm_feature(env, ARM_FEATURE_M)) { + return rebuild_hflags_m32(env, fp_el, mmu_idx); + } else { + return rebuild_hflags_a32(env, fp_el, mmu_idx); + } +} + +void arm_rebuild_hflags(CPUARMState *env) +{ + env->hflags =3D rebuild_hflags_internal(env); +} + void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { - ARMMMUIdx mmu_idx =3D arm_mmu_idx(env); - int current_el =3D arm_current_el(env); - int fp_el =3D fp_exception_el(env, current_el); uint32_t flags, pstate_for_ss; =20 + flags =3D rebuild_hflags_internal(env); + if (is_a64(env)) { *pc =3D env->pc; - flags =3D rebuild_hflags_a64(env, current_el, fp_el, mmu_idx); if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { flags =3D FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype); } @@ -11217,8 +11235,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_= ulong *pc, *pc =3D env->regs[15]; =20 if (arm_feature(env, ARM_FEATURE_M)) { - flags =3D rebuild_hflags_m32(env, fp_el, mmu_idx); - if (arm_feature(env, ARM_FEATURE_M_SECURITY) && FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S) !=3D env->v7m.secure) { @@ -11242,8 +11258,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_= ulong *pc, flags =3D FIELD_DP32(flags, TBFLAG_A32, LSPACT, 1); } } else { - flags =3D rebuild_hflags_a32(env, fp_el, mmu_idx); - /* * Note that XSCALE_CPAR shares bits with VECSTRIDE. * Note that VECLEN+VECSTRIDE are RES0 for M-profile. --=20 2.20.1