From nobody Wed Nov 12 16:27:12 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1571529046; cv=none; d=zoho.com; s=zohoarc; b=hb9wDoi4mXoCrsXnKaDgVgrUJ73bH5Q+4msmxCF6x3TAFe0HdzZqIZCGqgEGEiZ9OBG8jvqTcpUDyB7ZK83Eqmz8Wf/7CAuCqDaMz4HdW622L8+GgSlSWrEJY03hnuxcR5gD739cbBhCS9fnG3RyFAhyY1z0Qt/dNhZbsiuYFFw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1571529046; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=d5xrmfH+e2mZccuWjO5XF0mbQ+EhH/vkHED8BLcRG38=; b=kyu1TeEfw5rRQqZw8MOlW6rncBsqp2WEgG2BFJW5harI8d8NwB7/3396H8BmzE5SPOlextEZnS+I/TrWZ25EOSe2qP4kN32aapylgnHRFeeBKpk3UHDjT/+JSOWCVZ1m3ws12Jp/Ek5TF/e8S4mV9ilXAl+FonL9QTaYydscf7Y= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1571529046152865.6660983239672; Sat, 19 Oct 2019 16:50:46 -0700 (PDT) Received: from localhost ([::1]:42134 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iLyUe-0003lr-TK for importer@patchew.org; Sat, 19 Oct 2019 19:50:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34539) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iLyRX-0000CS-LZ for qemu-devel@nongnu.org; Sat, 19 Oct 2019 19:47:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iLyRW-0005Yi-Bn for qemu-devel@nongnu.org; Sat, 19 Oct 2019 19:47:31 -0400 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]:33756) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iLyRW-0005YR-5T; Sat, 19 Oct 2019 19:47:30 -0400 Received: by mail-wm1-x344.google.com with SMTP id r17so11891983wme.0; Sat, 19 Oct 2019 16:47:30 -0700 (PDT) Received: from x1w.redhat.com (14.red-88-21-201.staticip.rima-tde.net. [88.21.201.14]) by smtp.gmail.com with ESMTPSA id u1sm10433763wrp.56.2019.10.19.16.47.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Oct 2019 16:47:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=d5xrmfH+e2mZccuWjO5XF0mbQ+EhH/vkHED8BLcRG38=; b=pVlY4EB37uWVNGoluiIwCwW3AjejPjJayyXcfCFQJ+rAyo38S+ja3pZLq5XiWIpJpG P8bcRr1WP129QKPrN7lVX+L7LHLA3ulgYEQGSVx3c350oz+Wjzw9AsHlWPXJUkBxGfwd 2ZkWA0jp0ranTUvkGzjXlczkFOvvoO7BL3RwNPZJaddQFfF6pw+S8qvfJkX7ddpOp3yQ 8p7Kp7rVEx86N6BCmnY4AESibYXnr3D86kckYULDq7fy6um+SbDLQAe0dGEHXKOuG40t 9RRV52GyvL4oOX4bdAX9aUrr3QUy/N9drIGxjprOdCQmy3ncZcIVtrdbFSdmP9nXSm6y VCkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=d5xrmfH+e2mZccuWjO5XF0mbQ+EhH/vkHED8BLcRG38=; b=ZskIJuPKs4oOeJ+tSa2fOLnHoIe0v7hWDf58PPGbybqHtv6tHoDnbDMTdz8wa7KQCz 6hbc5oF5o6sMPyPFBGrlnDo99LjJC0aPHyK7/e7qDKrbjdtZSg0q40Jf0oSap/YWsBRj BFhYWSCs8lVI1/7nLItkm+pUaOstYVYg+NYFYr6PehRCY20AKOtO3fIH38icFCZouWdq Mc1oiq0I4mKeQCDZlb83arbJmUzA+jFxRWf/revf+9dVZpBHsv4VmXCVQDZooog6Vhcw QqqqiQ7AZZhQAQ6w01tUDH7AFpHVBTFUICR0KGS8wihAASlvoM/Bmm+Jk5RzMqy/bYjr TgHg== X-Gm-Message-State: APjAAAVS89uDsldrueXH78cDwsK2kQP+OzBM3dTuyPJfIEZd5Uew6RLb 7UaoZflN+LmiLRNv7L7R4o37ckjB X-Google-Smtp-Source: APXvYqyNYrH9vj8ADz4k/pOV6UoyVdU0+ykvT4K3MYE/JlLHt2xs6W0ca1cUzIaH50iiIeLN4SHj9Q== X-Received: by 2002:a7b:c3cf:: with SMTP id t15mr12828743wmj.85.1571528848922; Sat, 19 Oct 2019 16:47:28 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 06/16] hw/arm/bcm2836: Rename cpus[] as cpu[].core Date: Sun, 20 Oct 2019 01:47:05 +0200 Message-Id: <20191019234715.25750-7-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191019234715.25750-1-f4bug@amsat.org> References: <20191019234715.25750-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Matthias Brugger , Rob Herring , Alistair Francis , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Andrew Baumann , Esteban Bosse , "Emilio G . Cota" , Clement Deschamps , qemu-arm@nongnu.org, Cleber Rosa , Laurent Bonnans , Cheng Xiang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pekka Enberg , Pete Batard Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) As we are going to add more core-specific fields, add a 'cpu' structure and move the ARMCPU field there as 'core'. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis --- hw/arm/bcm2836.c | 26 ++++++++++++++------------ include/hw/arm/bcm2836.h | 4 +++- 2 files changed, 17 insertions(+), 13 deletions(-) diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index 019e67b906..221ff06895 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -51,8 +51,9 @@ static void bcm2836_init(Object *obj) int n; =20 for (n =3D 0; n < BCM283X_NCPUS; n++) { - object_initialize_child(obj, "cpu[*]", &s->cpus[n], sizeof(s->cpus= [n]), - info->cpu_type, &error_abort, NULL); + object_initialize_child(obj, "cpu[*]", &s->cpu[n].core, + sizeof(s->cpu[n].core), info->cpu_type, + &error_abort, NULL); } =20 sysbus_init_child_obj(obj, "control", &s->control, sizeof(s->control), @@ -122,10 +123,10 @@ static void bcm2836_realize(DeviceState *dev, Error *= *errp) =20 for (n =3D 0; n < BCM283X_NCPUS; n++) { /* TODO: this should be converted to a property of ARM_CPU */ - s->cpus[n].mp_affinity =3D (info->clusterid << 8) | n; + s->cpu[n].core.mp_affinity =3D (info->clusterid << 8) | n; =20 /* set periphbase/CBAR value for CPU-local registers */ - object_property_set_int(OBJECT(&s->cpus[n]), + object_property_set_int(OBJECT(&s->cpu[n].core), info->peri_base, "reset-cbar", &err); if (err) { @@ -134,14 +135,15 @@ static void bcm2836_realize(DeviceState *dev, Error *= *errp) } =20 /* start powered off if not enabled */ - object_property_set_bool(OBJECT(&s->cpus[n]), n >=3D s->enabled_cp= us, + object_property_set_bool(OBJECT(&s->cpu[n].core), n >=3D s->enable= d_cpus, "start-powered-off", &err); if (err) { error_propagate(errp, err); return; } =20 - object_property_set_bool(OBJECT(&s->cpus[n]), true, "realized", &e= rr); + object_property_set_bool(OBJECT(&s->cpu[n].core), true, + "realized", &err); if (err) { error_propagate(errp, err); return; @@ -149,18 +151,18 @@ static void bcm2836_realize(DeviceState *dev, Error *= *errp) =20 /* Connect irq/fiq outputs from the interrupt controller. */ qdev_connect_gpio_out_named(DEVICE(&s->control), "irq", n, - qdev_get_gpio_in(DEVICE(&s->cpus[n]), ARM_CPU_IRQ)); + qdev_get_gpio_in(DEVICE(&s->cpu[n].core), ARM_CPU_IRQ)); qdev_connect_gpio_out_named(DEVICE(&s->control), "fiq", n, - qdev_get_gpio_in(DEVICE(&s->cpus[n]), ARM_CPU_FIQ)); + qdev_get_gpio_in(DEVICE(&s->cpu[n].core), ARM_CPU_FIQ)); =20 /* Connect timers from the CPU to the interrupt controller */ - qdev_connect_gpio_out(DEVICE(&s->cpus[n]), GTIMER_PHYS, + qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_PHYS, qdev_get_gpio_in_named(DEVICE(&s->control), "cntpnsirq", n= )); - qdev_connect_gpio_out(DEVICE(&s->cpus[n]), GTIMER_VIRT, + qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_VIRT, qdev_get_gpio_in_named(DEVICE(&s->control), "cntvirq", n)); - qdev_connect_gpio_out(DEVICE(&s->cpus[n]), GTIMER_HYP, + qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_HYP, qdev_get_gpio_in_named(DEVICE(&s->control), "cnthpirq", n)= ); - qdev_connect_gpio_out(DEVICE(&s->cpus[n]), GTIMER_SEC, + qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_SEC, qdev_get_gpio_in_named(DEVICE(&s->control), "cntpsirq", n)= ); } } diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h index 97187f72be..92a6544816 100644 --- a/include/hw/arm/bcm2836.h +++ b/include/hw/arm/bcm2836.h @@ -35,7 +35,9 @@ typedef struct BCM283XState { char *cpu_type; uint32_t enabled_cpus; =20 - ARMCPU cpus[BCM283X_NCPUS]; + struct { + ARMCPU core; + } cpu[BCM283X_NCPUS]; BCM2836ControlState control; BCM2835PeripheralState peripherals; } BCM283XState; --=20 2.21.0