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[88.21.201.14]) by smtp.gmail.com with ESMTPSA id u1sm10433763wrp.56.2019.10.19.16.47.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Oct 2019 16:47:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=t7hE2pbrub3AVEyc/oyjS4UfKKd4rj51NgMEOKFwXuo=; b=BFiqlYfHurAD4oF18R9w4sddxFJxMhYyTp07v52acGbmFLL6ijI/6Qxnuf6WJ6eYXh xvIaYeou6w2D87k7Bn8lAG/i2pzPQ9NaSyIahJB8nR3OT2xujB4hWoQjoqwtzVg4TqgB 9tDeY/fj7y+byjBTPsnZyS992eUUJ9VfDktMXN6wy7jmsj8AvqGoJoKdBtC3OaBg+8Jk aBhgZp57FTLnjD8nI+lYD+7jRePVrXMGS8j3ElSAmqLWrb1CEzP+cwDCry8hlK4EMyHl Fpvfg+J4Zfq+Z6fKcQai4qlPK6r/sNMFkFUKed2lUCYFQJ63WeGzJegOZG8fT/1eWxoD OgtA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=t7hE2pbrub3AVEyc/oyjS4UfKKd4rj51NgMEOKFwXuo=; b=hjZmr4QRIh0YEuLlzlz077I4lXo1Y7OCblWEhGdt8lPQ9RsZrS8muZw545i8slcaaZ WasCJL/jJWW0S/B6tqsLc1orLWKW2RMLiJrGLqS/Ez7rxDEguDEzFRRB4SralKFeoBXr Un25aLQWMj1WtwwXdL8tdwb2BZeTxM/vcTqa5cZuh4gTJOHbG+dYI7bG+kYnH0C1ojjc jbWZjeg95JBVvqPOljxkcZQueVaQx5AsqsvceJP5mjsPV9GVxx7xXjQ8IabXcDqDJQwf JvJBJqZ/7/7NCQ/nBgZbfRyvk2sPoUtDv9lr2BtUeIBrvsFs9OimBmKzDFXLRV8yQXs9 9Mkg== X-Gm-Message-State: APjAAAVT0jYWjwV0YtOYZXlKw+7W2WZejM4iDyjirFABKBkbqVNBYcCS NMnixOQeD4WU2PK7sAvpPXa2m0OF X-Google-Smtp-Source: APXvYqzpWnjlcXtzlmFfKR1N9DGo6jcA7bC2qkg2M9spZoNI+9M3hXPwPeA3U5WPALFqe5Z7w6sSIQ== X-Received: by 2002:a1c:658a:: with SMTP id z132mr12769528wmb.174.1571528855548; Sat, 19 Oct 2019 16:47:35 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 10/16] hw/arm/raspi: Use AddressSpace when using arm_boot::write_secondary_boot Date: Sun, 20 Oct 2019 01:47:09 +0200 Message-Id: <20191019234715.25750-11-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191019234715.25750-1-f4bug@amsat.org> References: <20191019234715.25750-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Matthias Brugger , Rob Herring , Alistair Francis , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Andrew Baumann , Esteban Bosse , "Emilio G . Cota" , Clement Deschamps , qemu-arm@nongnu.org, Cleber Rosa , Laurent Bonnans , Cheng Xiang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pekka Enberg , Pete Batard Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) write_secondary_boot() is used in SMP configurations where the CPU address space might not be the main System Bus. The rom_add_blob_fixed_as() function allow us to specify an address space. Use it to write each boot blob in the corresponding CPU address space. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis --- hw/arm/raspi.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index a12459bc41..569d85c11a 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -60,12 +60,14 @@ static void write_smpboot(ARMCPU *cpu, const struct arm= _boot_info *info) QEMU_BUILD_BUG_ON((BOARDSETUP_ADDR & 0xf) !=3D 0 || (BOARDSETUP_ADDR >> 4) >=3D 0x100); =20 - rom_add_blob_fixed("raspi_smpboot", smpboot, sizeof(smpboot), - info->smp_loader_start); + rom_add_blob_fixed_as("raspi_smpboot", smpboot, sizeof(smpboot), + info->smp_loader_start, + arm_boot_address_space(cpu, info)); } =20 static void write_smpboot64(ARMCPU *cpu, const struct arm_boot_info *info) { + AddressSpace *as =3D arm_boot_address_space(cpu, info); /* Unlike the AArch32 version we don't need to call the board setup ho= ok. * The mechanism for doing the spin-table is also entirely different. * We must have four 64-bit fields at absolute addresses @@ -92,10 +94,10 @@ static void write_smpboot64(ARMCPU *cpu, const struct a= rm_boot_info *info) 0, 0, 0, 0 }; =20 - rom_add_blob_fixed("raspi_smpboot", smpboot, sizeof(smpboot), - info->smp_loader_start); - rom_add_blob_fixed("raspi_spintables", spintables, sizeof(spintables), - SPINTABLE_ADDR); + rom_add_blob_fixed_as("raspi_smpboot", smpboot, sizeof(smpboot), + info->smp_loader_start, as); + rom_add_blob_fixed_as("raspi_spintables", spintables, sizeof(spintable= s), + SPINTABLE_ADDR, as); } =20 static void write_board_setup(ARMCPU *cpu, const struct arm_boot_info *inf= o) --=20 2.21.0