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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id n15sm718923pjt.13.2019.10.16.21.42.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Oct 2019 21:42:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=SRZQsTbvRxdOfePmd1uDNUZ2LATO2+P/OmknHuKR8Jo=; b=Hnvj8JAPBVP57VOFQg1nzmpXUqkrmXoRi1dp990PBtoeP15bhbYuqFqyb3Tvv/ynLW PrfMw1dEHuWowBSlcaiGW8vKcMiot22GwXB3W9g0IDQEYo/ImkbGy+GcaPuqrPTp4Fe9 AQ1QiwUmBESFj7Tvi8i5IXwhFJY0v6vpl7XkRPpMbM34BXnmQxDo3+pkeBhasmvPAWrH iswCniRIsGqNPekqzcOWjHFC74zflAHNkq57Rl7VOBJ6BTPHoxUE9uAunXSPHx+L4NE2 uUnRzMXMwL3hMupEue2oU3uc98UAQDK/MH+sluIzYe8LdwQs3s7PLNJTeLRJk8yeUTu/ PWew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=SRZQsTbvRxdOfePmd1uDNUZ2LATO2+P/OmknHuKR8Jo=; b=oDlQR6rs0o9bjSUY8ZkXDwzsPJxDE+MQGEf4cyMXJY6hA2QRcQXjpB3hSRXYB/rCks AIUJJJm0L64+QLfBmWTyTtjOAtDxwK3CCRKVbffcBFX1liVkBASBRpi3RrigEPHcVWQF QQP6uRzPqeWCpiVEU4HLVyYXeZItc+j3lmrN8QOcp5vspQJRECDRpYpO6VdElEiobFJ9 vhscXAuQc4kBFt3NqdXvQ/8EP7awW32hxKPrsKmR+2j6UT/cZ0Gv8sxidZloh7h6fElx 0+4F65kbO0Ss8n8CCxZZXJNHpkSwojGuqf2FZmwV3C+lMJI+hOsop++XS0s1pE7zdo9I RQVQ== X-Gm-Message-State: APjAAAXKdnf+YcJeJ0sWXL6GQ8cF5mXziMc1JaPnFLKQsiA3T+tOKMhv CIGAzvi3bzq2mFpdsKJOcNHi26X8YLc= X-Google-Smtp-Source: APXvYqw6so9+lTfzce6Hg7KP2yjnVBYGwp4hdt+mWdVsrxO9F2mzXMjUmulRgA04H94aZg98ty8vPQ== X-Received: by 2002:a17:90a:6346:: with SMTP id v6mr1870189pjs.4.1571287356584; Wed, 16 Oct 2019 21:42:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 1/4] target/arm: Vectorize USHL and SSHL Date: Wed, 16 Oct 2019 21:42:29 -0700 Message-Id: <20191017044232.27601-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191017044232.27601-1-richard.henderson@linaro.org> References: <20191017044232.27601-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::535 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" These instructions shift left or right depending on the sign of the input, and 7 bits are significant to the shift. This requires several masks and selects in addition to the actual shifts to form the complete answer. That said, the operation is still a small improvement even for two 64-bit elements -- 13 vector operations instead of 2 * 7 integer operations. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- v2: Fix operand ordering for aa32 VSHL. --- target/arm/helper.h | 11 +- target/arm/translate.h | 6 + target/arm/neon_helper.c | 33 ---- target/arm/translate-a64.c | 18 +-- target/arm/translate.c | 301 +++++++++++++++++++++++++++++++++++-- target/arm/vec_helper.c | 88 +++++++++++ 6 files changed, 391 insertions(+), 66 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index 1fb2cb5a77..fc0d594a14 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -296,14 +296,8 @@ DEF_HELPER_2(neon_abd_s16, i32, i32, i32) DEF_HELPER_2(neon_abd_u32, i32, i32, i32) DEF_HELPER_2(neon_abd_s32, i32, i32, i32) =20 -DEF_HELPER_2(neon_shl_u8, i32, i32, i32) -DEF_HELPER_2(neon_shl_s8, i32, i32, i32) DEF_HELPER_2(neon_shl_u16, i32, i32, i32) DEF_HELPER_2(neon_shl_s16, i32, i32, i32) -DEF_HELPER_2(neon_shl_u32, i32, i32, i32) -DEF_HELPER_2(neon_shl_s32, i32, i32, i32) -DEF_HELPER_2(neon_shl_u64, i64, i64, i64) -DEF_HELPER_2(neon_shl_s64, i64, i64, i64) DEF_HELPER_2(neon_rshl_u8, i32, i32, i32) DEF_HELPER_2(neon_rshl_s8, i32, i32, i32) DEF_HELPER_2(neon_rshl_u16, i32, i32, i32) @@ -690,6 +684,11 @@ DEF_HELPER_FLAGS_2(frint64_s, TCG_CALL_NO_RWG, f32, f3= 2, ptr) DEF_HELPER_FLAGS_2(frint32_d, TCG_CALL_NO_RWG, f64, f64, ptr) DEF_HELPER_FLAGS_2(frint64_d, TCG_CALL_NO_RWG, f64, f64, ptr) =20 +DEF_HELPER_FLAGS_4(gvec_sshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_sshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_ushl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_ushl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + #ifdef TARGET_AARCH64 #include "helper-a64.h" #include "helper-sve.h" diff --git a/target/arm/translate.h b/target/arm/translate.h index dd24f91f26..0c4e6e4bbd 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -274,6 +274,8 @@ uint64_t vfp_expand_imm(int size, uint8_t imm8); extern const GVecGen3 mla_op[4]; extern const GVecGen3 mls_op[4]; extern const GVecGen3 cmtst_op[4]; +extern const GVecGen3 sshl_op[4]; +extern const GVecGen3 ushl_op[4]; extern const GVecGen2i ssra_op[4]; extern const GVecGen2i usra_op[4]; extern const GVecGen2i sri_op[4]; @@ -283,6 +285,10 @@ extern const GVecGen4 sqadd_op[4]; extern const GVecGen4 uqsub_op[4]; extern const GVecGen4 sqsub_op[4]; void gen_cmtst_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b); +void gen_ushl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b); +void gen_sshl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b); +void gen_ushl_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b); +void gen_sshl_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b); =20 /* * Forward to the isar_feature_* tests given a DisasContext pointer. diff --git a/target/arm/neon_helper.c b/target/arm/neon_helper.c index 4259056723..c581ffb7d3 100644 --- a/target/arm/neon_helper.c +++ b/target/arm/neon_helper.c @@ -615,24 +615,9 @@ NEON_VOP(abd_u32, neon_u32, 1) } else { \ dest =3D src1 << tmp; \ }} while (0) -NEON_VOP(shl_u8, neon_u8, 4) NEON_VOP(shl_u16, neon_u16, 2) -NEON_VOP(shl_u32, neon_u32, 1) #undef NEON_FN =20 -uint64_t HELPER(neon_shl_u64)(uint64_t val, uint64_t shiftop) -{ - int8_t shift =3D (int8_t)shiftop; - if (shift >=3D 64 || shift <=3D -64) { - val =3D 0; - } else if (shift < 0) { - val >>=3D -shift; - } else { - val <<=3D shift; - } - return val; -} - #define NEON_FN(dest, src1, src2) do { \ int8_t tmp; \ tmp =3D (int8_t)src2; \ @@ -645,27 +630,9 @@ uint64_t HELPER(neon_shl_u64)(uint64_t val, uint64_t s= hiftop) } else { \ dest =3D src1 << tmp; \ }} while (0) -NEON_VOP(shl_s8, neon_s8, 4) NEON_VOP(shl_s16, neon_s16, 2) -NEON_VOP(shl_s32, neon_s32, 1) #undef NEON_FN =20 -uint64_t HELPER(neon_shl_s64)(uint64_t valop, uint64_t shiftop) -{ - int8_t shift =3D (int8_t)shiftop; - int64_t val =3D valop; - if (shift >=3D 64) { - val =3D 0; - } else if (shift <=3D -64) { - val >>=3D 63; - } else if (shift < 0) { - val >>=3D -shift; - } else { - val <<=3D shift; - } - return val; -} - #define NEON_FN(dest, src1, src2) do { \ int8_t tmp; \ tmp =3D (int8_t)src2; \ diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 2d6cd09634..255a168df6 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -8685,9 +8685,9 @@ static void handle_3same_64(DisasContext *s, int opco= de, bool u, break; case 0x8: /* SSHL, USHL */ if (u) { - gen_helper_neon_shl_u64(tcg_rd, tcg_rn, tcg_rm); + gen_ushl_i64(tcg_rd, tcg_rn, tcg_rm); } else { - gen_helper_neon_shl_s64(tcg_rd, tcg_rn, tcg_rm); + gen_sshl_i64(tcg_rd, tcg_rn, tcg_rm); } break; case 0x9: /* SQSHL, UQSHL */ @@ -11082,6 +11082,10 @@ static void disas_simd_3same_int(DisasContext *s, = uint32_t insn) is_q ? 16 : 8, vec_full_reg_size(s), (u ? uqsub_op : sqsub_op) + size); return; + case 0x08: /* SSHL, USHL */ + gen_gvec_op3(s, is_q, rd, rn, rm, + u ? &ushl_op[size] : &sshl_op[size]); + return; case 0x0c: /* SMAX, UMAX */ if (u) { gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_umax, size); @@ -11197,16 +11201,6 @@ static void disas_simd_3same_int(DisasContext *s, = uint32_t insn) genfn =3D fns[size][u]; break; } - case 0x8: /* SSHL, USHL */ - { - static NeonGenTwoOpFn * const fns[3][2] =3D { - { gen_helper_neon_shl_s8, gen_helper_neon_shl_u8 }, - { gen_helper_neon_shl_s16, gen_helper_neon_shl_u16 }, - { gen_helper_neon_shl_s32, gen_helper_neon_shl_u32 }, - }; - genfn =3D fns[size][u]; - break; - } case 0x9: /* SQSHL, UQSHL */ { static NeonGenTwoOpEnvFn * const fns[3][2] =3D { diff --git a/target/arm/translate.c b/target/arm/translate.c index 698c594e8c..598bb1cc00 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3580,13 +3580,13 @@ static inline void gen_neon_shift_narrow(int size, = TCGv_i32 var, TCGv_i32 shift, if (u) { switch (size) { case 1: gen_helper_neon_shl_u16(var, var, shift); break; - case 2: gen_helper_neon_shl_u32(var, var, shift); break; + case 2: gen_ushl_i32(var, var, shift); break; default: abort(); } } else { switch (size) { case 1: gen_helper_neon_shl_s16(var, var, shift); break; - case 2: gen_helper_neon_shl_s32(var, var, shift); break; + case 2: gen_sshl_i32(var, var, shift); break; default: abort(); } } @@ -4389,6 +4389,282 @@ const GVecGen3 cmtst_op[4] =3D { .vece =3D MO_64 }, }; =20 +void gen_ushl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + TCGv_i32 lval =3D tcg_temp_new_i32(); + TCGv_i32 rval =3D tcg_temp_new_i32(); + TCGv_i32 lsh =3D tcg_temp_new_i32(); + TCGv_i32 rsh =3D tcg_temp_new_i32(); + TCGv_i32 zero =3D tcg_const_i32(0); + TCGv_i32 max =3D tcg_const_i32(32); + + /* + * Rely on the TCG guarantee that out of range shifts produce + * unspecified results, not undefined behaviour (i.e. no trap). + * Discard out-of-range results after the fact. + */ + tcg_gen_ext8s_i32(lsh, b); + tcg_gen_neg_i32(rsh, lsh); + tcg_gen_shl_i32(lval, a, lsh); + tcg_gen_shr_i32(rval, a, rsh); + tcg_gen_movcond_i32(TCG_COND_LTU, d, lsh, max, lval, zero); + tcg_gen_movcond_i32(TCG_COND_LTU, d, rsh, max, rval, d); + + tcg_temp_free_i32(lval); + tcg_temp_free_i32(rval); + tcg_temp_free_i32(lsh); + tcg_temp_free_i32(rsh); + tcg_temp_free_i32(zero); + tcg_temp_free_i32(max); +} + +void gen_ushl_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) +{ + TCGv_i64 lval =3D tcg_temp_new_i64(); + TCGv_i64 rval =3D tcg_temp_new_i64(); + TCGv_i64 lsh =3D tcg_temp_new_i64(); + TCGv_i64 rsh =3D tcg_temp_new_i64(); + TCGv_i64 zero =3D tcg_const_i64(0); + TCGv_i64 max =3D tcg_const_i64(64); + + /* + * Rely on the TCG guarantee that out of range shifts produce + * unspecified results, not undefined behaviour (i.e. no trap). + * Discard out-of-range results after the fact. + */ + tcg_gen_ext8s_i64(lsh, b); + tcg_gen_neg_i64(rsh, lsh); + tcg_gen_shl_i64(lval, a, lsh); + tcg_gen_shr_i64(rval, a, rsh); + tcg_gen_movcond_i64(TCG_COND_LTU, d, lsh, max, lval, zero); + tcg_gen_movcond_i64(TCG_COND_LTU, d, rsh, max, rval, d); + + tcg_temp_free_i64(lval); + tcg_temp_free_i64(rval); + tcg_temp_free_i64(lsh); + tcg_temp_free_i64(rsh); + tcg_temp_free_i64(zero); + tcg_temp_free_i64(max); +} + +static void gen_ushl_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b) +{ + TCGv_vec lval =3D tcg_temp_new_vec_matching(d); + TCGv_vec rval =3D tcg_temp_new_vec_matching(d); + TCGv_vec lsh =3D tcg_temp_new_vec_matching(d); + TCGv_vec rsh =3D tcg_temp_new_vec_matching(d); + TCGv_vec msk, max; + + /* + * Rely on the TCG guarantee that out of range shifts produce + * unspecified results, not undefined behaviour (i.e. no trap). + * Discard out-of-range results after the fact. + */ + tcg_gen_neg_vec(vece, rsh, b); + if (vece =3D=3D MO_8) { + tcg_gen_mov_vec(lsh, b); + } else { + msk =3D tcg_temp_new_vec_matching(d); + tcg_gen_dupi_vec(vece, msk, 0xff); + tcg_gen_and_vec(vece, lsh, b, msk); + tcg_gen_and_vec(vece, rsh, rsh, msk); + tcg_temp_free_vec(msk); + } + + /* + * Perform possibly out of range shifts, trusting that the operation + * does not trap. Discard unused results after the fact. + */ + tcg_gen_shlv_vec(vece, lval, a, lsh); + tcg_gen_shrv_vec(vece, rval, a, rsh); + + max =3D tcg_temp_new_vec_matching(d); + tcg_gen_dupi_vec(vece, max, 8 << vece); + + /* + * The choice of LT (signed) and GEU (unsigned) are biased toward + * the instructions of the x86_64 host. For MO_8, the whole byte + * is significant so we must use an unsigned compare; otherwise we + * have already masked to a byte and so a signed compare works. + * Other tcg hosts have a full set of comparisons and do not care. + */ + if (vece =3D=3D MO_8) { + tcg_gen_cmp_vec(TCG_COND_GEU, vece, lsh, lsh, max); + tcg_gen_cmp_vec(TCG_COND_GEU, vece, rsh, rsh, max); + tcg_gen_andc_vec(vece, lval, lval, lsh); + tcg_gen_andc_vec(vece, rval, rval, rsh); + } else { + tcg_gen_cmp_vec(TCG_COND_LT, vece, lsh, lsh, max); + tcg_gen_cmp_vec(TCG_COND_LT, vece, rsh, rsh, max); + tcg_gen_and_vec(vece, lval, lval, lsh); + tcg_gen_and_vec(vece, rval, rval, rsh); + } + tcg_gen_or_vec(vece, d, lval, rval); + + tcg_temp_free_vec(max); + tcg_temp_free_vec(lval); + tcg_temp_free_vec(rval); + tcg_temp_free_vec(lsh); + tcg_temp_free_vec(rsh); +} + +static const TCGOpcode ushl_list[] =3D { + INDEX_op_neg_vec, INDEX_op_shlv_vec, + INDEX_op_shrv_vec, INDEX_op_cmp_vec, 0 +}; + +const GVecGen3 ushl_op[4] =3D { + { .fniv =3D gen_ushl_vec, + .fno =3D gen_helper_gvec_ushl_b, + .opt_opc =3D ushl_list, + .vece =3D MO_8 }, + { .fniv =3D gen_ushl_vec, + .fno =3D gen_helper_gvec_ushl_h, + .opt_opc =3D ushl_list, + .vece =3D MO_16 }, + { .fni4 =3D gen_ushl_i32, + .fniv =3D gen_ushl_vec, + .opt_opc =3D ushl_list, + .vece =3D MO_32 }, + { .fni8 =3D gen_ushl_i64, + .fniv =3D gen_ushl_vec, + .opt_opc =3D ushl_list, + .vece =3D MO_64 }, +}; + +void gen_sshl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + TCGv_i32 lval =3D tcg_temp_new_i32(); + TCGv_i32 rval =3D tcg_temp_new_i32(); + TCGv_i32 lsh =3D tcg_temp_new_i32(); + TCGv_i32 rsh =3D tcg_temp_new_i32(); + TCGv_i32 zero =3D tcg_const_i32(0); + TCGv_i32 max =3D tcg_const_i32(31); + + /* + * Rely on the TCG guarantee that out of range shifts produce + * unspecified results, not undefined behaviour (i.e. no trap). + * Discard out-of-range results after the fact. + */ + tcg_gen_ext8s_i32(lsh, b); + tcg_gen_neg_i32(rsh, lsh); + tcg_gen_shl_i32(lval, a, lsh); + tcg_gen_umin_i32(rsh, rsh, max); + tcg_gen_sar_i32(rval, a, rsh); + tcg_gen_movcond_i32(TCG_COND_LEU, lval, lsh, max, lval, zero); + tcg_gen_movcond_i32(TCG_COND_LT, d, lsh, zero, rval, lval); + + tcg_temp_free_i32(lval); + tcg_temp_free_i32(rval); + tcg_temp_free_i32(lsh); + tcg_temp_free_i32(rsh); + tcg_temp_free_i32(zero); + tcg_temp_free_i32(max); +} + +void gen_sshl_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) +{ + TCGv_i64 lval =3D tcg_temp_new_i64(); + TCGv_i64 rval =3D tcg_temp_new_i64(); + TCGv_i64 lsh =3D tcg_temp_new_i64(); + TCGv_i64 rsh =3D tcg_temp_new_i64(); + TCGv_i64 zero =3D tcg_const_i64(0); + TCGv_i64 max =3D tcg_const_i64(63); + + /* + * Rely on the TCG guarantee that out of range shifts produce + * unspecified results, not undefined behaviour (i.e. no trap). + * Discard out-of-range results after the fact. + */ + tcg_gen_ext8s_i64(lsh, b); + tcg_gen_neg_i64(rsh, lsh); + tcg_gen_shl_i64(lval, a, lsh); + tcg_gen_umin_i64(rsh, rsh, max); + tcg_gen_sar_i64(rval, a, rsh); + tcg_gen_movcond_i64(TCG_COND_LEU, lval, lsh, max, lval, zero); + tcg_gen_movcond_i64(TCG_COND_LT, d, lsh, zero, rval, lval); + + tcg_temp_free_i64(lval); + tcg_temp_free_i64(rval); + tcg_temp_free_i64(lsh); + tcg_temp_free_i64(rsh); + tcg_temp_free_i64(zero); + tcg_temp_free_i64(max); +} + +static void gen_sshl_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b) +{ + TCGv_vec lval =3D tcg_temp_new_vec_matching(d); + TCGv_vec rval =3D tcg_temp_new_vec_matching(d); + TCGv_vec lsh =3D tcg_temp_new_vec_matching(d); + TCGv_vec rsh =3D tcg_temp_new_vec_matching(d); + TCGv_vec tmp =3D tcg_temp_new_vec_matching(d); + + /* + * Rely on the TCG guarantee that out of range shifts produce + * unspecified results, not undefined behaviour (i.e. no trap). + * Discard out-of-range results after the fact. + */ + tcg_gen_neg_vec(vece, rsh, b); + if (vece =3D=3D MO_8) { + tcg_gen_mov_vec(lsh, b); + } else { + tcg_gen_dupi_vec(vece, tmp, 0xff); + tcg_gen_and_vec(vece, lsh, b, tmp); + tcg_gen_and_vec(vece, rsh, rsh, tmp); + } + + /* Bound rsh so out of bound right shift gets -1. */ + tcg_gen_dupi_vec(vece, tmp, (8 << vece) - 1); + tcg_gen_umin_vec(vece, rsh, rsh, tmp); + tcg_gen_cmp_vec(TCG_COND_GT, vece, tmp, lsh, tmp); + + tcg_gen_shlv_vec(vece, lval, a, lsh); + tcg_gen_sarv_vec(vece, rval, a, rsh); + + /* Select in-bound left shift. */ + tcg_gen_andc_vec(vece, lval, lval, tmp); + + /* Select between left and right shift. */ + if (vece =3D=3D MO_8) { + tcg_gen_dupi_vec(vece, tmp, 0); + tcg_gen_cmpsel_vec(TCG_COND_LT, vece, d, lsh, tmp, rval, lval); + } else { + tcg_gen_dupi_vec(vece, tmp, 0x80); + tcg_gen_cmpsel_vec(TCG_COND_LT, vece, d, lsh, tmp, lval, rval); + } + + tcg_temp_free_vec(lval); + tcg_temp_free_vec(rval); + tcg_temp_free_vec(lsh); + tcg_temp_free_vec(rsh); + tcg_temp_free_vec(tmp); +} + +static const TCGOpcode sshl_list[] =3D { + INDEX_op_neg_vec, INDEX_op_umin_vec, INDEX_op_shlv_vec, + INDEX_op_sarv_vec, INDEX_op_cmp_vec, INDEX_op_cmpsel_vec, 0 +}; + +const GVecGen3 sshl_op[4] =3D { + { .fniv =3D gen_sshl_vec, + .fno =3D gen_helper_gvec_sshl_b, + .opt_opc =3D sshl_list, + .vece =3D MO_8 }, + { .fniv =3D gen_sshl_vec, + .fno =3D gen_helper_gvec_sshl_h, + .opt_opc =3D sshl_list, + .vece =3D MO_16 }, + { .fni4 =3D gen_sshl_i32, + .fniv =3D gen_sshl_vec, + .opt_opc =3D sshl_list, + .vece =3D MO_32 }, + { .fni8 =3D gen_sshl_i64, + .fniv =3D gen_sshl_vec, + .opt_opc =3D sshl_list, + .vece =3D MO_64 }, +}; + static void gen_uqadd_vec(unsigned vece, TCGv_vec t, TCGv_vec sat, TCGv_vec a, TCGv_vec b) { @@ -4792,6 +5068,12 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) vec_size, vec_size); } return 0; + + case NEON_3R_VSHL: + /* Note the operation is vshl vd,vm,vn */ + tcg_gen_gvec_3(rd_ofs, rm_ofs, rn_ofs, vec_size, vec_size, + u ? &ushl_op[size] : &sshl_op[size]); + return 0; } =20 if (size =3D=3D 3) { @@ -4800,13 +5082,6 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) neon_load_reg64(cpu_V0, rn + pass); neon_load_reg64(cpu_V1, rm + pass); switch (op) { - case NEON_3R_VSHL: - if (u) { - gen_helper_neon_shl_u64(cpu_V0, cpu_V1, cpu_V0); - } else { - gen_helper_neon_shl_s64(cpu_V0, cpu_V1, cpu_V0); - } - break; case NEON_3R_VQSHL: if (u) { gen_helper_neon_qshl_u64(cpu_V0, cpu_env, @@ -4841,7 +5116,6 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) } pairwise =3D 0; switch (op) { - case NEON_3R_VSHL: case NEON_3R_VQSHL: case NEON_3R_VRSHL: case NEON_3R_VQRSHL: @@ -4921,9 +5195,6 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) case NEON_3R_VHSUB: GEN_NEON_INTEGER_OP(hsub); break; - case NEON_3R_VSHL: - GEN_NEON_INTEGER_OP(shl); - break; case NEON_3R_VQSHL: GEN_NEON_INTEGER_OP_ENV(qshl); break; @@ -5332,9 +5603,9 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) } } else { if (input_unsigned) { - gen_helper_neon_shl_u64(cpu_V0, in, tmp64); + gen_ushl_i64(cpu_V0, in, tmp64); } else { - gen_helper_neon_shl_s64(cpu_V0, in, tmp64); + gen_sshl_i64(cpu_V0, in, tmp64); } } tmp =3D tcg_temp_new_i32(); diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c index dedef62403..fcb3663903 100644 --- a/target/arm/vec_helper.c +++ b/target/arm/vec_helper.c @@ -1046,3 +1046,91 @@ void HELPER(gvec_fmlal_idx_a64)(void *vd, void *vn, = void *vm, do_fmlal_idx(vd, vn, vm, &env->vfp.fp_status, desc, get_flush_inputs_to_zero(&env->vfp.fp_status_f16)); } + +void HELPER(gvec_sshl_b)(void *vd, void *vn, void *vm, uint32_t desc) +{ + intptr_t i, opr_sz =3D simd_oprsz(desc); + int8_t *d =3D vd, *n =3D vn, *m =3D vm; + + for (i =3D 0; i < opr_sz; ++i) { + int8_t mm =3D m[i]; + int8_t nn =3D n[i]; + int8_t res =3D 0; + if (mm >=3D 0) { + if (mm < 8) { + res =3D nn << mm; + } + } else { + res =3D nn >> (mm > -8 ? -mm : 7); + } + d[i] =3D res; + } + clear_tail(d, opr_sz, simd_maxsz(desc)); +} + +void HELPER(gvec_sshl_h)(void *vd, void *vn, void *vm, uint32_t desc) +{ + intptr_t i, opr_sz =3D simd_oprsz(desc); + int16_t *d =3D vd, *n =3D vn, *m =3D vm; + + for (i =3D 0; i < opr_sz / 2; ++i) { + int8_t mm =3D m[i]; /* only 8 bits of shift are significant */ + int16_t nn =3D n[i]; + int16_t res =3D 0; + if (mm >=3D 0) { + if (mm < 16) { + res =3D nn << mm; + } + } else { + res =3D nn >> (mm > -16 ? -mm : 15); + } + d[i] =3D res; + } + clear_tail(d, opr_sz, simd_maxsz(desc)); +} + +void HELPER(gvec_ushl_b)(void *vd, void *vn, void *vm, uint32_t desc) +{ + intptr_t i, opr_sz =3D simd_oprsz(desc); + uint8_t *d =3D vd, *n =3D vn, *m =3D vm; + + for (i =3D 0; i < opr_sz; ++i) { + int8_t mm =3D m[i]; + uint8_t nn =3D n[i]; + uint8_t res =3D 0; + if (mm >=3D 0) { + if (mm < 8) { + res =3D nn << mm; + } + } else { + if (mm > -8) { + res =3D nn >> -mm; + } + } + d[i] =3D res; + } + clear_tail(d, opr_sz, simd_maxsz(desc)); +} + +void HELPER(gvec_ushl_h)(void *vd, void *vn, void *vm, uint32_t desc) +{ + intptr_t i, opr_sz =3D simd_oprsz(desc); + uint16_t *d =3D vd, *n =3D vn, *m =3D vm; + + for (i =3D 0; i < opr_sz / 2; ++i) { + int8_t mm =3D m[i]; /* only 8 bits of shift are significant */ + uint16_t nn =3D n[i]; + uint16_t res =3D 0; + if (mm >=3D 0) { + if (mm < 16) { + res =3D nn << mm; + } + } else { + if (mm > -16) { + res =3D nn >> -mm; + } + } + d[i] =3D res; + } + clear_tail(d, opr_sz, simd_maxsz(desc)); +} --=20 2.17.1 From nobody Sat May 18 06:31:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id n15sm718923pjt.13.2019.10.16.21.42.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Oct 2019 21:42:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=PZpnzCTp4TAl1mRs0mTpxpQvQZ85cY78nrzStIrtedc=; b=JfzAzPUF2/99Y/+DBBydjMifYJAY57nm3672k93VYO/eY3zjqys2cRNrLVii9SgnO2 pM2u3chbNOBYnAS9wYSOqv8oqDMMiaynAQhFCF63Gc+nMr/omG7NfbjJJp8AVCd6EDIi FgnAgHSfcd+Dc6oeisrWp2ZcaCnMQE5KBzRmqk7oAGC+eHoljg8DfqS2BK7H/aLvpYP1 s8PPTwrEjaM/fDrUv/HYHbs3ODwjyvawTFsCnmn82zcocAbS0WHtDZq2v7O97HW3JeWs PoD5e0hto/HiNNEq1TgO+oZGpF7gxeLZsYLUGepHTfwM5S3ygNR6ud/FeQlUqX4vwlyg 4n0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=PZpnzCTp4TAl1mRs0mTpxpQvQZ85cY78nrzStIrtedc=; b=aIwjWlEiyLthqZ87qNilNINvK9Lp1PeXfj/WPmLb7EuDXC8wvZPZqdUZTzETUVJOAt 96WgQqh4h+HedBGPTCtSWb9BUxrPrJ/NcF5TWW4jMae0WI8lDX2LEepRh/qsLXk6kA8M ZtdrYKXx7BCz9ZaU3F9h+y26WYQZV9YcwrBHKW/NtpztEgUpZjX9fw1QC/x1qHiHvZBj eOuciyJX/OOkEEgb+LBGt1/WhlGaSJ72xHkGVrd7+KKku1KEllE1VIkiCRBeQ8W17H7x DZC6eHJsMMP8AaReZOyQCu0iQZ+D2IbDPcVjcT3FD5O5z2OftFOtau3WbqfNpFQfZEUZ yNZg== X-Gm-Message-State: APjAAAXx5xwt/LeCASaxyQCcZmViNHnWYNazjxqKxCgjE6ErRrw3ubtO H7HS/xlrYwtEaW76dfpqoR+2HrPCGdY= X-Google-Smtp-Source: APXvYqw+03t31Ft674h0hhjX1d7HyFAfkdpkwPz7iMkYqZT5ks07Fpwv67FLBdfpIn8fHpv0J4jwCg== X-Received: by 2002:a17:902:900c:: with SMTP id a12mr1994684plp.30.1571287357948; Wed, 16 Oct 2019 21:42:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 2/4] target/arm: Convert PMUL.8 to gvec Date: Wed, 16 Oct 2019 21:42:30 -0700 Message-Id: <20191017044232.27601-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191017044232.27601-1-richard.henderson@linaro.org> References: <20191017044232.27601-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The gvec form will be needed for implementing SVE2. Extend the implementation to operate on uint64_t instead of uint32_t. Use a counted inner loop instead of terminating when op1 goes to zero, looking toward the required implementation for ARMv8.4-DIT. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Tested-by: Alex Benn=C3=A9e --- target/arm/helper.h | 3 ++- target/arm/neon_helper.c | 22 ---------------------- target/arm/translate-a64.c | 10 +++------- target/arm/translate.c | 11 ++++------- target/arm/vec_helper.c | 30 ++++++++++++++++++++++++++++++ 5 files changed, 39 insertions(+), 37 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index fc0d594a14..800446e537 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -335,7 +335,6 @@ DEF_HELPER_2(neon_sub_u8, i32, i32, i32) DEF_HELPER_2(neon_sub_u16, i32, i32, i32) DEF_HELPER_2(neon_mul_u8, i32, i32, i32) DEF_HELPER_2(neon_mul_u16, i32, i32, i32) -DEF_HELPER_2(neon_mul_p8, i32, i32, i32) DEF_HELPER_2(neon_mull_p8, i64, i32, i32) =20 DEF_HELPER_2(neon_tst_u8, i32, i32, i32) @@ -689,6 +688,8 @@ DEF_HELPER_FLAGS_4(gvec_sshl_h, TCG_CALL_NO_RWG, void, = ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_ushl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_ushl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) =20 +DEF_HELPER_FLAGS_4(gvec_pmul_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + #ifdef TARGET_AARCH64 #include "helper-a64.h" #include "helper-sve.h" diff --git a/target/arm/neon_helper.c b/target/arm/neon_helper.c index c581ffb7d3..9e7a9a1ac5 100644 --- a/target/arm/neon_helper.c +++ b/target/arm/neon_helper.c @@ -1131,28 +1131,6 @@ NEON_VOP(mul_u16, neon_u16, 2) =20 /* Polynomial multiplication is like integer multiplication except the partial products are XORed, not added. */ -uint32_t HELPER(neon_mul_p8)(uint32_t op1, uint32_t op2) -{ - uint32_t mask; - uint32_t result; - result =3D 0; - while (op1) { - mask =3D 0; - if (op1 & 1) - mask |=3D 0xff; - if (op1 & (1 << 8)) - mask |=3D (0xff << 8); - if (op1 & (1 << 16)) - mask |=3D (0xff << 16); - if (op1 & (1 << 24)) - mask |=3D (0xff << 24); - result ^=3D op2 & mask; - op1 =3D (op1 >> 1) & 0x7f7f7f7f; - op2 =3D (op2 << 1) & 0xfefefefe; - } - return result; -} - uint64_t HELPER(neon_mull_p8)(uint32_t op1, uint32_t op2) { uint64_t result =3D 0; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 255a168df6..04e25cfe06 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11110,9 +11110,10 @@ static void disas_simd_3same_int(DisasContext *s, = uint32_t insn) case 0x13: /* MUL, PMUL */ if (!u) { /* MUL */ gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_mul, size); - return; + } else { /* PMUL */ + gen_gvec_op3_ool(s, is_q, rd, rn, rm, 0, gen_helper_gvec_pmul_= b); } - break; + return; case 0x12: /* MLA, MLS */ if (u) { gen_gvec_op3(s, is_q, rd, rn, rm, &mls_op[size]); @@ -11242,11 +11243,6 @@ static void disas_simd_3same_int(DisasContext *s, = uint32_t insn) genfn =3D fns[size][u]; break; } - case 0x13: /* MUL, PMUL */ - assert(u); /* PMUL */ - assert(size =3D=3D 0); - genfn =3D gen_helper_neon_mul_p8; - break; case 0x16: /* SQDMULH, SQRDMULH */ { static NeonGenTwoOpEnvFn * const fns[2][2] =3D { diff --git a/target/arm/translate.c b/target/arm/translate.c index 598bb1cc00..b66a2f6b71 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5014,16 +5014,17 @@ static int disas_neon_data_insn(DisasContext *s, ui= nt32_t insn) =20 case NEON_3R_VMUL: /* VMUL */ if (u) { - /* Polynomial case allows only P8 and is handled below. */ + /* Polynomial case allows only P8. */ if (size !=3D 0) { return 1; } + tcg_gen_gvec_3_ool(rd_ofs, rn_ofs, rm_ofs, vec_size, vec_s= ize, + 0, gen_helper_gvec_pmul_b); } else { tcg_gen_gvec_mul(size, rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size); - return 0; } - break; + return 0; =20 case NEON_3R_VML: /* VMLA, VMLS */ tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size, @@ -5213,10 +5214,6 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) tmp2 =3D neon_load_reg(rd, pass); gen_neon_add(size, tmp, tmp2); break; - case NEON_3R_VMUL: - /* VMUL.P8; other cases already eliminated. */ - gen_helper_neon_mul_p8(tmp, tmp, tmp2); - break; case NEON_3R_VPMAX: GEN_NEON_INTEGER_OP(pmax); break; diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c index fcb3663903..d401282c6f 100644 --- a/target/arm/vec_helper.c +++ b/target/arm/vec_helper.c @@ -1134,3 +1134,33 @@ void HELPER(gvec_ushl_h)(void *vd, void *vn, void *v= m, uint32_t desc) } clear_tail(d, opr_sz, simd_maxsz(desc)); } + +/* + * 8x8->8 polynomial multiply. + * + * Polynomial multiplication is like integer multiplication except the + * partial products are XORed, not added. + * + * TODO: expose this as a generic vector operation, as it is a common + * crypto building block. + */ +void HELPER(gvec_pmul_b)(void *vd, void *vn, void *vm, uint32_t desc) +{ + intptr_t i, j, opr_sz =3D simd_oprsz(desc); + uint64_t *d =3D vd, *n =3D vn, *m =3D vm; + + for (i =3D 0; i < opr_sz / 8; ++i) { + uint64_t nn =3D n[i]; + uint64_t mm =3D m[i]; + uint64_t rr =3D 0; + + for (j =3D 0; j < 8; ++j) { + uint64_t mask =3D (nn & 0x0101010101010101ull) * 0xff; + rr ^=3D mm & mask; + mm =3D (mm << 1) & 0xfefefefefefefefeull; + nn =3D (nn >> 1) & 0x7f7f7f7f7f7f7f7full; + } + d[i] =3D rr; + } + clear_tail(d, opr_sz, simd_maxsz(desc)); +} --=20 2.17.1 From nobody Sat May 18 06:31:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1571287574; cv=none; d=zoho.com; s=zohoarc; b=jD3qIUaKm7bt4TctypS0ScA+JU3RZ3jE7qLHWbm2MeykBBNF3TzlyMGaXHyV1GWZMxFngCRbU6FUMwEY02B4u7wPbKkWaHYR55GhweCsRGownlphSOuFO3BgGjvkgD1GvzZlv+/hHWWwzEbpNmfLuU+wtHb9fR6DMFcJjENjd74= ARC-Message-Signature: i=1; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id n15sm718923pjt.13.2019.10.16.21.42.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Oct 2019 21:42:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=lVdQH6nYOq21p9N9yfgGgZSVSK8ODl+pJ+gy2hM81M4=; b=adSbWHGemM8aJJEiPLQ40FnnACAWUN8v2PEOpbkkNKFAgEByCo3t4x8+0+bqROQm0R +ypMcdNhFlAByqSvxbaSRuGdl8Yo4bp6hPi8JkQc0n45vY+vUm1bhnyHOOM4Devz5M6f vbzxM0ZoSZH0YttovbpqIq9V7W+AHhrgcM3dSYBmapEPPM+76uNpNHOjEAGjBfZYWklO CMjNYaLa+Gr9FcHkiXsbifaSWEok11G06/vwj5Mw8l9MR8ca3xVZzS2fjIiLls0tNFjq s89ckvsp8Wa9kIU+hRo3oQnyGfdfC9YgU16aB1xR6q0tLZfsqm5uk3PuWKWdtqEwBFyK U+lA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=lVdQH6nYOq21p9N9yfgGgZSVSK8ODl+pJ+gy2hM81M4=; b=mkrXsSJ8mRgtGBxsSgThoGtpoEHlOCu1Qg0BJ/2zExh5OZQFEVcca8suLO5GNiY+K8 sF4ZWNHAejiegntjHb3onjP8sZXu7G83B/YSlzImKhbPVoZSZRajU/IGHy5XBMhm2piv J/32E7R08ar4mfBMffye6xbcl6/5wWHJa5GcXvkGV+BSnPK8cEFL3GGOkzeRqRqZGWh6 O4cHMg+U+rPk158p/oIVuJW6wg5wfRUwjXWB8wOPwNTCp0XOI0AM0PQtFKgpYT9ow7/j y6xaAgSlWGisyH1zrvZBGs9Jp8j4Fp9nIm1jX3mp6tp08qgla9lKd2IX4LM79Zhm2t2V 7ZDA== X-Gm-Message-State: APjAAAVt9RwuYU1u9ZNJkVXf0emqckNYw18564WVQx5v6kzk5OGlFbFQ XvLrCdo3JPR/vN4IsyVF4ICBx9c5G2M= X-Google-Smtp-Source: APXvYqzyTzvNS/lz/gzSjZWvTNQJLb9uJdI2QQTqFJz/LhBj0u0/50mhh/h/TbEc8zlrdrlp+G0QeQ== X-Received: by 2002:a63:931a:: with SMTP id b26mr1864485pge.217.1571287359211; Wed, 16 Oct 2019 21:42:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 3/4] target/arm: Convert PMULL.64 to gvec Date: Wed, 16 Oct 2019 21:42:31 -0700 Message-Id: <20191017044232.27601-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191017044232.27601-1-richard.henderson@linaro.org> References: <20191017044232.27601-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The gvec form will be needed for implementing SVE2. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Tested-by: Alex Benn=C3=A9e --- target/arm/helper.h | 4 +--- target/arm/neon_helper.c | 30 ------------------------------ target/arm/translate-a64.c | 28 +++------------------------- target/arm/translate.c | 16 ++-------------- target/arm/vec_helper.c | 33 +++++++++++++++++++++++++++++++++ 5 files changed, 39 insertions(+), 72 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index 800446e537..d954399b7e 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -555,9 +555,6 @@ DEF_HELPER_FLAGS_3(crc32, TCG_CALL_NO_RWG_SE, i32, i32,= i32, i32) DEF_HELPER_FLAGS_3(crc32c, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) DEF_HELPER_2(dc_zva, void, env, i64) =20 -DEF_HELPER_FLAGS_2(neon_pmull_64_lo, TCG_CALL_NO_RWG_SE, i64, i64, i64) -DEF_HELPER_FLAGS_2(neon_pmull_64_hi, TCG_CALL_NO_RWG_SE, i64, i64, i64) - DEF_HELPER_FLAGS_5(gvec_qrdmlah_s16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_qrdmlsh_s16, TCG_CALL_NO_RWG, @@ -689,6 +686,7 @@ DEF_HELPER_FLAGS_4(gvec_ushl_b, TCG_CALL_NO_RWG, void, = ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_ushl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) =20 DEF_HELPER_FLAGS_4(gvec_pmul_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_pmull_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) =20 #ifdef TARGET_AARCH64 #include "helper-a64.h" diff --git a/target/arm/neon_helper.c b/target/arm/neon_helper.c index 9e7a9a1ac5..6a107da0e1 100644 --- a/target/arm/neon_helper.c +++ b/target/arm/neon_helper.c @@ -2152,33 +2152,3 @@ void HELPER(neon_zip16)(void *vd, void *vm) rm[0] =3D m0; rd[0] =3D d0; } - -/* Helper function for 64 bit polynomial multiply case: - * perform PolynomialMult(op1, op2) and return either the top or - * bottom half of the 128 bit result. - */ -uint64_t HELPER(neon_pmull_64_lo)(uint64_t op1, uint64_t op2) -{ - int bitnum; - uint64_t res =3D 0; - - for (bitnum =3D 0; bitnum < 64; bitnum++) { - if (op1 & (1ULL << bitnum)) { - res ^=3D op2 << bitnum; - } - } - return res; -} -uint64_t HELPER(neon_pmull_64_hi)(uint64_t op1, uint64_t op2) -{ - int bitnum; - uint64_t res =3D 0; - - /* bit 0 of op1 can't influence the high 64 bits at all */ - for (bitnum =3D 1; bitnum < 64; bitnum++) { - if (op1 & (1ULL << bitnum)) { - res ^=3D op2 >> (64 - bitnum); - } - } - return res; -} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 04e25cfe06..12588d18df 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10598,30 +10598,6 @@ static void handle_3rd_narrowing(DisasContext *s, = int is_q, int is_u, int size, clear_vec_high(s, is_q, rd); } =20 -static void handle_pmull_64(DisasContext *s, int is_q, int rd, int rn, int= rm) -{ - /* PMULL of 64 x 64 -> 128 is an odd special case because it - * is the only three-reg-diff instruction which produces a - * 128-bit wide result from a single operation. However since - * it's possible to calculate the two halves more or less - * separately we just use two helper calls. - */ - TCGv_i64 tcg_op1 =3D tcg_temp_new_i64(); - TCGv_i64 tcg_op2 =3D tcg_temp_new_i64(); - TCGv_i64 tcg_res =3D tcg_temp_new_i64(); - - read_vec_element(s, tcg_op1, rn, is_q, MO_64); - read_vec_element(s, tcg_op2, rm, is_q, MO_64); - gen_helper_neon_pmull_64_lo(tcg_res, tcg_op1, tcg_op2); - write_vec_element(s, tcg_res, rd, 0, MO_64); - gen_helper_neon_pmull_64_hi(tcg_res, tcg_op1, tcg_op2); - write_vec_element(s, tcg_res, rd, 1, MO_64); - - tcg_temp_free_i64(tcg_op1); - tcg_temp_free_i64(tcg_op2); - tcg_temp_free_i64(tcg_res); -} - /* AdvSIMD three different * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0 * +---+---+---+-----------+------+---+------+--------+-----+------+------+ @@ -10686,7 +10662,9 @@ static void disas_simd_three_reg_diff(DisasContext = *s, uint32_t insn) if (!fp_access_check(s)) { return; } - handle_pmull_64(s, is_q, rd, rn, rm); + /* The Q field specifies lo/hi half input for this insn. */ + gen_gvec_op3_ool(s, true, rd, rn, rm, is_q, + gen_helper_gvec_pmull_q); return; } goto is_widening; diff --git a/target/arm/translate.c b/target/arm/translate.c index b66a2f6b71..4e34249672 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5877,23 +5877,11 @@ static int disas_neon_data_insn(DisasContext *s, ui= nt32_t insn) * outside the loop below as it only performs a single pas= s. */ if (op =3D=3D 14 && size =3D=3D 2) { - TCGv_i64 tcg_rn, tcg_rm, tcg_rd; - if (!dc_isar_feature(aa32_pmull, s)) { return 1; } - tcg_rn =3D tcg_temp_new_i64(); - tcg_rm =3D tcg_temp_new_i64(); - tcg_rd =3D tcg_temp_new_i64(); - neon_load_reg64(tcg_rn, rn); - neon_load_reg64(tcg_rm, rm); - gen_helper_neon_pmull_64_lo(tcg_rd, tcg_rn, tcg_rm); - neon_store_reg64(tcg_rd, rd); - gen_helper_neon_pmull_64_hi(tcg_rd, tcg_rn, tcg_rm); - neon_store_reg64(tcg_rd, rd + 1); - tcg_temp_free_i64(tcg_rn); - tcg_temp_free_i64(tcg_rm); - tcg_temp_free_i64(tcg_rd); + tcg_gen_gvec_3_ool(rd_ofs, rn_ofs, rm_ofs, 16, 16, + 0, gen_helper_gvec_pmull_q); return 0; } =20 diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c index d401282c6f..5c1074374e 100644 --- a/target/arm/vec_helper.c +++ b/target/arm/vec_helper.c @@ -1164,3 +1164,36 @@ void HELPER(gvec_pmul_b)(void *vd, void *vn, void *v= m, uint32_t desc) } clear_tail(d, opr_sz, simd_maxsz(desc)); } + +/* + * 64x64->128 polynomial multiply. + * Because of the lanes are not accessed in strict columns, + * this probably cannot be turned into a generic helper. + */ +void HELPER(gvec_pmull_q)(void *vd, void *vn, void *vm, uint32_t desc) +{ + intptr_t i, j, opr_sz =3D simd_oprsz(desc); + intptr_t hi =3D simd_data(desc); + uint64_t *d =3D vd, *n =3D vn, *m =3D vm; + + for (i =3D 0; i < opr_sz / 8; i +=3D 2) { + uint64_t nn =3D n[i + hi]; + uint64_t mm =3D m[i + hi]; + uint64_t rhi =3D 0; + uint64_t rlo =3D 0; + + /* Bit 0 can only influence the low 64-bit result. */ + if (nn & 1) { + rlo =3D mm; + } + + for (j =3D 1; j < 64; ++j) { + uint64_t mask =3D -((nn >> j) & 1); + rlo ^=3D (mm << j) & mask; + rhi ^=3D (mm >> (64 - j)) & mask; + } + d[i] =3D rlo; + d[i + 1] =3D rhi; + } + clear_tail(d, opr_sz, simd_maxsz(desc)); +} --=20 2.17.1 From nobody Sat May 18 06:31:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id n15sm718923pjt.13.2019.10.16.21.42.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Oct 2019 21:42:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=zOC1XFUB3wi7uYonQZJi3b57G5irg2dMBLyQa/p2Rwg=; b=PqasWzusV5n8E3FTj5KAwIup8KIFEElEg4opN7fBG35UMUfAmUVUR4vf7HI8LbR9az +uVJBjR6ouG7FVGpCwaI2wl7JIpL+fFUae4OrCaPI0TOIM9GvDk8hcbNcf25owk0iQ7h /9QvZ44yAkI5+/Zqbw4sdZUBelVefNdS3hCIndTp7+wv6hmWQF/bkiCnZ+4dEyZq52kV SlZPKdgoauQwj9l2kXusIP0Zbx5qrhkL/eBvB3LBrB23JEw2D/lNJQpxBWYlSGh+Pw8y 8oj98Xj4TmGucpjiOQlGS/XlUCBwSdMASw2Ffpdm5COMvQ3nQdLj7OwZwYgiX7jm6B+g szIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=zOC1XFUB3wi7uYonQZJi3b57G5irg2dMBLyQa/p2Rwg=; b=d45WR1UwXzvHBWTTRGXPvtIOWBWjzjFwU+MX9BslRR9ML1ZsAayJ7qNgoMBNlmM6OF vlPRyGrU7MakaRWFKK3UqTcw2ilwi2aBCU/vYYzA58GDH0kaOZtetUAB1UlbQyQ6I9o5 hLt2KVXCIzE+3Up3LYkOQ0gV7fp7Sy1CkFLi1bvSL8hQ9d0FWya9NcMDxRiFLzalc1MH Ug8FNE9C36ZTixsXZfXGAxG3Zh5kuGhbGiFB0IxrRfNxHI0xVqTrhH0yNhM43P/c03y0 Ss4WX8eBJw6hw+o1CuxnqVg0NP9PcM5Wrrsg13VcgoFxLN7Ct5PESw/oe1qbYihUH04i 2MSg== X-Gm-Message-State: APjAAAXE0uJ3oDlJYmWnr86Yoejg/pfk5iweycmp68ZvMl0MUOXG0bDt pBYrzoFH0D99H9bRxvmJlkkIEIBOPxc= X-Google-Smtp-Source: APXvYqxpCNftxJggwUkeVGcf5l44WTaRBu5M31kiY3C+Oi6+VYzjV3j1C34kuYMcPqZY+XuVb/Xkwg== X-Received: by 2002:a63:e055:: with SMTP id n21mr1852972pgj.411.1571287360556; Wed, 16 Oct 2019 21:42:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 4/4] target/arm: Convert PMULL.8 to gvec Date: Wed, 16 Oct 2019 21:42:32 -0700 Message-Id: <20191017044232.27601-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191017044232.27601-1-richard.henderson@linaro.org> References: <20191017044232.27601-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We still need two different helpers, since NEON and SVE2 get the inputs from different locations within the source vector. However, we can convert both to the same internal form for computation. The sve2 helper is not used yet, but adding it with this patch helps illustrate why the neon changes are helpful. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Tested-by: Alex Benn=C3=A9e --- target/arm/helper-sve.h | 2 ++ target/arm/helper.h | 3 +- target/arm/neon_helper.c | 32 -------------------- target/arm/translate-a64.c | 27 +++++++++++------ target/arm/translate.c | 26 ++++++++--------- target/arm/vec_helper.c | 60 ++++++++++++++++++++++++++++++++++++++ 6 files changed, 95 insertions(+), 55 deletions(-) diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index 9e79182ab4..2f47279155 100644 --- a/target/arm/helper-sve.h +++ b/target/arm/helper-sve.h @@ -1574,3 +1574,5 @@ DEF_HELPER_FLAGS_6(sve_stdd_le_zd, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr, tl, i32) DEF_HELPER_FLAGS_6(sve_stdd_be_zd, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr, tl, i32) + +DEF_HELPER_FLAGS_4(sve2_pmull_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) diff --git a/target/arm/helper.h b/target/arm/helper.h index d954399b7e..8a8517cf34 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -335,7 +335,6 @@ DEF_HELPER_2(neon_sub_u8, i32, i32, i32) DEF_HELPER_2(neon_sub_u16, i32, i32, i32) DEF_HELPER_2(neon_mul_u8, i32, i32, i32) DEF_HELPER_2(neon_mul_u16, i32, i32, i32) -DEF_HELPER_2(neon_mull_p8, i64, i32, i32) =20 DEF_HELPER_2(neon_tst_u8, i32, i32, i32) DEF_HELPER_2(neon_tst_u16, i32, i32, i32) @@ -688,6 +687,8 @@ DEF_HELPER_FLAGS_4(gvec_ushl_h, TCG_CALL_NO_RWG, void, = ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_pmul_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_pmull_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) =20 +DEF_HELPER_FLAGS_4(neon_pmull_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + #ifdef TARGET_AARCH64 #include "helper-a64.h" #include "helper-sve.h" diff --git a/target/arm/neon_helper.c b/target/arm/neon_helper.c index 6a107da0e1..c7a8438b42 100644 --- a/target/arm/neon_helper.c +++ b/target/arm/neon_helper.c @@ -1129,38 +1129,6 @@ NEON_VOP(mul_u8, neon_u8, 4) NEON_VOP(mul_u16, neon_u16, 2) #undef NEON_FN =20 -/* Polynomial multiplication is like integer multiplication except the - partial products are XORed, not added. */ -uint64_t HELPER(neon_mull_p8)(uint32_t op1, uint32_t op2) -{ - uint64_t result =3D 0; - uint64_t mask; - uint64_t op2ex =3D op2; - op2ex =3D (op2ex & 0xff) | - ((op2ex & 0xff00) << 8) | - ((op2ex & 0xff0000) << 16) | - ((op2ex & 0xff000000) << 24); - while (op1) { - mask =3D 0; - if (op1 & 1) { - mask |=3D 0xffff; - } - if (op1 & (1 << 8)) { - mask |=3D (0xffffU << 16); - } - if (op1 & (1 << 16)) { - mask |=3D (0xffffULL << 32); - } - if (op1 & (1 << 24)) { - mask |=3D (0xffffULL << 48); - } - result ^=3D op2ex & mask; - op1 =3D (op1 >> 1) & 0x7f7f7f7f; - op2ex <<=3D 1; - } - return result; -} - #define NEON_FN(dest, src1, src2) dest =3D (src1 & src2) ? -1 : 0 NEON_VOP(tst_u8, neon_u8, 4) NEON_VOP(tst_u16, neon_u16, 2) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 12588d18df..2934e4fc16 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10483,10 +10483,6 @@ static void handle_3rd_widening(DisasContext *s, i= nt is_q, int is_u, int size, gen_helper_neon_addl_saturate_s32(tcg_passres, cpu_env, tcg_passres, tcg_passres= ); break; - case 14: /* PMULL */ - assert(size =3D=3D 0); - gen_helper_neon_mull_p8(tcg_passres, tcg_op1, tcg_op2); - break; default: g_assert_not_reached(); } @@ -10650,11 +10646,21 @@ static void disas_simd_three_reg_diff(DisasContex= t *s, uint32_t insn) handle_3rd_narrowing(s, is_q, is_u, size, opcode, rd, rn, rm); break; case 14: /* PMULL, PMULL2 */ - if (is_u || size =3D=3D 1 || size =3D=3D 2) { + if (is_u) { unallocated_encoding(s); return; } - if (size =3D=3D 3) { + switch (size) { + case 0: /* PMULL.P8 */ + if (!fp_access_check(s)) { + return; + } + /* The Q field specifies lo/hi half input for this insn. */ + gen_gvec_op3_ool(s, true, rd, rn, rm, is_q, + gen_helper_neon_pmull_h); + break; + + case 3: /* PMULL.P64 */ if (!dc_isar_feature(aa64_pmull, s)) { unallocated_encoding(s); return; @@ -10665,9 +10671,13 @@ static void disas_simd_three_reg_diff(DisasContext= *s, uint32_t insn) /* The Q field specifies lo/hi half input for this insn. */ gen_gvec_op3_ool(s, true, rd, rn, rm, is_q, gen_helper_gvec_pmull_q); - return; + break; + + default: + unallocated_encoding(s); + break; } - goto is_widening; + return; case 9: /* SQDMLAL, SQDMLAL2 */ case 11: /* SQDMLSL, SQDMLSL2 */ case 13: /* SQDMULL, SQDMULL2 */ @@ -10688,7 +10698,6 @@ static void disas_simd_three_reg_diff(DisasContext = *s, uint32_t insn) unallocated_encoding(s); return; } - is_widening: if (!fp_access_check(s)) { return; } diff --git a/target/arm/translate.c b/target/arm/translate.c index 4e34249672..c3abf130cc 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5873,15 +5873,20 @@ static int disas_neon_data_insn(DisasContext *s, ui= nt32_t insn) return 1; } =20 - /* Handle VMULL.P64 (Polynomial 64x64 to 128 bit multiply) - * outside the loop below as it only performs a single pas= s. - */ - if (op =3D=3D 14 && size =3D=3D 2) { - if (!dc_isar_feature(aa32_pmull, s)) { - return 1; + /* Handle polynomial VMULL in a single pass. */ + if (op =3D=3D 14) { + if (size =3D=3D 0) { + /* VMULL.P8 */ + tcg_gen_gvec_3_ool(rd_ofs, rn_ofs, rm_ofs, 16, 16, + 0, gen_helper_neon_pmull_h); + } else { + /* VMULL.P64 */ + if (!dc_isar_feature(aa32_pmull, s)) { + return 1; + } + tcg_gen_gvec_3_ool(rd_ofs, rn_ofs, rm_ofs, 16, 16, + 0, gen_helper_gvec_pmull_q); } - tcg_gen_gvec_3_ool(rd_ofs, rn_ofs, rm_ofs, 16, 16, - 0, gen_helper_gvec_pmull_q); return 0; } =20 @@ -5959,11 +5964,6 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) /* VMLAL, VQDMLAL, VMLSL, VQDMLSL, VMULL, VQDMULL = */ gen_neon_mull(cpu_V0, tmp, tmp2, size, u); break; - case 14: /* Polynomial VMULL */ - gen_helper_neon_mull_p8(cpu_V0, tmp, tmp2); - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp); - break; default: /* 15 is RESERVED: caught earlier */ abort(); } diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c index 5c1074374e..04b4d7402d 100644 --- a/target/arm/vec_helper.c +++ b/target/arm/vec_helper.c @@ -1197,3 +1197,63 @@ void HELPER(gvec_pmull_q)(void *vd, void *vn, void *= vm, uint32_t desc) } clear_tail(d, opr_sz, simd_maxsz(desc)); } + +/* + * 8x8->16 polynomial multiply. + * + * The byte inputs are expanded to (or extracted from) half-words. + * Note that neon and sve2 get the inputs from different positions. + * This allows 4 bytes to be processed in parallel with uint64_t. + */ + +static uint64_t expand_byte_to_half(uint64_t x) +{ + return (x & 0x000000ff) + | ((x & 0x0000ff00) << 8) + | ((x & 0x00ff0000) << 16) + | ((x & 0xff000000) << 24); +} + +static uint64_t pmull_h(uint64_t op1, uint64_t op2) +{ + uint64_t result =3D 0; + int i; + + for (i =3D 0; i < 8; ++i) { + uint64_t mask =3D (op1 & 0x0001000100010001ull) * 0xffff; + result ^=3D op2 & mask; + op1 >>=3D 1; + op2 <<=3D 1; + } + return result; +} + +void HELPER(neon_pmull_h)(void *vd, void *vn, void *vm, uint32_t desc) +{ + int hi =3D simd_data(desc); + uint64_t *d =3D vd, *n =3D vn, *m =3D vm; + uint64_t nn =3D n[hi], mm =3D m[hi]; + + d[0] =3D pmull_h(expand_byte_to_half(nn), expand_byte_to_half(mm)); + nn >>=3D 32; + mm >>=3D 32; + d[1] =3D pmull_h(expand_byte_to_half(nn), expand_byte_to_half(mm)); + + clear_tail(d, 16, simd_maxsz(desc)); +} + +#ifdef TARGET_AARCH64 +void HELPER(sve2_pmull_h)(void *vd, void *vn, void *vm, uint32_t desc) +{ + int shift =3D simd_data(desc) * 8; + intptr_t i, opr_sz =3D simd_oprsz(desc); + uint64_t *d =3D vd, *n =3D vn, *m =3D vm; + + for (i =3D 0; i < opr_sz / 8; ++i) { + uint64_t nn =3D (n[i] >> shift) & 0x00ff00ff00ff00ffull; + uint64_t mm =3D (m[i] >> shift) & 0x00ff00ff00ff00ffull; + + d[i] =3D pmull_h(nn, mm); + } +} +#endif --=20 2.17.1