From nobody Mon Feb 9 09:24:45 2026 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1571157222; cv=none; d=zoho.com; s=zohoarc; b=Be9iZy3WB0SP8wrNPu7Ek79WB6JVlH8yoRdhAYLNYa80rb9DYqldkSa/N8vBVUtQew/e93az0q7I86nWbO8Rc36m+cgIS34oo3EbllNUxIYDjv3D68SHlZU8C7wPoRzlNPiG6/+bkdyyPQ3BwvTZfjYMBXVYuhzxwx9zpQ2u1xA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1571157222; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=zsmukuUvHD497Zy/+LCQHbNEESBmUuxk3OioGYYHzQU=; b=fkRxudQRcp7XsyR3DZ5hD74Dn6kYicVhT0LrhCG/+ivItqs+Zg2xcN3nilSHMKC8bVUYOKr1UqYTv91VuL3E/aYdyKlf7VeEovWlKnKFlav/lTxSGZu0c7CReamzCwN3gkatH1HTgwbpoYYSGy3pxX5F3XWA6gnnkw4MEL9oaPo= ARC-Authentication-Results: i=1; mx.zoho.com; spf=none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1571157222808568.207037255164; Tue, 15 Oct 2019 09:33:42 -0700 (PDT) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iKPkb-00061d-Jh; Tue, 15 Oct 2019 16:32:45 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iKPkb-00061J-3y for xen-devel@lists.xenproject.org; Tue, 15 Oct 2019 16:32:45 +0000 Received: from mx1.redhat.com (unknown [209.132.183.28]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTPS id 6983a6ab-ef69-11e9-9397-12813bfff9fa; Tue, 15 Oct 2019 16:32:44 +0000 (UTC) Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 139E73090FF4; Tue, 15 Oct 2019 16:32:44 +0000 (UTC) Received: from x1w.redhat.com (ovpn-204-35.brq.redhat.com [10.40.204.35]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 9CBAB451D; Tue, 15 Oct 2019 16:32:26 +0000 (UTC) X-Inumbo-ID: 6983a6ab-ef69-11e9-9397-12813bfff9fa From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Date: Tue, 15 Oct 2019 18:27:00 +0200 Message-Id: <20191015162705.28087-28-philmd@redhat.com> In-Reply-To: <20191015162705.28087-1-philmd@redhat.com> References: <20191015162705.28087-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.43]); Tue, 15 Oct 2019 16:32:44 +0000 (UTC) Subject: [Xen-devel] [PATCH 27/32] hw/pci-host/piix: Define and use the PIIX IRQ Route Control Registers X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Thomas Huth , Stefano Stabellini , Eduardo Habkost , kvm@vger.kernel.org, Paul Durrant , "Michael S. Tsirkin" , Marcel Apfelbaum , Paolo Bonzini , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Aleksandar Markovic , xen-devel@lists.xenproject.org, Anthony Perard , Igor Mammedov , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno , Richard Henderson Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The IRQ Route Control registers definitions belong to the PIIX chipset. We were only defining the 'A' register. Define the other B, C and D registers, and use them. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Paul Durrant Reviewed-by: Aleksandar Markovic --- hw/i386/xen/xen-hvm.c | 5 +++-- hw/mips/gt64xxx_pci.c | 4 ++-- hw/pci-host/piix.c | 9 ++++----- include/hw/southbridge/piix.h | 6 ++++++ 4 files changed, 15 insertions(+), 9 deletions(-) diff --git a/hw/i386/xen/xen-hvm.c b/hw/i386/xen/xen-hvm.c index 6b5e5bb7f5..4ce2fb9c89 100644 --- a/hw/i386/xen/xen-hvm.c +++ b/hw/i386/xen/xen-hvm.c @@ -14,6 +14,7 @@ #include "hw/pci/pci.h" #include "hw/pci/pci_host.h" #include "hw/i386/pc.h" +#include "hw/southbridge/piix.h" #include "hw/irq.h" #include "hw/hw.h" #include "hw/i386/apic-msidef.h" @@ -156,8 +157,8 @@ void xen_piix_pci_write_config_client(uint32_t address,= uint32_t val, int len) v =3D 0; } v &=3D 0xf; - if (((address + i) >=3D 0x60) && ((address + i) <=3D 0x63)) { - xen_set_pci_link_route(xen_domid, address + i - 0x60, v); + if (((address + i) >=3D PIIX_PIRQCA) && ((address + i) <=3D PIIX_P= IRQCD)) { + xen_set_pci_link_route(xen_domid, address + i - PIIX_PIRQCA, v= ); } } } diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index c277398c0d..5cab9c1ee1 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -1013,12 +1013,12 @@ static void gt64120_pci_set_irq(void *opaque, int i= rq_num, int level) =20 /* now we change the pic irq level according to the piix irq mappings = */ /* XXX: optimize */ - pic_irq =3D piix4_dev->config[0x60 + irq_num]; + pic_irq =3D piix4_dev->config[PIIX_PIRQCA + irq_num]; if (pic_irq < 16) { /* The pic level is the logical OR of all the PCI irqs mapped to i= t. */ pic_level =3D 0; for (i =3D 0; i < 4; i++) { - if (pic_irq =3D=3D piix4_dev->config[0x60 + i]) { + if (pic_irq =3D=3D piix4_dev->config[PIIX_PIRQCA + i]) { pic_level |=3D pci_irq_levels[i]; } } diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c index 3770575c1a..a450fc726e 100644 --- a/hw/pci-host/piix.c +++ b/hw/pci-host/piix.c @@ -61,7 +61,6 @@ typedef struct I440FXState { #define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */ #define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */ #define XEN_PIIX_NUM_PIRQS 128ULL -#define PIIX_PIRQC 0x60 =20 typedef struct PIIX3State { PCIDevice dev; @@ -468,7 +467,7 @@ static void piix3_set_irq_level_internal(PIIX3State *pi= ix3, int pirq, int level) int pic_irq; uint64_t mask; =20 - pic_irq =3D piix3->dev.config[PIIX_PIRQC + pirq]; + pic_irq =3D piix3->dev.config[PIIX_PIRQCA + pirq]; if (pic_irq >=3D PIIX_NUM_PIC_IRQS) { return; } @@ -482,7 +481,7 @@ static void piix3_set_irq_level(PIIX3State *piix3, int = pirq, int level) { int pic_irq; =20 - pic_irq =3D piix3->dev.config[PIIX_PIRQC + pirq]; + pic_irq =3D piix3->dev.config[PIIX_PIRQCA + pirq]; if (pic_irq >=3D PIIX_NUM_PIC_IRQS) { return; } @@ -501,7 +500,7 @@ static void piix3_set_irq(void *opaque, int pirq, int l= evel) static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin) { PIIX3State *piix3 =3D opaque; - int irq =3D piix3->dev.config[PIIX_PIRQC + pin]; + int irq =3D piix3->dev.config[PIIX_PIRQCA + pin]; PCIINTxRoute route; =20 if (irq < PIIX_NUM_PIC_IRQS) { @@ -530,7 +529,7 @@ static void piix3_write_config(PCIDevice *dev, uint32_t address, uint32_t val, int len) { pci_default_write_config(dev, address, val, len); - if (ranges_overlap(address, len, PIIX_PIRQC, 4)) { + if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) { PIIX3State *piix3 =3D PIIX3_PCI_DEVICE(dev); int pic_irq; =20 diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index 79ebe0089b..9c92c37a4d 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -18,6 +18,12 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t s= mb_io_base, qemu_irq sci_irq, qemu_irq smi_irq, int smm_enabled, DeviceState **piix4_pm); =20 +/* PIRQRC[A:D]: PIRQx Route Control Registers */ +#define PIIX_PIRQCA 0x60 +#define PIIX_PIRQCB 0x61 +#define PIIX_PIRQCC 0x62 +#define PIIX_PIRQCD 0x63 + /* * Reset Control Register: PCI-accessible ISA-Compatible Register at addre= ss * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000). --=20 2.21.0 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel