From nobody Mon Feb 9 04:29:47 2026 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1571157011; cv=none; d=zoho.com; s=zohoarc; b=m2+vywjgj8cvgTQ3Ac/EmWPK/Lf0XutndWESDU3pA2fY898VDRFUXOXPh1tMHsf6ruryetJuGrvNESiJNftFuK+LpxBxksrJNJQlMaJXI00cw1X2BN7Pelt9sgv/ZIWRM3hf8aSbGAe5agvZ0aOzd/AacgjLCDY3zoIuRCvYiMA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1571157011; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=CPwaT6o62qyRqVENpm3ecZfQp5LjFvIGOWaWWFDZwp8=; b=nUmkswOn9L0/Vfvvq+oPHGbNmgW5BNnYEEr9Xb3DGAcdgNoERpdpofqlzFChHHjXAV9fSPn0j9gYIu4rKTpml5qPE+zG8EJ3znbAuan3FNR3iK0ob3/JL9J1zMVMnrjw0/U16WesuAPYA8mraSfRMQ/OEkusbzcQpD0JCBBt5hI= ARC-Authentication-Results: i=1; mx.zoho.com; spf=none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1571157011793495.2400397734542; Tue, 15 Oct 2019 09:30:11 -0700 (PDT) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iKPhD-0003WO-01; Tue, 15 Oct 2019 16:29:14 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iKPhB-0003Vm-Gi for xen-devel@lists.xenproject.org; Tue, 15 Oct 2019 16:29:13 +0000 Received: from mx1.redhat.com (unknown [209.132.183.28]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id ec10cf36-ef68-11e9-beca-bc764e2007e4; Tue, 15 Oct 2019 16:29:13 +0000 (UTC) Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 7E8ED307D942; Tue, 15 Oct 2019 16:29:12 +0000 (UTC) Received: from x1w.redhat.com (ovpn-204-35.brq.redhat.com [10.40.204.35]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 21B2419C58; Tue, 15 Oct 2019 16:29:05 +0000 (UTC) X-Inumbo-ID: ec10cf36-ef68-11e9-beca-bc764e2007e4 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Date: Tue, 15 Oct 2019 18:26:42 +0200 Message-Id: <20191015162705.28087-10-philmd@redhat.com> In-Reply-To: <20191015162705.28087-1-philmd@redhat.com> References: <20191015162705.28087-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.48]); Tue, 15 Oct 2019 16:29:12 +0000 (UTC) Subject: [Xen-devel] [PATCH 09/32] piix4: add Reset Control Register X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Thomas Huth , Stefano Stabellini , Eduardo Habkost , kvm@vger.kernel.org, Paul Durrant , "Michael S. Tsirkin" , Marcel Apfelbaum , Paolo Bonzini , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Aleksandar Markovic , xen-devel@lists.xenproject.org, Anthony Perard , Igor Mammedov , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno , Richard Henderson Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" From: Herv=C3=A9 Poussineau The RCR I/O port (0xcf9) is used to generate a hard reset or a soft reset. Acked-by: Michael S. Tsirkin Acked-by: Paolo Bonzini Signed-off-by: Herv=C3=A9 Poussineau Message-Id: <20171216090228.28505-7-hpoussin@reactos.org> [PMD: rebased, updated includes] Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Aleksandar Markovic --- hw/isa/piix4.c | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 4202243e41..6e2d9b9774 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -2,6 +2,7 @@ * QEMU PIIX4 PCI Bridge Emulation * * Copyright (c) 2006 Fabrice Bellard + * Copyright (c) 2018 Herv=C3=A9 Poussineau * * Permission is hereby granted, free of charge, to any person obtaining a= copy * of this software and associated documentation files (the "Software"), t= o deal @@ -29,11 +30,16 @@ #include "hw/sysbus.h" #include "migration/vmstate.h" #include "sysemu/reset.h" +#include "sysemu/runstate.h" =20 PCIDevice *piix4_dev; =20 typedef struct PIIX4State { PCIDevice dev; + + /* Reset Control Register */ + MemoryRegion rcr_mem; + uint8_t rcr; } PIIX4State; =20 #define TYPE_PIIX4_PCI_DEVICE "PIIX4" @@ -88,6 +94,34 @@ static const VMStateDescription vmstate_piix4 =3D { } }; =20 +static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val, + unsigned int len) +{ + PIIX4State *s =3D opaque; + + if (val & 4) { + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); + return; + } + s->rcr =3D val & 2; /* keep System Reset type only */ +} + +static uint64_t piix4_rcr_read(void *opaque, hwaddr addr, unsigned int len) +{ + PIIX4State *s =3D opaque; + return s->rcr; +} + +static const MemoryRegionOps piix4_rcr_ops =3D { + .read =3D piix4_rcr_read, + .write =3D piix4_rcr_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .impl =3D { + .min_access_size =3D 1, + .max_access_size =3D 1, + }, +}; + static void piix4_realize(PCIDevice *pci_dev, Error **errp) { DeviceState *dev =3D DEVICE(pci_dev); @@ -97,6 +131,12 @@ static void piix4_realize(PCIDevice *pci_dev, Error **e= rrp) pci_address_space_io(pci_dev), errp)) { return; } + + memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s, + "reset-control", 1); + memory_region_add_subregion_overlap(pci_address_space_io(pci_dev), 0xc= f9, + &s->rcr_mem, 1); + piix4_dev =3D pci_dev; qemu_register_reset(piix4_reset, s); } --=20 2.21.0 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel