From nobody Thu Dec 18 19:33:19 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1571071816; cv=none; d=zoho.com; s=zohoarc; b=RqgNwhnKmJ5DHnalilstWDExS4mvKeE9ch2vMVDQ1ltfXrbpZOxVN2QjquknMcBB322zUrurYvJOaVYKyW5QBoMbG0ir5NAUum5Rjq79cL03C1fHytvpmXnAhkolrs+TPBvRYYmTzf32IljcjwU0bO+O9oxKgojySgbLDm985vk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1571071816; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=IqGNIGYeYxIliLJN1uLbXaji79hnCldokJEYbv+GISM=; b=a7xJMJwEGQqIrT/29uYllwW3wl+VSxcX6yIrEbOaQTO8UfbtMXuqQ2tusGPZot/Lqz68ogMEYpz2J6mc6pwgy92MBcWcKDSGy3l9Qx0XldRj6DNlqjEaCU2qkM8/Vo6LT+suX78RFUilZTMwl2DSriOoc00l1Ss5PZ9Hy8UA2L0= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 15710718165631008.4572478916027; Mon, 14 Oct 2019 09:50:16 -0700 (PDT) Received: from localhost ([::1]:53684 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iK3Xy-0002MI-Ug for importer@patchew.org; Mon, 14 Oct 2019 12:50:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37346) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iK2qe-00056x-Qk for qemu-devel@nongnu.org; Mon, 14 Oct 2019 12:05:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iK2qd-00086E-IX for qemu-devel@nongnu.org; Mon, 14 Oct 2019 12:05:28 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]:52246) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iK2qd-00085r-Bv for qemu-devel@nongnu.org; Mon, 14 Oct 2019 12:05:27 -0400 Received: by mail-wm1-x334.google.com with SMTP id r19so17863769wmh.2 for ; Mon, 14 Oct 2019 09:05:27 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id 5sm18029779wrk.86.2019.10.14.09.05.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Oct 2019 09:05:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=IqGNIGYeYxIliLJN1uLbXaji79hnCldokJEYbv+GISM=; b=vaWazH5SfNaUJ2rINfgkFwL08o/qYqifZdpyvMrJ0L9Ltr4wHMArMp8P++PoXXUngL 0Tcr6RETzbcSMWtFkgzMD8EyiwxGBwMIXEm6tywOYwB0nDocXf2f0r2otqYDG9vXIXE9 3ldYmGyR6y3t2KOh6jiwlv+JaC7tj/31bte8g6XwRfyEXQO3jDi2jKzNaZtCJ1yjLVEV QDbBYVQgQBODQSknHfUvRjKcunkJaZmXZYtoUMkA6Oiiq7YF0lBA1qQCCNmfGcJqxKpa GiA7OKe76b7BTvRZwXxbGzDVE7B824cX3pS4qolYk4kLxoauBaEeitCb3iGP39G1y68w X28w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IqGNIGYeYxIliLJN1uLbXaji79hnCldokJEYbv+GISM=; b=kALYPgsWzFa0CPP5OqJc1PJOLIDuoIKhKSqod3eunTWC/oinlVSIX5CCqlyWM5MUKc iV4SDpBNmjJYRjL2YLFWOLksxypFc6rKp6Zq/Cj4PePihKKRa0vv/HHOcUvyL3Cxwcag TL5xbPk+z1QxFGC7i+R2PtU+gfNzEFK3yKMWYyPA2j3yjuzdfAk+osbaQwJGxOLYTdDx V1TfPOYan3vnV5LPvZFnArAkFcfI0RKrE6jZE/8ODVe9d23KrTo/PH943Y25X1DT/pKs 5GBCDKu5WIBCxdjci9zqRJbb5raP/6deXx9CP5c39Nm4J7VKf6EFKDF8VFfhZPr3hy1K LN5w== X-Gm-Message-State: APjAAAWXw2+554vtB34Uy+Phi7I7cf23gE2joaGnV/+EH6lkIE9bb9tP 5q+pV4dOZsW+YJY+HMvTqokOo777QJ09zA== X-Google-Smtp-Source: APXvYqy/hm2G3nu9vo9rp21IWDgnB3HmSKPJdEzTrZnBfJcVn+cL9kWruJxQZyQkpe7rGOyyz70tUQ== X-Received: by 2002:a1c:f00a:: with SMTP id a10mr16480746wmb.89.1571069126074; Mon, 14 Oct 2019 09:05:26 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 50/68] hw: wdt_aspeed: Add AST2600 support Date: Mon, 14 Oct 2019 17:03:46 +0100 Message-Id: <20191014160404.19553-51-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191014160404.19553-1-peter.maydell@linaro.org> References: <20191014160404.19553-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::334 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Joel Stanley The AST2600 has four watchdogs, and they each have a 0x40 of registers. When running as part of an ast2600 system we must check a different offset for the system reset control register in the SCU. Signed-off-by: Joel Stanley Signed-off-by: C=C3=A9dric Le Goater Message-id: 20190925143248.10000-12-clg@kaod.org [clg: - reworked model integration into new object class ] Signed-off-by: C=C3=A9dric Le Goater Signed-off-by: Peter Maydell --- include/hw/arm/aspeed_soc.h | 2 +- include/hw/watchdog/wdt_aspeed.h | 1 + hw/watchdog/wdt_aspeed.c | 29 +++++++++++++++++++++++++++++ 3 files changed, 31 insertions(+), 1 deletion(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index ba5bbb53e1a..b427f2668a8 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -27,7 +27,7 @@ #include "hw/sd/aspeed_sdhci.h" =20 #define ASPEED_SPIS_NUM 2 -#define ASPEED_WDTS_NUM 3 +#define ASPEED_WDTS_NUM 4 #define ASPEED_CPUS_NUM 2 #define ASPEED_MACS_NUM 2 =20 diff --git a/include/hw/watchdog/wdt_aspeed.h b/include/hw/watchdog/wdt_asp= eed.h index 796342764e2..dfedd7662dd 100644 --- a/include/hw/watchdog/wdt_aspeed.h +++ b/include/hw/watchdog/wdt_aspeed.h @@ -18,6 +18,7 @@ OBJECT_CHECK(AspeedWDTState, (obj), TYPE_ASPEED_WDT) #define TYPE_ASPEED_2400_WDT TYPE_ASPEED_WDT "-ast2400" #define TYPE_ASPEED_2500_WDT TYPE_ASPEED_WDT "-ast2500" +#define TYPE_ASPEED_2600_WDT TYPE_ASPEED_WDT "-ast2600" =20 #define ASPEED_WDT_REGS_MAX (0x20 / 4) =20 diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c index fc0e6c486a7..145be6f99ce 100644 --- a/hw/watchdog/wdt_aspeed.c +++ b/hw/watchdog/wdt_aspeed.c @@ -40,12 +40,14 @@ #define WDT_DRIVE_TYPE_MASK (0xFF << 24) #define WDT_PUSH_PULL_MAGIC (0xA8 << 24) #define WDT_OPEN_DRAIN_MAGIC (0x8A << 24) +#define WDT_RESET_MASK1 (0x1c / 4) =20 #define WDT_TIMEOUT_STATUS (0x10 / 4) #define WDT_TIMEOUT_CLEAR (0x14 / 4) =20 #define WDT_RESTART_MAGIC 0x4755 =20 +#define AST2600_SCU_RESET_CONTROL1 (0x40 / 4) #define SCU_RESET_CONTROL1 (0x04 / 4) #define SCU_RESET_SDRAM BIT(0) =20 @@ -74,6 +76,8 @@ static uint64_t aspeed_wdt_read(void *opaque, hwaddr offs= et, unsigned size) return s->regs[WDT_CTRL]; case WDT_RESET_WIDTH: return s->regs[WDT_RESET_WIDTH]; + case WDT_RESET_MASK1: + return s->regs[WDT_RESET_MASK1]; case WDT_TIMEOUT_STATUS: case WDT_TIMEOUT_CLEAR: qemu_log_mask(LOG_UNIMP, @@ -146,6 +150,11 @@ static void aspeed_wdt_write(void *opaque, hwaddr offs= et, uint64_t data, s->regs[WDT_RESET_WIDTH] |=3D data & awc->ext_pulse_width_mask; break; =20 + case WDT_RESET_MASK1: + /* TODO: implement */ + s->regs[WDT_RESET_MASK1] =3D data; + break; + case WDT_TIMEOUT_STATUS: case WDT_TIMEOUT_CLEAR: qemu_log_mask(LOG_UNIMP, @@ -316,12 +325,32 @@ static const TypeInfo aspeed_2500_wdt_info =3D { .class_init =3D aspeed_2500_wdt_class_init, }; =20 +static void aspeed_2600_wdt_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + AspeedWDTClass *awc =3D ASPEED_WDT_CLASS(klass); + + dc->desc =3D "ASPEED 2600 Watchdog Controller"; + awc->offset =3D 0x40; + awc->ext_pulse_width_mask =3D 0xfffff; /* TODO */ + awc->reset_ctrl_reg =3D AST2600_SCU_RESET_CONTROL1; + awc->reset_pulse =3D aspeed_2500_wdt_reset_pulse; +} + +static const TypeInfo aspeed_2600_wdt_info =3D { + .name =3D TYPE_ASPEED_2600_WDT, + .parent =3D TYPE_ASPEED_WDT, + .instance_size =3D sizeof(AspeedWDTState), + .class_init =3D aspeed_2600_wdt_class_init, +}; + static void wdt_aspeed_register_types(void) { watchdog_add_model(&model); type_register_static(&aspeed_wdt_info); type_register_static(&aspeed_2400_wdt_info); type_register_static(&aspeed_2500_wdt_info); + type_register_static(&aspeed_2600_wdt_info); } =20 type_init(wdt_aspeed_register_types) --=20 2.20.1