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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id 5sm18029779wrk.86.2019.10.14.09.04.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Oct 2019 09:04:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=/9+N4KRIkIC7AplGQHDw+bqwPBeiJl0AKn35kS9i8E4=; b=y+s8HoN5IHuYd1Fha2waiFu7ngg0IG3H+wRp8GL8llYmUDbfyEqWlkXez+9/t2/9VI SbKdpl/ziPT9jsXcEvJJ84u6Ifz+snDuPAErIqMqAbAOVhX6DHL6k1Aqx5vJq5oUWd8Q Us/BsPSaGC44GkMeEiCt7CIPjRj8Hm9y/19qcF6eTmP6XoQ6emGU3twsiNv/nVXXlgTu DD1P6TSJ+clOJf4NwZAsTmBgNYxY8TJyVG1ZabFMuXcppIf7Bu0bzgvbVMn1P13MYLLZ WzuEcYUElApUU96Nq41WpTp3bG5t+Y7zmofYP7jLxdUssumx1ZG80e5AK5uN0vpNmFdf qHtQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/9+N4KRIkIC7AplGQHDw+bqwPBeiJl0AKn35kS9i8E4=; b=Qjluhcl7AHzEKZBv4A0QSODuxCoWK5EZYHLkYMStEP/aGylYb3jSy0cNDURngkVb4j VZM1zhGWWOLVkFrlKfWylw6HzxCmtZ3nLFeV/KOTgNatBNT+/KyqqUjSjMUT9CSVQMOh zXG3Kt1sWqe4d2bZUNMrkGhnevKJtJePr9AC/9DC6TTVtjZbyBbKlqIa8jOV5G348ePm Shz1qPNggJ+A7u+v5F4TBSkLOKKaHYWPnZW5PP+ANSz8kMVEAVZEbsMi/TUBP6ffiY3g Ye9DkjKefnZk6FTkGyWssNk6MdZa1/3Y9yQNVt8CIz86R258POE6oipK761KjBCjpLQd 4bHA== X-Gm-Message-State: APjAAAVPUcEMrWfnfJ2M4UGUMzpVqX4jSf1aIddgufL6ncTB22ZGZ3iS WZsx3yh3Po0ACA5if7pxtzmJFwZu7NlqSA== X-Google-Smtp-Source: APXvYqyBkUcpHnWWKrk4oESQ45nFTt+VhFESwe3aiv51fb9U3IONQFqLSbLS+z0KqPIypjBhusODSQ== X-Received: by 2002:a5d:6709:: with SMTP id o9mr26271482wru.116.1571069069952; Mon, 14 Oct 2019 09:04:29 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/68] hw/timer/arm_mptimer.c: Switch to transaction-based ptimer API Date: Mon, 14 Oct 2019 17:03:06 +0100 Message-Id: <20191014160404.19553-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191014160404.19553-1-peter.maydell@linaro.org> References: <20191014160404.19553-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Switch the arm_mptimer.c code away from bottom-half based ptimers to the new transaction-based ptimer API. This just requires adding begin/commit calls around the various places that modify the ptimer state, and using the new ptimer_init() function to create the timer. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20191008171740.9679-8-peter.maydell@linaro.org --- hw/timer/arm_mptimer.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/hw/timer/arm_mptimer.c b/hw/timer/arm_mptimer.c index 2a54a011431..fdf97d1800f 100644 --- a/hw/timer/arm_mptimer.c +++ b/hw/timer/arm_mptimer.c @@ -27,7 +27,6 @@ #include "hw/timer/arm_mptimer.h" #include "migration/vmstate.h" #include "qapi/error.h" -#include "qemu/main-loop.h" #include "qemu/module.h" #include "hw/core/cpu.h" =20 @@ -65,6 +64,7 @@ static inline uint32_t timerblock_scale(uint32_t control) return (((control >> 8) & 0xff) + 1) * 10; } =20 +/* Must be called within a ptimer transaction block */ static inline void timerblock_set_count(struct ptimer_state *timer, uint32_t control, uint64_t *count) { @@ -77,6 +77,7 @@ static inline void timerblock_set_count(struct ptimer_sta= te *timer, ptimer_set_count(timer, *count); } =20 +/* Must be called within a ptimer transaction block */ static inline void timerblock_run(struct ptimer_state *timer, uint32_t control, uint32_t load) { @@ -124,6 +125,7 @@ static void timerblock_write(void *opaque, hwaddr addr, uint32_t control =3D tb->control; switch (addr) { case 0: /* Load */ + ptimer_transaction_begin(tb->timer); /* Setting load to 0 stops the timer without doing the tick if * prescaler =3D 0. */ @@ -132,8 +134,10 @@ static void timerblock_write(void *opaque, hwaddr addr, } ptimer_set_limit(tb->timer, value, 1); timerblock_run(tb->timer, control, value); + ptimer_transaction_commit(tb->timer); break; case 4: /* Counter. */ + ptimer_transaction_begin(tb->timer); /* Setting counter to 0 stops the one-shot timer, or periodic with * load =3D 0, without doing the tick if prescaler =3D 0. */ @@ -143,8 +147,10 @@ static void timerblock_write(void *opaque, hwaddr addr, } timerblock_set_count(tb->timer, control, &value); timerblock_run(tb->timer, control, value); + ptimer_transaction_commit(tb->timer); break; case 8: /* Control. */ + ptimer_transaction_begin(tb->timer); if ((control & 3) !=3D (value & 3)) { ptimer_stop(tb->timer); } @@ -160,6 +166,7 @@ static void timerblock_write(void *opaque, hwaddr addr, timerblock_run(tb->timer, value, count); } tb->control =3D value; + ptimer_transaction_commit(tb->timer); break; case 12: /* Interrupt status. */ tb->status &=3D ~value; @@ -212,9 +219,11 @@ static void timerblock_reset(TimerBlock *tb) tb->control =3D 0; tb->status =3D 0; if (tb->timer) { + ptimer_transaction_begin(tb->timer); ptimer_stop(tb->timer); ptimer_set_limit(tb->timer, 0, 1); ptimer_set_period(tb->timer, timerblock_scale(0)); + ptimer_transaction_commit(tb->timer); } } =20 @@ -260,8 +269,7 @@ static void arm_mptimer_realize(DeviceState *dev, Error= **errp) */ for (i =3D 0; i < s->num_cpu; i++) { TimerBlock *tb =3D &s->timerblock[i]; - QEMUBH *bh =3D qemu_bh_new(timerblock_tick, tb); - tb->timer =3D ptimer_init_with_bh(bh, PTIMER_POLICY); + tb->timer =3D ptimer_init(timerblock_tick, tb, PTIMER_POLICY); sysbus_init_irq(sbd, &tb->irq); memory_region_init_io(&tb->iomem, OBJECT(s), &timerblock_ops, tb, "arm_mptimer_timerblock", 0x20); --=20 2.20.1