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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 18/23] tcg/ppc: Update vector support for v2.07 VSX
Date: Sun, 13 Oct 2019 15:25:39 -0700
Message-Id: <20191013222544.3679-19-richard.henderson@linaro.org>
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These new instructions are conditional only on MSR.VSX and
are thus part of the VSX instruction set, and not Altivec.
This includes double-word loads and stores.
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/ppc/tcg-target.inc.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index bc3a669cb4..6321e0767f 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -470,10 +470,12 @@ static int tcg_target_const_match(tcg_target_long val=
, TCGType type,
#define LVEWX XO31(71)
#define LXSDX (XO31(588) | 1) /* v2.06, force tx=3D1 */
#define LXVDSX (XO31(332) | 1) /* v2.06, force tx=3D1 */
+#define LXSIWZX (XO31(12) | 1) /* v2.07, force tx=3D1 */
=20
#define STVX XO31(231)
#define STVEWX XO31(199)
#define STXSDX (XO31(716) | 1) /* v2.06, force sx=3D1 */
+#define STXSIWX (XO31(140) | 1) /* v2.07, force sx=3D1 */
=20
#define VADDSBS VX4(768)
#define VADDUBS VX4(512)
@@ -1156,6 +1158,10 @@ static void tcg_out_ld(TCGContext *s, TCGType type, =
TCGReg ret,
tcg_out_mem_long(s, LWZ, LWZX, ret, base, offset);
break;
}
+ if (have_isa_2_07 && have_vsx) {
+ tcg_out_mem_long(s, 0, LXSIWZX, ret, base, offset);
+ break;
+ }
tcg_debug_assert((offset & 3) =3D=3D 0);
tcg_out_mem_long(s, 0, LVEWX, ret, base, offset);
shift =3D (offset - 4) & 0xc;
@@ -1203,6 +1209,11 @@ static void tcg_out_st(TCGContext *s, TCGType type, =
TCGReg arg,
tcg_out_mem_long(s, STW, STWX, arg, base, offset);
break;
}
+ if (have_isa_2_07 && have_vsx) {
+ tcg_out_mem_long(s, 0, STXSIWX, arg, base, offset);
+ break;
+ }
+ assert((offset & 3) =3D=3D 0);
tcg_debug_assert((offset & 3) =3D=3D 0);
shift =3D (offset - 4) & 0xc;
if (shift) {
--=20
2.17.1