From nobody Tue Feb 10 06:58:29 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1570810150; cv=none; d=zoho.com; s=zohoarc; b=MN9+shfA7iQSiy3TcCCcsBzozD7qCVvUqxMSyxtnhl8wqK3tSoasVZ88dr+A18Y7k4Rc1PxoOOFL8vyoQONDVLwd+ardomXovThi6JBVv3VYJXudtc7Xz2B/mIIOyZ0sgOWdfXUpYSF9kIhaYXrVzdKXcDTjyCkDyJghzgyXfus= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1570810150; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=4OOGMGav7WyY+i6Vj46PkAX7nW+w3pL8v7F+DMrUq7Y=; b=kkCxqes0FmtuvFt8kUC+iuR69KU4HFyCBmPXdKIYsO2F8uf1ysyqEko5HKSPmdtITCT1gvENyeSdtm+LWYe2aCigzBCQp6rIclmyGrbS4OCkqGEXRAhimpl0ephLDItUFbRlQhiwkSjefmYS5A7HaKxBEHITPu4Uor+hpsgLXCw= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1570810149964843.2614548761853; Fri, 11 Oct 2019 09:09:09 -0700 (PDT) Received: from localhost ([::1]:53394 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iIxTY-00017t-Dq for importer@patchew.org; Fri, 11 Oct 2019 12:09:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33787) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iIxGt-0002W1-AE for qemu-devel@nongnu.org; Fri, 11 Oct 2019 11:56:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iIxGs-0007is-2p for qemu-devel@nongnu.org; Fri, 11 Oct 2019 11:56:03 -0400 Received: from mail-yw1-xc44.google.com ([2607:f8b0:4864:20::c44]:36711) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iIxGr-0007iD-VW for qemu-devel@nongnu.org; Fri, 11 Oct 2019 11:56:02 -0400 Received: by mail-yw1-xc44.google.com with SMTP id x64so3651768ywg.3 for ; Fri, 11 Oct 2019 08:56:01 -0700 (PDT) Received: from cloudburst.gateway.pace.com (67.216.151.25.pool.hargray.net. [67.216.151.25]) by smtp.gmail.com with ESMTPSA id d17sm2473139ywb.95.2019.10.11.08.55.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Oct 2019 08:56:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4OOGMGav7WyY+i6Vj46PkAX7nW+w3pL8v7F+DMrUq7Y=; b=aILbN6xZ30EdzU7O9mibwUqzEqS2SYXFObkfEjAJZKVPFnRsKsQ7cLSrGAVHICGR4V y3o7gQPy64gjZJ4lN1GLaHIvu5Gf0AQKQp2Kwnd4hPC4LOoeQj0mDoHM0iTZOxSKp79r oKAobjVm6JkBKqFytkWOtvdf/hVVug3pjTQpSpYwLwbi31tVKZsDJg7ocTjwNGL9IMgD 6Vhs/FsABJEFrTFGsKOCCezZDFf9xrpTXRJh+VkzdHmM2YRkCVblHLmFg9nIkmj8nNdj r+/SnYZvW3gGRxeKHEts9pWMhMSsxF7ig26z4IRTkj+4733JmWbcfLjwag+9/wtvfBTI lwJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4OOGMGav7WyY+i6Vj46PkAX7nW+w3pL8v7F+DMrUq7Y=; b=HDbSdpVcYTRwoF4AoThNyJBdnKGPsu7xoTf6GSlelY5yMkEHZn8PdmC91VUXBxVUGd NuEm/gdvNFjaE15jh1jLwz98mLDBPeW8uFxchbNLs2716numavHVzJwZQXDJWYymUPp8 yHSgN/ecFLVYfUKWBEWmnn/9bTP8tgUYQIzQa70kSgcrv6Ya5kJGHQmDXNGmuAWmpi6e Ab/bcHHHQU7J3mIaGmHRaRrn7Rp6VBx8MxbZcm7tic1On51vYTeZ0FvCN9IFNpoKoSR9 1dLiW19dD8z1vibGri+h+UvuShqntoetiAu5mQ6k1rHOeZyH/MRDS936upej8ETfD36w Yrow== X-Gm-Message-State: APjAAAXGsoOSfZ2xUrNSbVgJONwvTS19+gB51vSZTH4JVRhLFxzPL6bE qUKv7+kG8n6aWJdmySMnw76SyPkM0Ak= X-Google-Smtp-Source: APXvYqwHLw2/gfnwTQwIIZFwKjz0TnGLJTXYOlE8nNeeG5UP5SCUJBCwldg/tpfyZvnmrUSQOg0EDQ== X-Received: by 2002:a0d:d384:: with SMTP id v126mr2818553ywd.166.1570809360832; Fri, 11 Oct 2019 08:56:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 11/20] target/arm: Hoist computation of TBFLAG_A32.VFPEN Date: Fri, 11 Oct 2019 11:55:37 -0400 Message-Id: <20191011155546.14342-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191011155546.14342-1-richard.henderson@linaro.org> References: <20191011155546.14342-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::c44 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.desnogues@gmail.com, peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" There are 3 conditions that each enable this flag. M-profile always enables; A-profile with EL1 as AA64 always enables. Both of these conditions can easily be cached. The final condition relies on the FPEXC register which we are not prepared to cache. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- target/arm/cpu.h | 2 +- target/arm/helper.c | 14 ++++++++++---- 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 4d961474ce..9909ff89d4 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3192,7 +3192,7 @@ FIELD(TBFLAG_A32, XSCALE_CPAR, 4, 2) * the same thing as the current security state of the processor! */ FIELD(TBFLAG_A32, NS, 6, 1) -FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Not cached. */ +FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. = */ FIELD(TBFLAG_A32, CONDEXEC, 8, 8) /* Not cached. */ FIELD(TBFLAG_A32, SCTLR_B, 16, 1) /* For M profile only, set if FPCCR.LSPACT is set */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 398e5f5d6d..89aa6fd933 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11088,6 +11088,9 @@ static uint32_t rebuild_hflags_m32(CPUARMState *env= , int fp_el, { uint32_t flags =3D 0; =20 + /* v8M always enables the fpu. */ + flags =3D FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); + if (arm_v7m_is_handler_mode(env)) { flags =3D FIELD_DP32(flags, TBFLAG_A32, HANDLER, 1); } @@ -11119,6 +11122,10 @@ static uint32_t rebuild_hflags_a32(CPUARMState *en= v, int fp_el, ARMMMUIdx mmu_idx) { uint32_t flags =3D rebuild_hflags_aprofile(env); + + if (arm_el_is_aa64(env, 1)) { + flags =3D FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); + } return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); } =20 @@ -11250,14 +11257,13 @@ void cpu_get_tb_cpu_state(CPUARMState *env, targe= t_ulong *pc, flags =3D FIELD_DP32(flags, TBFLAG_A32, VECSTRIDE, env->vfp.vec_stride); } + if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) { + flags =3D FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); + } } =20 flags =3D FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); flags =3D FIELD_DP32(flags, TBFLAG_A32, CONDEXEC, env->condexec_bi= ts); - if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30) - || arm_el_is_aa64(env, 1) || arm_feature(env, ARM_FEATURE_M)) { - flags =3D FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); - } pstate_for_ss =3D env->uncached_cpsr; } =20 --=20 2.17.1