From nobody Sun May 19 01:43:06 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1570784306; cv=none; d=zoho.com; s=zohoarc; b=oZD6ecxMjwVhLSM0Ha8TBQ4tJbCUxxMzK5A4AZ48yhMD3qS1uS+nfUxo2qfNuSRcQMJetUZ58eLY1cpVROTbFWBr6WmHPG7IIE6/ZNkwqqiV99RCQ885LBV8xxYpAfcAmni4nzT5sxmA6JlvUJyZopUNKpSeERL8ALdYBAxqqqA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1570784306; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=mm53B5ZfYGBTZoN3pu9GHsvqrhtrbf+vxroFHBUhiJo=; b=H9SVFwDx2BnoxQV8E+J3MbD9nOdMuBEOJ5a1n5FYs84ZmY66pWXu08wcfvh7zR8nh4dYTurcgpFq6RWIxSA5I5EGy4GDEBRQTBN4k6TwIRshf4KbKdlygM5LwuHHU4zqKXkjtXGoqb/v2x7eHlTf+7H9RN72QVEAGkp63A9Jolw= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1570784306149649.962557884493; Fri, 11 Oct 2019 01:58:26 -0700 (PDT) Received: from localhost ([::1]:47442 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iIqki-00058H-TP for importer@patchew.org; Fri, 11 Oct 2019 04:58:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47540) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iIqil-0002ZZ-En for qemu-devel@nongnu.org; Fri, 11 Oct 2019 04:56:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iIqik-0007ia-6S for qemu-devel@nongnu.org; Fri, 11 Oct 2019 04:56:23 -0400 Received: from mx1.redhat.com ([209.132.183.28]:50414) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iIqij-0007hq-V2 for qemu-devel@nongnu.org; Fri, 11 Oct 2019 04:56:22 -0400 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 343CC3082DDD for ; Fri, 11 Oct 2019 08:56:21 +0000 (UTC) Received: from localhost (unknown [10.36.118.109]) by smtp.corp.redhat.com (Postfix) with ESMTP id B9BF360BE1; Fri, 11 Oct 2019 08:56:20 +0000 (UTC) From: Stefan Hajnoczi To: qemu-devel@nongnu.org Subject: [PATCH v2 1/7] libqos: extract Legacy virtio-pci.c code Date: Fri, 11 Oct 2019 09:56:05 +0100 Message-Id: <20191011085611.4194-2-stefanha@redhat.com> In-Reply-To: <20191011085611.4194-1-stefanha@redhat.com> References: <20191011085611.4194-1-stefanha@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.46]); Fri, 11 Oct 2019 08:56:21 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Paolo Bonzini , Thomas Huth , Stefan Hajnoczi , "Michael S. Tsirkin" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The current libqos virtio-pci.c code implements the VIRTIO Legacy interface. Extract existing code in preparation for VIRTIO 1.0 support. Signed-off-by: Stefan Hajnoczi Reviewed-by: Sergio Lopez Reviewed-by: Thomas Huth --- tests/libqos/virtio-pci.h | 2 -- tests/libqos/virtio-pci.c | 25 ++++++++++--------------- 2 files changed, 10 insertions(+), 17 deletions(-) diff --git a/tests/libqos/virtio-pci.h b/tests/libqos/virtio-pci.h index 728b4715f1..0d105d67b3 100644 --- a/tests/libqos/virtio-pci.h +++ b/tests/libqos/virtio-pci.h @@ -31,8 +31,6 @@ typedef struct QVirtQueuePCI { uint32_t msix_data; } QVirtQueuePCI; =20 -extern const QVirtioBus qvirtio_pci; - void virtio_pci_init(QVirtioPCIDevice *dev, QPCIBus *bus, QPCIAddress * ad= dr); QVirtioPCIDevice *virtio_pci_new(QPCIBus *bus, QPCIAddress * addr); =20 diff --git a/tests/libqos/virtio-pci.c b/tests/libqos/virtio-pci.c index 50499e75ef..c8d736f4d1 100644 --- a/tests/libqos/virtio-pci.c +++ b/tests/libqos/virtio-pci.c @@ -35,14 +35,6 @@ * original qvirtio_pci_destructor and qvirtio_pci_start_hw. */ =20 -static inline bool qvirtio_pci_is_big_endian(QVirtioPCIDevice *dev) -{ - QPCIBus *bus =3D dev->pdev->bus; - - /* FIXME: virtio 1.0 is always little-endian */ - return qtest_big_endian(bus->qts); -} - #define CONFIG_BASE(dev) (VIRTIO_PCI_CONFIG_OFF((dev)->pdev->msix_enabled)) =20 static uint8_t qvirtio_pci_config_readb(QVirtioDevice *d, uint64_t off) @@ -55,8 +47,7 @@ static uint8_t qvirtio_pci_config_readb(QVirtioDevice *d,= uint64_t off) * but virtio ( < 1.0) is in guest order * so with a big-endian guest the order has been reversed, * reverse it again - * virtio-1.0 is always little-endian, like PCI, but this - * case will be managed inside qvirtio_pci_is_big_endian() + * virtio-1.0 is always little-endian, like PCI */ =20 static uint16_t qvirtio_pci_config_readw(QVirtioDevice *d, uint64_t off) @@ -258,7 +249,7 @@ static void qvirtio_pci_virtqueue_kick(QVirtioDevice *d= , QVirtQueue *vq) qpci_io_writew(dev->pdev, dev->bar, VIRTIO_PCI_QUEUE_NOTIFY, vq->index= ); } =20 -const QVirtioBus qvirtio_pci =3D { +static const QVirtioBus qvirtio_pci_legacy =3D { .config_readb =3D qvirtio_pci_config_readb, .config_readw =3D qvirtio_pci_config_readw, .config_readl =3D qvirtio_pci_config_readl, @@ -374,15 +365,19 @@ void qvirtio_pci_start_hw(QOSGraphObject *obj) qvirtio_start_device(&dev->vdev); } =20 +static void qvirtio_pci_init_legacy(QVirtioPCIDevice *dev) +{ + dev->vdev.device_type =3D qpci_config_readw(dev->pdev, PCI_SUBSYSTEM_I= D); + dev->vdev.bus =3D &qvirtio_pci_legacy; + dev->vdev.big_endian =3D qtest_big_endian(dev->pdev->bus->qts); +} + static void qvirtio_pci_init_from_pcidev(QVirtioPCIDevice *dev, QPCIDevice= *pci_dev) { dev->pdev =3D pci_dev; - dev->vdev.device_type =3D qpci_config_readw(pci_dev, PCI_SUBSYSTEM_ID); - dev->config_msix_entry =3D -1; =20 - dev->vdev.bus =3D &qvirtio_pci; - dev->vdev.big_endian =3D qvirtio_pci_is_big_endian(dev); + qvirtio_pci_init_legacy(dev); =20 /* each virtio-xxx-pci device should override at least this function */ dev->obj.get_driver =3D NULL; --=20 2.21.0 From nobody Sun May 19 01:43:06 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; 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Fri, 11 Oct 2019 04:56:28 -0400 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 5524D10C0930 for ; Fri, 11 Oct 2019 08:56:27 +0000 (UTC) Received: from localhost (unknown [10.36.118.109]) by smtp.corp.redhat.com (Postfix) with ESMTP id 60BEA5D9C3; Fri, 11 Oct 2019 08:56:22 +0000 (UTC) From: Stefan Hajnoczi To: qemu-devel@nongnu.org Subject: [PATCH v2 2/7] libqos: add iteration support to qpci_find_capability() Date: Fri, 11 Oct 2019 09:56:06 +0100 Message-Id: <20191011085611.4194-3-stefanha@redhat.com> In-Reply-To: <20191011085611.4194-1-stefanha@redhat.com> References: <20191011085611.4194-1-stefanha@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.6.2 (mx1.redhat.com [10.5.110.66]); Fri, 11 Oct 2019 08:56:27 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Paolo Bonzini , Thomas Huth , Stefan Hajnoczi , "Michael S. Tsirkin" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" VIRTIO 1.0 PCI devices have multiple PCI_CAP_ID_VNDR capabilities so we need a way to iterate over them. Extend qpci_find_capability() to take the last address. Signed-off-by: Stefan Hajnoczi Reviewed-by: Sergio Lopez Reviewed-by: Thomas Huth --- tests/libqos/pci.h | 2 +- tests/libqos/pci.c | 18 ++++++++++++------ 2 files changed, 13 insertions(+), 7 deletions(-) diff --git a/tests/libqos/pci.h b/tests/libqos/pci.h index a5389a5845..590c175190 100644 --- a/tests/libqos/pci.h +++ b/tests/libqos/pci.h @@ -86,7 +86,7 @@ bool qpci_has_buggy_msi(QPCIDevice *dev); bool qpci_check_buggy_msi(QPCIDevice *dev); =20 void qpci_device_enable(QPCIDevice *dev); -uint8_t qpci_find_capability(QPCIDevice *dev, uint8_t id); +uint8_t qpci_find_capability(QPCIDevice *dev, uint8_t id, uint8_t start_ad= dr); void qpci_msix_enable(QPCIDevice *dev); void qpci_msix_disable(QPCIDevice *dev); bool qpci_msix_pending(QPCIDevice *dev, uint16_t entry); diff --git a/tests/libqos/pci.c b/tests/libqos/pci.c index 662ee7a517..b8679dff1d 100644 --- a/tests/libqos/pci.c +++ b/tests/libqos/pci.c @@ -115,10 +115,16 @@ void qpci_device_enable(QPCIDevice *dev) g_assert_cmphex(cmd & PCI_COMMAND_MASTER, =3D=3D, PCI_COMMAND_MASTER); } =20 -uint8_t qpci_find_capability(QPCIDevice *dev, uint8_t id) +uint8_t qpci_find_capability(QPCIDevice *dev, uint8_t id, uint8_t start_ad= dr) { uint8_t cap; - uint8_t addr =3D qpci_config_readb(dev, PCI_CAPABILITY_LIST); + uint8_t addr; + + if (start_addr) { + addr =3D qpci_config_readb(dev, start_addr + PCI_CAP_LIST_NEXT); + } else { + addr =3D qpci_config_readb(dev, PCI_CAPABILITY_LIST); + } =20 do { cap =3D qpci_config_readb(dev, addr); @@ -138,7 +144,7 @@ void qpci_msix_enable(QPCIDevice *dev) uint8_t bir_table; uint8_t bir_pba; =20 - addr =3D qpci_find_capability(dev, PCI_CAP_ID_MSIX); + addr =3D qpci_find_capability(dev, PCI_CAP_ID_MSIX, 0); g_assert_cmphex(addr, !=3D, 0); =20 val =3D qpci_config_readw(dev, addr + PCI_MSIX_FLAGS); @@ -167,7 +173,7 @@ void qpci_msix_disable(QPCIDevice *dev) uint16_t val; =20 g_assert(dev->msix_enabled); - addr =3D qpci_find_capability(dev, PCI_CAP_ID_MSIX); + addr =3D qpci_find_capability(dev, PCI_CAP_ID_MSIX, 0); g_assert_cmphex(addr, !=3D, 0); val =3D qpci_config_readw(dev, addr + PCI_MSIX_FLAGS); qpci_config_writew(dev, addr + PCI_MSIX_FLAGS, @@ -203,7 +209,7 @@ bool qpci_msix_masked(QPCIDevice *dev, uint16_t entry) uint64_t vector_off =3D dev->msix_table_off + entry * PCI_MSIX_ENTRY_S= IZE; =20 g_assert(dev->msix_enabled); - addr =3D qpci_find_capability(dev, PCI_CAP_ID_MSIX); + addr =3D qpci_find_capability(dev, PCI_CAP_ID_MSIX, 0); g_assert_cmphex(addr, !=3D, 0); val =3D qpci_config_readw(dev, addr + PCI_MSIX_FLAGS); =20 @@ -221,7 +227,7 @@ uint16_t qpci_msix_table_size(QPCIDevice *dev) uint8_t addr; uint16_t control; =20 - addr =3D qpci_find_capability(dev, PCI_CAP_ID_MSIX); + addr =3D qpci_find_capability(dev, PCI_CAP_ID_MSIX, 0); g_assert_cmphex(addr, !=3D, 0); =20 control =3D qpci_config_readw(dev, addr + PCI_MSIX_FLAGS); --=20 2.21.0 From nobody Sun May 19 01:43:06 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Fri, 11 Oct 2019 04:56:36 -0400 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 21E7E8AC6FD for ; Fri, 11 Oct 2019 08:56:35 +0000 (UTC) Received: from localhost (unknown [10.36.118.109]) by smtp.corp.redhat.com (Postfix) with ESMTP id B62CA10013D9; Fri, 11 Oct 2019 08:56:28 +0000 (UTC) From: Stefan Hajnoczi To: qemu-devel@nongnu.org Subject: [PATCH v2 3/7] libqos: pass full QVirtQueue to set_queue_address() Date: Fri, 11 Oct 2019 09:56:07 +0100 Message-Id: <20191011085611.4194-4-stefanha@redhat.com> In-Reply-To: <20191011085611.4194-1-stefanha@redhat.com> References: <20191011085611.4194-1-stefanha@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.6.2 (mx1.redhat.com [10.5.110.69]); Fri, 11 Oct 2019 08:56:35 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Paolo Bonzini , Thomas Huth , Stefan Hajnoczi , "Michael S. Tsirkin" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Instead of just passing the vring page frame number, pass the full QVirtQueue. This will allow the VIRTIO 1.0 transport to program the fine-grained vring address registers in the future. Signed-off-by: Stefan Hajnoczi Reviewed-by: Sergio Lopez Reviewed-by: Thomas Huth --- tests/libqos/virtio.h | 2 +- tests/libqos/virtio-mmio.c | 6 ++++-- tests/libqos/virtio-pci.c | 6 ++++-- 3 files changed, 9 insertions(+), 5 deletions(-) diff --git a/tests/libqos/virtio.h b/tests/libqos/virtio.h index 2cb2448f46..37f55b6ade 100644 --- a/tests/libqos/virtio.h +++ b/tests/libqos/virtio.h @@ -79,7 +79,7 @@ struct QVirtioBus { uint16_t (*get_queue_size)(QVirtioDevice *d); =20 /* Set the address of the selected queue */ - void (*set_queue_address)(QVirtioDevice *d, uint32_t pfn); + void (*set_queue_address)(QVirtioDevice *d, QVirtQueue *vq); =20 /* Setup the virtqueue specified by index */ QVirtQueue *(*virtqueue_setup)(QVirtioDevice *d, QGuestAllocator *allo= c, diff --git a/tests/libqos/virtio-mmio.c b/tests/libqos/virtio-mmio.c index d0047876a8..43ca4e49c1 100644 --- a/tests/libqos/virtio-mmio.c +++ b/tests/libqos/virtio-mmio.c @@ -127,9 +127,11 @@ static uint16_t qvirtio_mmio_get_queue_size(QVirtioDev= ice *d) return (uint16_t)qtest_readl(dev->qts, dev->addr + QVIRTIO_MMIO_QUEUE_= NUM_MAX); } =20 -static void qvirtio_mmio_set_queue_address(QVirtioDevice *d, uint32_t pfn) +static void qvirtio_mmio_set_queue_address(QVirtioDevice *d, QVirtQueue *v= q) { QVirtioMMIODevice *dev =3D container_of(d, QVirtioMMIODevice, vdev); + uint64_t pfn =3D vq->desc / dev->page_size; + qtest_writel(dev->qts, dev->addr + QVIRTIO_MMIO_QUEUE_PFN, pfn); } =20 @@ -162,7 +164,7 @@ static QVirtQueue *qvirtio_mmio_virtqueue_setup(QVirtio= Device *d, =20 addr =3D guest_alloc(alloc, qvring_size(vq->size, dev->page_size)); qvring_init(dev->qts, alloc, vq, addr); - qvirtio_mmio_set_queue_address(d, vq->desc / dev->page_size); + qvirtio_mmio_set_queue_address(d, vq); =20 return vq; } diff --git a/tests/libqos/virtio-pci.c b/tests/libqos/virtio-pci.c index c8d736f4d1..4772239b61 100644 --- a/tests/libqos/virtio-pci.c +++ b/tests/libqos/virtio-pci.c @@ -190,9 +190,11 @@ static uint16_t qvirtio_pci_get_queue_size(QVirtioDevi= ce *d) return qpci_io_readw(dev->pdev, dev->bar, VIRTIO_PCI_QUEUE_NUM); } =20 -static void qvirtio_pci_set_queue_address(QVirtioDevice *d, uint32_t pfn) +static void qvirtio_pci_set_queue_address(QVirtioDevice *d, QVirtQueue *vq) { QVirtioPCIDevice *dev =3D container_of(d, QVirtioPCIDevice, vdev); + uint64_t pfn =3D vq->desc / VIRTIO_PCI_VRING_ALIGN; + qpci_io_writel(dev->pdev, dev->bar, VIRTIO_PCI_QUEUE_PFN, pfn); } =20 @@ -229,7 +231,7 @@ static QVirtQueue *qvirtio_pci_virtqueue_setup(QVirtioD= evice *d, addr =3D guest_alloc(alloc, qvring_size(vqpci->vq.size, VIRTIO_PCI_VRING_ALIGN)); qvring_init(qvpcidev->pdev->bus->qts, alloc, &vqpci->vq, addr); - qvirtio_pci_set_queue_address(d, vqpci->vq.desc / VIRTIO_PCI_VRING_ALI= GN); + qvirtio_pci_set_queue_address(d, &vqpci->vq); =20 return &vqpci->vq; } --=20 2.21.0 From nobody Sun May 19 01:43:06 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; 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Fri, 11 Oct 2019 08:56:36 +0000 (UTC) Received: from localhost (unknown [10.36.118.109]) by smtp.corp.redhat.com (Postfix) with ESMTP id 809925D9C3; Fri, 11 Oct 2019 08:56:36 +0000 (UTC) From: Stefan Hajnoczi To: qemu-devel@nongnu.org Subject: [PATCH v2 4/7] libqos: add MSI-X callbacks to QVirtioPCIDevice Date: Fri, 11 Oct 2019 09:56:08 +0100 Message-Id: <20191011085611.4194-5-stefanha@redhat.com> In-Reply-To: <20191011085611.4194-1-stefanha@redhat.com> References: <20191011085611.4194-1-stefanha@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.6.2 (mx1.redhat.com [10.5.110.64]); Fri, 11 Oct 2019 08:56:37 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Paolo Bonzini , Thomas Huth , Stefan Hajnoczi , "Michael S. Tsirkin" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The MSI-X vectors are programmed differently in the VIRTIO 1.0 and Legacy interfaces. Introduce callbacks so different implementations can be used depending on the interface version. Signed-off-by: Stefan Hajnoczi Reviewed-by: Sergio Lopez Reviewed-by: Thomas Huth --- tests/libqos/virtio-pci.h | 12 ++++++++++++ tests/libqos/virtio-pci.c | 37 ++++++++++++++++++++++++++++--------- 2 files changed, 40 insertions(+), 9 deletions(-) diff --git a/tests/libqos/virtio-pci.h b/tests/libqos/virtio-pci.h index 0d105d67b3..443e53affc 100644 --- a/tests/libqos/virtio-pci.h +++ b/tests/libqos/virtio-pci.h @@ -14,16 +14,28 @@ #include "libqos/pci.h" #include "libqos/qgraph.h" =20 +typedef struct QVirtioPCIMSIXOps QVirtioPCIMSIXOps; + typedef struct QVirtioPCIDevice { QOSGraphObject obj; QVirtioDevice vdev; QPCIDevice *pdev; QPCIBar bar; + const QVirtioPCIMSIXOps *msix_ops; uint16_t config_msix_entry; uint64_t config_msix_addr; uint32_t config_msix_data; } QVirtioPCIDevice; =20 +struct QVirtioPCIMSIXOps { + /* Set the Configuration Vector for MSI-X */ + void (*set_config_vector)(QVirtioPCIDevice *d, uint16_t entry); + + /* Set the Queue Vector for MSI-X */ + void (*set_queue_vector)(QVirtioPCIDevice *d, uint16_t vq_idx, + uint16_t entry); +}; + typedef struct QVirtQueuePCI { QVirtQueue vq; uint16_t msix_entry; diff --git a/tests/libqos/virtio-pci.c b/tests/libqos/virtio-pci.c index 4772239b61..651f6dbfc6 100644 --- a/tests/libqos/virtio-pci.c +++ b/tests/libqos/virtio-pci.c @@ -271,6 +271,31 @@ static const QVirtioBus qvirtio_pci_legacy =3D { .virtqueue_kick =3D qvirtio_pci_virtqueue_kick, }; =20 +static void qvirtio_pci_set_config_vector(QVirtioPCIDevice *d, uint16_t en= try) +{ + uint16_t vector; + + qpci_io_writew(d->pdev, d->bar, VIRTIO_MSI_CONFIG_VECTOR, entry); + vector =3D qpci_io_readw(d->pdev, d->bar, VIRTIO_MSI_CONFIG_VECTOR); + g_assert_cmphex(vector, !=3D, VIRTIO_MSI_NO_VECTOR); +} + +static void qvirtio_pci_set_queue_vector(QVirtioPCIDevice *d, uint16_t vq_= idx, + uint16_t entry) +{ + uint16_t vector; + + qvirtio_pci_queue_select(&d->vdev, vq_idx); + qpci_io_writew(d->pdev, d->bar, VIRTIO_MSI_QUEUE_VECTOR, entry); + vector =3D qpci_io_readw(d->pdev, d->bar, VIRTIO_MSI_QUEUE_VECTOR); + g_assert_cmphex(vector, !=3D, VIRTIO_MSI_NO_VECTOR); +} + +static const QVirtioPCIMSIXOps qvirtio_pci_msix_ops_legacy =3D { + .set_config_vector =3D qvirtio_pci_set_config_vector, + .set_queue_vector =3D qvirtio_pci_set_queue_vector, +}; + void qvirtio_pci_device_enable(QVirtioPCIDevice *d) { qpci_device_enable(d->pdev); @@ -285,7 +310,6 @@ void qvirtio_pci_device_disable(QVirtioPCIDevice *d) void qvirtqueue_pci_msix_setup(QVirtioPCIDevice *d, QVirtQueuePCI *vqpci, QGuestAllocator *alloc, uint16_t e= ntry) { - uint16_t vector; uint32_t control; uint64_t off; =20 @@ -311,16 +335,12 @@ void qvirtqueue_pci_msix_setup(QVirtioPCIDevice *d, Q= VirtQueuePCI *vqpci, off + PCI_MSIX_ENTRY_VECTOR_CTRL, control & ~PCI_MSIX_ENTRY_CTRL_MASKBIT); =20 - qvirtio_pci_queue_select(&d->vdev, vqpci->vq.index); - qpci_io_writew(d->pdev, d->bar, VIRTIO_MSI_QUEUE_VECTOR, entry); - vector =3D qpci_io_readw(d->pdev, d->bar, VIRTIO_MSI_QUEUE_VECTOR); - g_assert_cmphex(vector, !=3D, VIRTIO_MSI_NO_VECTOR); + d->msix_ops->set_queue_vector(d, vqpci->vq.index, entry); } =20 void qvirtio_pci_set_msix_configuration_vector(QVirtioPCIDevice *d, QGuestAllocator *alloc, uint16_t e= ntry) { - uint16_t vector; uint32_t control; uint64_t off; =20 @@ -348,9 +368,7 @@ void qvirtio_pci_set_msix_configuration_vector(QVirtioP= CIDevice *d, off + PCI_MSIX_ENTRY_VECTOR_CTRL, control & ~PCI_MSIX_ENTRY_CTRL_MASKBIT); =20 - qpci_io_writew(d->pdev, d->bar, VIRTIO_MSI_CONFIG_VECTOR, entry); - vector =3D qpci_io_readw(d->pdev, d->bar, VIRTIO_MSI_CONFIG_VECTOR); - g_assert_cmphex(vector, !=3D, VIRTIO_MSI_NO_VECTOR); + d->msix_ops->set_config_vector(d, entry); } =20 void qvirtio_pci_destructor(QOSGraphObject *obj) @@ -371,6 +389,7 @@ static void qvirtio_pci_init_legacy(QVirtioPCIDevice *d= ev) { dev->vdev.device_type =3D qpci_config_readw(dev->pdev, PCI_SUBSYSTEM_I= D); dev->vdev.bus =3D &qvirtio_pci_legacy; + dev->msix_ops =3D &qvirtio_pci_msix_ops_legacy; dev->vdev.big_endian =3D qtest_big_endian(dev->pdev->bus->qts); } =20 --=20 2.21.0 From nobody Sun May 19 01:43:06 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Fri, 11 Oct 2019 04:56:44 -0400 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 807C8801662 for ; Fri, 11 Oct 2019 08:56:43 +0000 (UTC) Received: from localhost (unknown [10.36.118.109]) by smtp.corp.redhat.com (Postfix) with ESMTP id 5A0E05C1B2; Fri, 11 Oct 2019 08:56:38 +0000 (UTC) From: Stefan Hajnoczi To: qemu-devel@nongnu.org Subject: [PATCH v2 5/7] libqos: expose common virtqueue setup/cleanup functions Date: Fri, 11 Oct 2019 09:56:09 +0100 Message-Id: <20191011085611.4194-6-stefanha@redhat.com> In-Reply-To: <20191011085611.4194-1-stefanha@redhat.com> References: <20191011085611.4194-1-stefanha@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.6.2 (mx1.redhat.com [10.5.110.67]); Fri, 11 Oct 2019 08:56:43 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Paolo Bonzini , Thomas Huth , Stefan Hajnoczi , "Michael S. Tsirkin" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The VIRTIO 1.0 code will need to perform additional steps but it will reuse the common virtqueue setup/cleanup code. Make these functions public. Make sure to invoke callbacks via QVirtioBus instead of directly calling the virtio-pci Legacy versions of these functions. Signed-off-by: Stefan Hajnoczi Reviewed-by: Sergio Lopez Reviewed-by: Thomas Huth --- tests/libqos/virtio-pci.h | 8 ++++++++ tests/libqos/virtio-pci.c | 19 ++++++++++--------- 2 files changed, 18 insertions(+), 9 deletions(-) diff --git a/tests/libqos/virtio-pci.h b/tests/libqos/virtio-pci.h index 443e53affc..b620c30451 100644 --- a/tests/libqos/virtio-pci.h +++ b/tests/libqos/virtio-pci.h @@ -63,4 +63,12 @@ void qvirtio_pci_set_msix_configuration_vector(QVirtioPC= IDevice *d, QGuestAllocator *alloc, uint16_t e= ntry); void qvirtqueue_pci_msix_setup(QVirtioPCIDevice *d, QVirtQueuePCI *vqpci, QGuestAllocator *alloc, uint16_t e= ntry); + +/* Used by Legacy and Modern virtio-pci code */ +QVirtQueue *qvirtio_pci_virtqueue_setup_common(QVirtioDevice *d, + QGuestAllocator *alloc, + uint16_t index); +void qvirtio_pci_virtqueue_cleanup_common(QVirtQueue *vq, + QGuestAllocator *alloc); + #endif diff --git a/tests/libqos/virtio-pci.c b/tests/libqos/virtio-pci.c index 651f6dbfc6..3fb4af4016 100644 --- a/tests/libqos/virtio-pci.c +++ b/tests/libqos/virtio-pci.c @@ -198,8 +198,9 @@ static void qvirtio_pci_set_queue_address(QVirtioDevice= *d, QVirtQueue *vq) qpci_io_writel(dev->pdev, dev->bar, VIRTIO_PCI_QUEUE_PFN, pfn); } =20 -static QVirtQueue *qvirtio_pci_virtqueue_setup(QVirtioDevice *d, - QGuestAllocator *alloc, uint16_t i= ndex) +QVirtQueue *qvirtio_pci_virtqueue_setup_common(QVirtioDevice *d, + QGuestAllocator *alloc, + uint16_t index) { uint32_t feat; uint64_t addr; @@ -207,11 +208,11 @@ static QVirtQueue *qvirtio_pci_virtqueue_setup(QVirti= oDevice *d, QVirtioPCIDevice *qvpcidev =3D container_of(d, QVirtioPCIDevice, vdev); =20 vqpci =3D g_malloc0(sizeof(*vqpci)); - feat =3D qvirtio_pci_get_guest_features(d); + feat =3D d->bus->get_guest_features(d); =20 - qvirtio_pci_queue_select(d, index); + d->bus->queue_select(d, index); vqpci->vq.index =3D index; - vqpci->vq.size =3D qvirtio_pci_get_queue_size(d); + vqpci->vq.size =3D d->bus->get_queue_size(d); vqpci->vq.free_head =3D 0; vqpci->vq.num_free =3D vqpci->vq.size; vqpci->vq.align =3D VIRTIO_PCI_VRING_ALIGN; @@ -231,12 +232,12 @@ static QVirtQueue *qvirtio_pci_virtqueue_setup(QVirti= oDevice *d, addr =3D guest_alloc(alloc, qvring_size(vqpci->vq.size, VIRTIO_PCI_VRING_ALIGN)); qvring_init(qvpcidev->pdev->bus->qts, alloc, &vqpci->vq, addr); - qvirtio_pci_set_queue_address(d, &vqpci->vq); + d->bus->set_queue_address(d, &vqpci->vq); =20 return &vqpci->vq; } =20 -static void qvirtio_pci_virtqueue_cleanup(QVirtQueue *vq, +void qvirtio_pci_virtqueue_cleanup_common(QVirtQueue *vq, QGuestAllocator *alloc) { QVirtQueuePCI *vqpci =3D container_of(vq, QVirtQueuePCI, vq); @@ -266,8 +267,8 @@ static const QVirtioBus qvirtio_pci_legacy =3D { .queue_select =3D qvirtio_pci_queue_select, .get_queue_size =3D qvirtio_pci_get_queue_size, .set_queue_address =3D qvirtio_pci_set_queue_address, - .virtqueue_setup =3D qvirtio_pci_virtqueue_setup, - .virtqueue_cleanup =3D qvirtio_pci_virtqueue_cleanup, + .virtqueue_setup =3D qvirtio_pci_virtqueue_setup_common, + .virtqueue_cleanup =3D qvirtio_pci_virtqueue_cleanup_common, .virtqueue_kick =3D qvirtio_pci_virtqueue_kick, }; =20 --=20 2.21.0 From nobody Sun May 19 01:43:06 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Fri, 11 Oct 2019 04:56:51 -0400 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 4548630024DA for ; Fri, 11 Oct 2019 08:56:50 +0000 (UTC) Received: from localhost (unknown [10.36.118.109]) by smtp.corp.redhat.com (Postfix) with ESMTP id E228A60872; Fri, 11 Oct 2019 08:56:44 +0000 (UTC) From: Stefan Hajnoczi To: qemu-devel@nongnu.org Subject: [PATCH v2 6/7] libqos: make the virtio-pci BAR index configurable Date: Fri, 11 Oct 2019 09:56:10 +0100 Message-Id: <20191011085611.4194-7-stefanha@redhat.com> In-Reply-To: <20191011085611.4194-1-stefanha@redhat.com> References: <20191011085611.4194-1-stefanha@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.40]); Fri, 11 Oct 2019 08:56:50 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Paolo Bonzini , Thomas Huth , Stefan Hajnoczi , "Michael S. Tsirkin" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The Legacy virtio-pci interface always uses BAR 0. VIRTIO 1.0 may need to use a different BAR index, so make it configurable. Signed-off-by: Stefan Hajnoczi Reviewed-by: Sergio Lopez Reviewed-by: Thomas Huth --- tests/libqos/virtio-pci.h | 2 ++ tests/libqos/virtio-pci.c | 3 ++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/tests/libqos/virtio-pci.h b/tests/libqos/virtio-pci.h index b620c30451..f2d53aa377 100644 --- a/tests/libqos/virtio-pci.h +++ b/tests/libqos/virtio-pci.h @@ -25,6 +25,8 @@ typedef struct QVirtioPCIDevice { uint16_t config_msix_entry; uint64_t config_msix_addr; uint32_t config_msix_data; + + uint8_t bar_idx; } QVirtioPCIDevice; =20 struct QVirtioPCIMSIXOps { diff --git a/tests/libqos/virtio-pci.c b/tests/libqos/virtio-pci.c index 3fb4af4016..efd8caee18 100644 --- a/tests/libqos/virtio-pci.c +++ b/tests/libqos/virtio-pci.c @@ -300,7 +300,7 @@ static const QVirtioPCIMSIXOps qvirtio_pci_msix_ops_leg= acy =3D { void qvirtio_pci_device_enable(QVirtioPCIDevice *d) { qpci_device_enable(d->pdev); - d->bar =3D qpci_iomap(d->pdev, 0, NULL); + d->bar =3D qpci_iomap(d->pdev, d->bar_idx, NULL); } =20 void qvirtio_pci_device_disable(QVirtioPCIDevice *d) @@ -389,6 +389,7 @@ void qvirtio_pci_start_hw(QOSGraphObject *obj) static void qvirtio_pci_init_legacy(QVirtioPCIDevice *dev) { dev->vdev.device_type =3D qpci_config_readw(dev->pdev, PCI_SUBSYSTEM_I= D); + dev->bar_idx =3D 0; dev->vdev.bus =3D &qvirtio_pci_legacy; dev->msix_ops =3D &qvirtio_pci_msix_ops_legacy; dev->vdev.big_endian =3D qtest_big_endian(dev->pdev->bus->qts); --=20 2.21.0 From nobody Sun May 19 01:43:06 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1570784838; 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Fri, 11 Oct 2019 08:56:56 +0000 (UTC) Received: from localhost (unknown [10.36.118.109]) by smtp.corp.redhat.com (Postfix) with ESMTP id A6E0B5D9C3; Fri, 11 Oct 2019 08:56:51 +0000 (UTC) From: Stefan Hajnoczi To: qemu-devel@nongnu.org Subject: [PATCH v2 7/7] libqos: add VIRTIO PCI 1.0 support Date: Fri, 11 Oct 2019 09:56:11 +0100 Message-Id: <20191011085611.4194-8-stefanha@redhat.com> In-Reply-To: <20191011085611.4194-1-stefanha@redhat.com> References: <20191011085611.4194-1-stefanha@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.44]); Fri, 11 Oct 2019 08:56:56 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Paolo Bonzini , Thomas Huth , Stefan Hajnoczi , "Michael S. Tsirkin" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Implement the VIRTIO 1.0 virtio-pci interface. The main change here is that the register layout is no longer a fixed layout in BAR 0. Instead we have to iterate of PCI Capabilities to find descriptions of where various registers are located. The vring registers are also more fine-grained, allowing for more flexible vring layouts, but we don't take advantage of that. Note that test cases do not negotiate VIRTIO_F_VERSION_1 yet and are therefore not running in VIRTIO 1.0 mode. Signed-off-by: Stefan Hajnoczi Reviewed-by: Sergio Lopez --- tests/Makefile.include | 1 + tests/libqos/virtio-pci-modern.h | 17 ++ tests/libqos/virtio-pci.h | 10 + tests/libqos/virtio-pci-modern.c | 412 +++++++++++++++++++++++++++++++ tests/libqos/virtio-pci.c | 6 +- 5 files changed, 445 insertions(+), 1 deletion(-) create mode 100644 tests/libqos/virtio-pci-modern.h create mode 100644 tests/libqos/virtio-pci-modern.c diff --git a/tests/Makefile.include b/tests/Makefile.include index 3543451ed3..3f633c8313 100644 --- a/tests/Makefile.include +++ b/tests/Makefile.include @@ -715,6 +715,7 @@ qos-test-obj-y +=3D tests/libqos/virtio-blk.o qos-test-obj-y +=3D tests/libqos/virtio-mmio.o qos-test-obj-y +=3D tests/libqos/virtio-net.o qos-test-obj-y +=3D tests/libqos/virtio-pci.o +qos-test-obj-y +=3D tests/libqos/virtio-pci-modern.o qos-test-obj-y +=3D tests/libqos/virtio-rng.o qos-test-obj-y +=3D tests/libqos/virtio-scsi.o qos-test-obj-y +=3D tests/libqos/virtio-serial.o diff --git a/tests/libqos/virtio-pci-modern.h b/tests/libqos/virtio-pci-mod= ern.h new file mode 100644 index 0000000000..6bf2b207c3 --- /dev/null +++ b/tests/libqos/virtio-pci-modern.h @@ -0,0 +1,17 @@ +/* + * libqos virtio PCI VIRTIO 1.0 definitions + * + * Copyright (c) 2019 Red Hat, Inc + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef LIBQOS_VIRTIO_PCI_MODERN_H +#define LIBQOS_VIRTIO_PCI_MODERN_H + +#include "virtio-pci.h" + +bool qvirtio_pci_init_virtio_1(QVirtioPCIDevice *dev); + +#endif /* LIBQOS_VIRTIO_PCI_MODERN_H */ diff --git a/tests/libqos/virtio-pci.h b/tests/libqos/virtio-pci.h index f2d53aa377..29d4e9bf79 100644 --- a/tests/libqos/virtio-pci.h +++ b/tests/libqos/virtio-pci.h @@ -27,6 +27,13 @@ typedef struct QVirtioPCIDevice { uint32_t config_msix_data; =20 uint8_t bar_idx; + + /* VIRTIO 1.0 */ + uint32_t common_cfg_offset; + uint32_t notify_cfg_offset; + uint32_t notify_off_multiplier; + uint32_t isr_cfg_offset; + uint32_t device_cfg_offset; } QVirtioPCIDevice; =20 struct QVirtioPCIMSIXOps { @@ -43,6 +50,9 @@ typedef struct QVirtQueuePCI { uint16_t msix_entry; uint64_t msix_addr; uint32_t msix_data; + + /* VIRTIO 1.0 */ + uint64_t notify_offset; } QVirtQueuePCI; =20 void virtio_pci_init(QVirtioPCIDevice *dev, QPCIBus *bus, QPCIAddress * ad= dr); diff --git a/tests/libqos/virtio-pci-modern.c b/tests/libqos/virtio-pci-mod= ern.c new file mode 100644 index 0000000000..f23c876290 --- /dev/null +++ b/tests/libqos/virtio-pci-modern.c @@ -0,0 +1,412 @@ +/* + * libqos VIRTIO 1.0 PCI driver + * + * Copyright (c) 2019 Red Hat, Inc + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "standard-headers/linux/pci_regs.h" +#include "standard-headers/linux/virtio_pci.h" +#include "virtio-pci-modern.h" + +static uint8_t config_readb(QVirtioDevice *d, uint64_t addr) +{ + QVirtioPCIDevice *dev =3D container_of(d, QVirtioPCIDevice, vdev); + return qpci_io_readb(dev->pdev, dev->bar, dev->device_cfg_offset + add= r); +} + +static uint16_t config_readw(QVirtioDevice *d, uint64_t addr) +{ + QVirtioPCIDevice *dev =3D container_of(d, QVirtioPCIDevice, vdev); + return qpci_io_readw(dev->pdev, dev->bar, dev->device_cfg_offset + add= r); +} + +static uint32_t config_readl(QVirtioDevice *d, uint64_t addr) +{ + QVirtioPCIDevice *dev =3D container_of(d, QVirtioPCIDevice, vdev); + return qpci_io_readl(dev->pdev, dev->bar, dev->device_cfg_offset + add= r); +} + +static uint64_t config_readq(QVirtioDevice *d, uint64_t addr) +{ + QVirtioPCIDevice *dev =3D container_of(d, QVirtioPCIDevice, vdev); + return qpci_io_readq(dev->pdev, dev->bar, dev->device_cfg_offset + add= r); +} + +static uint32_t get_features(QVirtioDevice *d) +{ + QVirtioPCIDevice *dev =3D container_of(d, QVirtioPCIDevice, vdev); + + qpci_io_writel(dev->pdev, dev->bar, dev->common_cfg_offset + + offsetof(struct virtio_pci_common_cfg, + device_feature_select), + 0); + return qpci_io_readl(dev->pdev, dev->bar, dev->common_cfg_offset + + offsetof(struct virtio_pci_common_cfg, + device_feature)); +} + +static void set_features(QVirtioDevice *d, uint32_t features) +{ + QVirtioPCIDevice *dev =3D container_of(d, QVirtioPCIDevice, vdev); + + qpci_io_writel(dev->pdev, dev->bar, dev->common_cfg_offset + + offsetof(struct virtio_pci_common_cfg, + guest_feature_select), + 0); + qpci_io_writel(dev->pdev, dev->bar, dev->common_cfg_offset + + offsetof(struct virtio_pci_common_cfg, + guest_feature), + features); +} + +static uint32_t get_guest_features(QVirtioDevice *d) +{ + QVirtioPCIDevice *dev =3D container_of(d, QVirtioPCIDevice, vdev); + + qpci_io_writel(dev->pdev, dev->bar, dev->common_cfg_offset + + offsetof(struct virtio_pci_common_cfg, + guest_feature_select), + 0); + return qpci_io_readl(dev->pdev, dev->bar, dev->common_cfg_offset + + offsetof(struct virtio_pci_common_cfg, + guest_feature)); +} + +static uint8_t get_status(QVirtioDevice *d) +{ + QVirtioPCIDevice *dev =3D container_of(d, QVirtioPCIDevice, vdev); + + return qpci_io_readb(dev->pdev, dev->bar, dev->common_cfg_offset + + offsetof(struct virtio_pci_common_cfg, + device_status)); +} + +static void set_status(QVirtioDevice *d, uint8_t status) +{ + QVirtioPCIDevice *dev =3D container_of(d, QVirtioPCIDevice, vdev); + + return qpci_io_writeb(dev->pdev, dev->bar, dev->common_cfg_offset + + offsetof(struct virtio_pci_common_cfg, + device_status), + status); +} + +static bool get_msix_status(QVirtioPCIDevice *dev, uint32_t msix_entry, + uint32_t msix_addr, uint32_t msix_data) +{ + uint32_t data; + + g_assert_cmpint(msix_entry, !=3D, -1); + if (qpci_msix_masked(dev->pdev, msix_entry)) { + /* No ISR checking should be done if masked, but read anyway */ + return qpci_msix_pending(dev->pdev, msix_entry); + } + + data =3D qtest_readl(dev->pdev->bus->qts, msix_addr); + if (data =3D=3D msix_data) { + qtest_writel(dev->pdev->bus->qts, msix_addr, 0); + return true; + } else { + return false; + } +} + +static bool get_queue_isr_status(QVirtioDevice *d, QVirtQueue *vq) +{ + QVirtioPCIDevice *dev =3D container_of(d, QVirtioPCIDevice, vdev); + + if (dev->pdev->msix_enabled) { + QVirtQueuePCI *vqpci =3D container_of(vq, QVirtQueuePCI, vq); + + return get_msix_status(dev, vqpci->msix_entry, vqpci->msix_addr, + vqpci->msix_data); + } + + return qpci_io_readb(dev->pdev, dev->bar, dev->isr_cfg_offset) & 1; +} + +static bool get_config_isr_status(QVirtioDevice *d) +{ + QVirtioPCIDevice *dev =3D container_of(d, QVirtioPCIDevice, vdev); + + if (dev->pdev->msix_enabled) { + return get_msix_status(dev, dev->config_msix_entry, + dev->config_msix_addr, dev->config_msix_dat= a); + } + + return qpci_io_readb(dev->pdev, dev->bar, dev->isr_cfg_offset) & 2; +} + +static void wait_config_isr_status(QVirtioDevice *d, gint64 timeout_us) +{ + QVirtioPCIDevice *dev =3D container_of(d, QVirtioPCIDevice, vdev); + gint64 start_time =3D g_get_monotonic_time(); + + do { + g_assert(g_get_monotonic_time() - start_time <=3D timeout_us); + qtest_clock_step(dev->pdev->bus->qts, 100); + } while (!get_config_isr_status(d)); +} + +static void queue_select(QVirtioDevice *d, uint16_t index) +{ + QVirtioPCIDevice *dev =3D container_of(d, QVirtioPCIDevice, vdev); + + qpci_io_writew(dev->pdev, dev->bar, dev->common_cfg_offset + + offsetof(struct virtio_pci_common_cfg, queue_select), + index); +} + +static uint16_t get_queue_size(QVirtioDevice *d) +{ + QVirtioPCIDevice *dev =3D container_of(d, QVirtioPCIDevice, vdev); + + return qpci_io_readw(dev->pdev, dev->bar, dev->common_cfg_offset + + offsetof(struct virtio_pci_common_cfg, queue_size= )); +} + +static void set_queue_address(QVirtioDevice *d, QVirtQueue *vq) +{ + QVirtioPCIDevice *dev =3D container_of(d, QVirtioPCIDevice, vdev); + + qpci_io_writel(dev->pdev, dev->bar, dev->common_cfg_offset + + offsetof(struct virtio_pci_common_cfg, queue_desc_lo), + vq->desc); + qpci_io_writel(dev->pdev, dev->bar, dev->common_cfg_offset + + offsetof(struct virtio_pci_common_cfg, queue_desc_hi), + vq->desc >> 32); + + qpci_io_writel(dev->pdev, dev->bar, dev->common_cfg_offset + + offsetof(struct virtio_pci_common_cfg, queue_avail_lo), + vq->avail); + qpci_io_writel(dev->pdev, dev->bar, dev->common_cfg_offset + + offsetof(struct virtio_pci_common_cfg, queue_avail_hi), + vq->avail >> 32); + + qpci_io_writel(dev->pdev, dev->bar, dev->common_cfg_offset + + offsetof(struct virtio_pci_common_cfg, queue_used_lo), + vq->used); + qpci_io_writel(dev->pdev, dev->bar, dev->common_cfg_offset + + offsetof(struct virtio_pci_common_cfg, queue_used_hi), + vq->used >> 32); +} + +static QVirtQueue *virtqueue_setup(QVirtioDevice *d, QGuestAllocator *allo= c, + uint16_t index) +{ + QVirtioPCIDevice *dev =3D container_of(d, QVirtioPCIDevice, vdev); + QVirtQueue *vq; + QVirtQueuePCI *vqpci; + uint16_t notify_off; + + vq =3D qvirtio_pci_virtqueue_setup_common(d, alloc, index); + vqpci =3D container_of(vq, QVirtQueuePCI, vq); + + notify_off =3D qpci_io_readw(dev->pdev, dev->bar, dev->common_cfg_offs= et + + offsetof(struct virtio_pci_common_cfg, + queue_notify_off)); + + vqpci->notify_offset =3D dev->notify_cfg_offset + + notify_off * dev->notify_off_multiplier; + + qpci_io_writew(dev->pdev, dev->bar, dev->common_cfg_offset + + offsetof(struct virtio_pci_common_cfg, queue_enable), 1= ); + + return vq; +} + +static void virtqueue_kick(QVirtioDevice *d, QVirtQueue *vq) +{ + QVirtioPCIDevice *dev =3D container_of(d, QVirtioPCIDevice, vdev); + QVirtQueuePCI *vqpci =3D container_of(vq, QVirtQueuePCI, vq); + + qpci_io_writew(dev->pdev, dev->bar, vqpci->notify_offset, vq->index); +} + +static const QVirtioBus qvirtio_pci_virtio_1 =3D { + .config_readb =3D config_readb, + .config_readw =3D config_readw, + .config_readl =3D config_readl, + .config_readq =3D config_readq, + .get_features =3D get_features, + .set_features =3D set_features, + .get_guest_features =3D get_guest_features, + .get_status =3D get_status, + .set_status =3D set_status, + .get_queue_isr_status =3D get_queue_isr_status, + .wait_config_isr_status =3D wait_config_isr_status, + .queue_select =3D queue_select, + .get_queue_size =3D get_queue_size, + .set_queue_address =3D set_queue_address, + .virtqueue_setup =3D virtqueue_setup, + .virtqueue_cleanup =3D qvirtio_pci_virtqueue_cleanup_common, + .virtqueue_kick =3D virtqueue_kick, +}; + +static void set_config_vector(QVirtioPCIDevice *d, uint16_t entry) +{ + uint16_t vector; + + qpci_io_writew(d->pdev, d->bar, d->common_cfg_offset + + offsetof(struct virtio_pci_common_cfg, msix_config), en= try); + vector =3D qpci_io_readw(d->pdev, d->bar, d->common_cfg_offset + + offsetof(struct virtio_pci_common_cfg, + msix_config)); + g_assert_cmphex(vector, !=3D, VIRTIO_MSI_NO_VECTOR); +} + +static void set_queue_vector(QVirtioPCIDevice *d, uint16_t vq_idx, + uint16_t entry) +{ + uint16_t vector; + + queue_select(&d->vdev, vq_idx); + qpci_io_writew(d->pdev, d->bar, d->common_cfg_offset + + offsetof(struct virtio_pci_common_cfg, queue_msix_vecto= r), + entry); + vector =3D qpci_io_readw(d->pdev, d->bar, d->common_cfg_offset + + offsetof(struct virtio_pci_common_cfg, + queue_msix_vector)); + g_assert_cmphex(vector, !=3D, VIRTIO_MSI_NO_VECTOR); +} + +static const QVirtioPCIMSIXOps qvirtio_pci_msix_ops_virtio_1 =3D { + .set_config_vector =3D set_config_vector, + .set_queue_vector =3D set_queue_vector, +}; + +static bool probe_device_type(QVirtioPCIDevice *dev) +{ + uint16_t vendor_id; + uint16_t device_id; + + /* "Drivers MUST match devices with the PCI Vendor ID 0x1AF4" */ + vendor_id =3D qpci_config_readw(dev->pdev, PCI_VENDOR_ID); + if (vendor_id !=3D 0x1af4) { + return false; + } + + /* + * "Any PCI device with ... PCI Device ID 0x1000 through 0x107F inclus= ive + * is a virtio device" + */ + device_id =3D qpci_config_readw(dev->pdev, PCI_DEVICE_ID); + if (device_id < 0x1000 || device_id > 0x107f) { + return false; + } + + /* + * "Devices MAY utilize a Transitional PCI Device ID range, 0x1000 to + * 0x103F depending on the device type" + */ + if (device_id < 0x1040) { + /* + * "Transitional devices MUST have the PCI Subsystem Device ID mat= ching + * the Virtio Device ID" + */ + dev->vdev.device_type =3D qpci_config_readw(dev->pdev, PCI_SUBSYST= EM_ID); + } else { + /* + * "The PCI Device ID is calculated by adding 0x1040 to the Virtio + * Device ID" + */ + dev->vdev.device_type =3D device_id - 0x1040; + } + + return true; +} + +/* Find the first VIRTIO 1.0 PCI structure for a given type */ +static bool find_structure(QVirtioPCIDevice *dev, uint8_t cfg_type, + uint8_t *bar, uint32_t *offset, uint32_t *lengt= h, + uint8_t *cfg_addr) +{ + uint8_t addr =3D 0; + + while ((addr =3D qpci_find_capability(dev->pdev, PCI_CAP_ID_VNDR, + addr)) !=3D 0) { + uint8_t type; + + type =3D qpci_config_readb(dev->pdev, + addr + offsetof(struct virtio_pci_cap, cfg_type)); + if (type !=3D cfg_type) { + continue; + } + + *bar =3D qpci_config_readb(dev->pdev, + addr + offsetof(struct virtio_pci_cap, bar)); + *offset =3D qpci_config_readl(dev->pdev, + addr + offsetof(struct virtio_pci_cap, offset)); + *length =3D qpci_config_readl(dev->pdev, + addr + offsetof(struct virtio_pci_cap, length)); + if (cfg_addr) { + *cfg_addr =3D addr; + } + + return true; + } + + return false; +} + +static bool probe_device_layout(QVirtioPCIDevice *dev) +{ + uint8_t bar; + uint8_t cfg_addr; + uint32_t length; + + /* + * Due to the qpci_iomap() API we only support devices that put all + * structures in the same PCI BAR. Luckily this is true with QEMU. + */ + + if (!find_structure(dev, VIRTIO_PCI_CAP_COMMON_CFG, &dev->bar_idx, + &dev->common_cfg_offset, &length, NULL)) { + return false; + } + + if (!find_structure(dev, VIRTIO_PCI_CAP_NOTIFY_CFG, &bar, + &dev->notify_cfg_offset, &length, &cfg_addr)) { + return false; + } + g_assert_cmphex(bar, =3D=3D, dev->bar_idx); + + dev->notify_off_multiplier =3D qpci_config_readl(dev->pdev, + cfg_addr + offsetof(struct virtio_pci_notify_cap, + notify_off_multiplier)); + + if (!find_structure(dev, VIRTIO_PCI_CAP_ISR_CFG, &bar, + &dev->isr_cfg_offset, &length, NULL)) { + return false; + } + g_assert_cmphex(bar, =3D=3D, dev->bar_idx); + + if (!find_structure(dev, VIRTIO_PCI_CAP_DEVICE_CFG, &bar, + &dev->device_cfg_offset, &length, NULL)) { + return false; + } + g_assert_cmphex(bar, =3D=3D, dev->bar_idx); + + return true; +} + +/* Probe a VIRTIO 1.0 device */ +bool qvirtio_pci_init_virtio_1(QVirtioPCIDevice *dev) +{ + if (!probe_device_type(dev)) { + return false; + } + + if (!probe_device_layout(dev)) { + return false; + } + + dev->vdev.bus =3D &qvirtio_pci_virtio_1; + dev->msix_ops =3D &qvirtio_pci_msix_ops_virtio_1; + dev->vdev.big_endian =3D false; + return true; +} diff --git a/tests/libqos/virtio-pci.c b/tests/libqos/virtio-pci.c index efd8caee18..5bdf403351 100644 --- a/tests/libqos/virtio-pci.c +++ b/tests/libqos/virtio-pci.c @@ -22,6 +22,8 @@ #include "hw/pci/pci.h" #include "hw/pci/pci_regs.h" =20 +#include "virtio-pci-modern.h" + /* virtio-pci is a superclass of all virtio-xxx-pci devices; * the relation between virtio-pci and virtio-xxx-pci is implicit, * and therefore virtio-pci does not produce virtio and is not @@ -400,7 +402,9 @@ static void qvirtio_pci_init_from_pcidev(QVirtioPCIDevi= ce *dev, QPCIDevice *pci_ dev->pdev =3D pci_dev; dev->config_msix_entry =3D -1; =20 - qvirtio_pci_init_legacy(dev); + if (!qvirtio_pci_init_virtio_1(dev)) { + qvirtio_pci_init_legacy(dev); + } =20 /* each virtio-xxx-pci device should override at least this function */ dev->obj.get_driver =3D NULL; --=20 2.21.0