From nobody Mon Feb 9 12:26:55 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1570713805; cv=none; d=zoho.com; s=zohoarc; b=B2Q/pPxzZ0i3VA0pOsY8lb2eywh6A30dhhB38u7PTXbda6LWOv3Rr98E5bPplnYDUkzdNqlsFvPlT+FS2fwMNtDgWzR15MBjvukZE7O6rYALMwoYCjAsbhQaWqgMMSH3fAGwGIFcsiZmGB60Zh158mU/814XgHfp9P/OJbb+a4Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1570713805; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=D5FXIWhaVIx4CNQx8TAUCptfFwEckphvDdLlQQbJW64=; b=oTw35syA9yQ3x0C87bE6zzANjxahx/PYqEQNT2UDxqLsHzccHQLUWicGUZMbTLuOHD8GMx2jhJMBRPZT2S1TgA/AdY/fWWZSNs0s1RMuoxpZCs0MbTHP6S6Jirs0eqtPK39cdUjNHrHg6Bi0yyeFTWCYh+Hq49Li9c1i/e165nA= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1570713805503679.3906810967546; Thu, 10 Oct 2019 06:23:25 -0700 (PDT) Received: from localhost ([::1]:39418 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iIYPb-0007Vh-VL for importer@patchew.org; Thu, 10 Oct 2019 09:23:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40572) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iIYJG-0000iM-Hn for qemu-devel@nongnu.org; Thu, 10 Oct 2019 09:16:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iIYJF-0002HZ-FD for qemu-devel@nongnu.org; Thu, 10 Oct 2019 09:16:50 -0400 Received: from mx1.redhat.com ([209.132.183.28]:54536) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iIYJ9-0002Dh-Il; Thu, 10 Oct 2019 09:16:43 -0400 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id BE3773084249; Thu, 10 Oct 2019 13:16:42 +0000 (UTC) Received: from x1w.redhat.com (unknown [10.40.205.241]) by smtp.corp.redhat.com (Postfix) with ESMTPS id B76B7600C4; Thu, 10 Oct 2019 13:16:34 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Eduardo Habkost , qemu-devel@nongnu.org Subject: [PATCH v3 4/8] hw/ide/sii3112: Convert reset handler to DeviceReset Date: Thu, 10 Oct 2019 15:15:23 +0200 Message-Id: <20191010131527.32513-5-philmd@redhat.com> In-Reply-To: <20191010131527.32513-1-philmd@redhat.com> References: <20191010131527.32513-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.40]); Thu, 10 Oct 2019 13:16:42 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Aleksandar Markovic , qemu-block@nongnu.org, "Michael S. Tsirkin" , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Li Qiang , qemu-arm@nongnu.org, qemu-ppc@nongnu.org, Igor Mammedov , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , John Snow Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The SiI3112A SATA controller is a PCI device, it will be reset when the PCI bus it stands on is reset. Convert its reset handler into a proper Device reset method. Reviewed-by: Li Qiang Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/ide/sii3112.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/hw/ide/sii3112.c b/hw/ide/sii3112.c index 2181260531..06605d7af2 100644 --- a/hw/ide/sii3112.c +++ b/hw/ide/sii3112.c @@ -15,7 +15,6 @@ #include "qemu/osdep.h" #include "hw/ide/pci.h" #include "qemu/module.h" -#include "sysemu/reset.h" #include "trace.h" =20 #define TYPE_SII3112_PCI "sii3112" @@ -237,9 +236,9 @@ static void sii3112_set_irq(void *opaque, int channel, = int level) sii3112_update_irq(s); } =20 -static void sii3112_reset(void *opaque) +static void sii3112_reset(DeviceState *dev) { - SiI3112PCIState *s =3D opaque; + SiI3112PCIState *s =3D SII3112_PCI(dev); int i; =20 for (i =3D 0; i < 2; i++) { @@ -290,7 +289,6 @@ static void sii3112_pci_realize(PCIDevice *dev, Error *= *errp) s->bmdma[i].bus =3D &s->bus[i]; ide_register_restart_cb(&s->bus[i]); } - qemu_register_reset(sii3112_reset, s); } =20 static void sii3112_pci_class_init(ObjectClass *klass, void *data) @@ -303,6 +301,7 @@ static void sii3112_pci_class_init(ObjectClass *klass, = void *data) pd->class_id =3D PCI_CLASS_STORAGE_RAID; pd->revision =3D 1; pd->realize =3D sii3112_pci_realize; + dc->reset =3D sii3112_reset; dc->desc =3D "SiI3112A SATA controller"; set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); } --=20 2.21.0