From nobody Sat Apr 27 01:55:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1570639723; cv=none; d=zoho.com; s=zohoarc; b=cvibtblVTaF5UV3/tEYVj7++a4AEfrSacKcLTD8tNUvmTIlq0SA6wkzgRzCm7Q8k9IEgai0xUuiAfNHbQs/yKWGhhQPtJXBQdtUWscCFVWdNiH9jps9duEN7ArWCc2mqnaD8E++Hxx3mYlp+BKMlQvGztNp/w73KOBjMzJN8sFw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1570639723; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=li73R6VG6AugPT+nb1lhSq0qQjn8TGYgwP1SkVF9PMs=; b=nccjHNjxET8z4DlZ9uzqmRmxxXqpVHwMex9qGc0qoilZrbN/DntEeoDelaYZbMQ1yy/c+y/a3O0JjvPjBGgftDE57BhusVEpLV5au3K2BC+R5q+oxu+zbGG39YQ3CXsLbT/G1hEKi7yrRd1SYzrNotVgY4P4qnEJT+RqQ+W1yMI= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1570639723160319.489315421008; Wed, 9 Oct 2019 09:48:43 -0700 (PDT) Received: from localhost ([::1]:52504 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iIF8j-0002ng-8Z for importer@patchew.org; Wed, 09 Oct 2019 12:48:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60011) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iI59C-0001XO-04 for qemu-devel@nongnu.org; Wed, 09 Oct 2019 02:08:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iI59A-0006UN-Cs for qemu-devel@nongnu.org; Wed, 09 Oct 2019 02:08:29 -0400 Received: from bilbo.ozlabs.org ([203.11.71.1]:51559 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iI599-0006PG-DG; Wed, 09 Oct 2019 02:08:28 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 46p3gD0r2pz9sDB; Wed, 9 Oct 2019 17:08:24 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1570601304; bh=5KV84r29nIJXr/A9Jl+oWqntFxHPYStDWAbStjFb6C0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bkJ07THdIuVgBT3JyE3rvy4J2z1bS07D2dYYlF0NuI76gF2qBT2Ie8VRgRgCqxNKc SlNPgz8YrpCJHkSmMGaJMQE0LNpHgpb+cT5vp0JegZ4DM7j3W2YOsjKecfhNeVOy8g iC6YmQCxd5+TuIjEDa2ka0DR3HbuePfnXdMJAI3s= From: David Gibson To: qemu-devel@nongnu.org, clg@kaod.org, qemu-ppc@nongnu.org Subject: [PATCH v4 01/19] xive: Make some device types not user creatable Date: Wed, 9 Oct 2019 17:08:00 +1100 Message-Id: <20191009060818.29719-2-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191009060818.29719-1-david@gibson.dropbear.id.au> References: <20191009060818.29719-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jason Wang , Riku Voipio , groug@kaod.org, Laurent Vivier , Paolo Bonzini , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , philmd@redhat.com, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Greg Kurz Some device types of the XIVE model are exposed to the QEMU command line: $ ppc64-softmmu/qemu-system-ppc64 -device help | grep xive name "xive-end-source", desc "XIVE END Source" name "xive-source", desc "XIVE Interrupt Source" name "xive-tctx", desc "XIVE Interrupt Thread Context" These are internal devices that shouldn't be instantiable by the user. By the way, they can't be because their respective realize functions expect link properties that can't be set from the command line: qemu-system-ppc64: -device xive-source: required link 'xive' not found: Property '.xive' not found qemu-system-ppc64: -device xive-end-source: required link 'xive' not found: Property '.xive' not found qemu-system-ppc64: -device xive-tctx: required link 'cpu' not found: Property '.cpu' not found Hide them by setting dc->user_creatable to false in their respective class init functions. Signed-off-by: Greg Kurz Message-Id: <157017473006.331610.2983143972519884544.stgit@bahia.lan> Message-Id: <157045578401.865784.6058183726552779559.stgit@bahia.lan> Reviewed-by: C=C3=A9dric Le Goater [dwg: Folded comment update into base patch] Signed-off-by: David Gibson --- hw/intc/xive.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 29df06df11..453d389848 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -670,6 +670,11 @@ static void xive_tctx_class_init(ObjectClass *klass, v= oid *data) dc->realize =3D xive_tctx_realize; dc->unrealize =3D xive_tctx_unrealize; dc->vmsd =3D &vmstate_xive_tctx; + /* + * Reason: part of XIVE interrupt controller, needs to be wired up + * by xive_tctx_create(). + */ + dc->user_creatable =3D false; } =20 static const TypeInfo xive_tctx_info =3D { @@ -1118,6 +1123,11 @@ static void xive_source_class_init(ObjectClass *klas= s, void *data) dc->props =3D xive_source_properties; dc->realize =3D xive_source_realize; dc->vmsd =3D &vmstate_xive_source; + /* + * Reason: part of XIVE interrupt controller, needs to be wired up, + * e.g. by spapr_xive_instance_init(). + */ + dc->user_creatable =3D false; } =20 static const TypeInfo xive_source_info =3D { @@ -1853,6 +1863,11 @@ static void xive_end_source_class_init(ObjectClass *= klass, void *data) dc->desc =3D "XIVE END Source"; dc->props =3D xive_end_source_properties; dc->realize =3D xive_end_source_realize; + /* + * Reason: part of XIVE interrupt controller, needs to be wired up, + * e.g. by spapr_xive_instance_init(). + */ + dc->user_creatable =3D false; } =20 static const TypeInfo xive_end_source_info =3D { --=20 2.21.0 From nobody Sat Apr 27 01:55:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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Wed, 9 Oct 2019 09:27:21 -0700 (PDT) Received: from localhost ([::1]:52249 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iIEo3-0006oE-M9 for importer@patchew.org; Wed, 09 Oct 2019 12:27:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60010) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iI59B-0001XN-OZ for qemu-devel@nongnu.org; Wed, 09 Oct 2019 02:08:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iI59A-0006UI-Cm for qemu-devel@nongnu.org; Wed, 09 Oct 2019 02:08:29 -0400 Received: from bilbo.ozlabs.org ([203.11.71.1]:51091 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iI599-0006PS-Jd; Wed, 09 Oct 2019 02:08:28 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 46p3gD1g9yz9sPK; Wed, 9 Oct 2019 17:08:24 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1570601304; bh=ocrX3ncUYBFcZTW4CQsb4v8fYUjtodAeqwtBgAzm4yU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Cw9eeIbrPSyfF2nzCRKQw1YtJUUi+eEic6M8GG9fYWv7oA5CsUGdUnfkhoCeSCTUr HQ/aGJYhnN//iXVmT+4Arpl7bK+jewf+dP0Ye+J4cu24ihRga39aVoWEHPI3vQJ9rm cSqFWZwiQxmEBZ7jipIl4uHDZ2lyP/aIzUuuXyNE= From: David Gibson To: qemu-devel@nongnu.org, clg@kaod.org, qemu-ppc@nongnu.org Subject: [PATCH v4 02/19] xics: Make some device types not user creatable Date: Wed, 9 Oct 2019 17:08:01 +1100 Message-Id: <20191009060818.29719-3-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191009060818.29719-1-david@gibson.dropbear.id.au> References: <20191009060818.29719-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jason Wang , Riku Voipio , groug@kaod.org, Laurent Vivier , Paolo Bonzini , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , philmd@redhat.com, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Greg Kurz Some device types of the XICS model are exposed to the QEMU command line: $ ppc64-softmmu/qemu-system-ppc64 -device help | grep ic[sp] name "icp" name "ics" name "ics-spapr" name "pnv-icp", desc "PowerNV ICP" These are internal devices that shouldn't be instantiable by the user. By the way, they can't be because their respective realize functions expect link properties that can't be set from the command line: qemu-system-ppc64: -device icp: required link 'xics' not found: Property '.xics' not found qemu-system-ppc64: -device ics: required link 'xics' not found: Property '.xics' not found qemu-system-ppc64: -device ics-spapr: required link 'xics' not found: Property '.xics' not found qemu-system-ppc64: -device pnv-icp: required link 'xics' not found: Property '.xics' not found Hide them by setting dc->user_creatable to false in the base class "icp" and "ics" init functions. Signed-off-by: Greg Kurz Message-Id: <157017826724.337875.14822177178282524024.stgit@bahia.lan> Message-Id: <157045578962.865784.8551555523533955113.stgit@bahia.lan> [dwg: Folded reason comment into base patch] Signed-off-by: David Gibson --- hw/intc/xics.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/hw/intc/xics.c b/hw/intc/xics.c index dfe7dbd254..b5ac408f7b 100644 --- a/hw/intc/xics.c +++ b/hw/intc/xics.c @@ -369,6 +369,11 @@ static void icp_class_init(ObjectClass *klass, void *d= ata) =20 dc->realize =3D icp_realize; dc->unrealize =3D icp_unrealize; + /* + * Reason: part of XICS interrupt controller, needs to be wired up + * by icp_create(). + */ + dc->user_creatable =3D false; } =20 static const TypeInfo icp_info =3D { @@ -689,6 +694,11 @@ static void ics_class_init(ObjectClass *klass, void *d= ata) dc->props =3D ics_properties; dc->reset =3D ics_reset; dc->vmsd =3D &vmstate_ics; + /* + * Reason: part of XICS interrupt controller, needs to be wired up, + * e.g. by spapr_irq_init(). + */ + dc->user_creatable =3D false; } =20 static const TypeInfo ics_info =3D { --=20 2.21.0 From nobody Sat Apr 27 01:55:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1570638704; cv=none; d=zoho.com; s=zohoarc; b=PcYePnbvHE1EFL1ygYF5TBgHRe5iBjr48sIvlOdDI/BdQhWKyRyVgfWJ1m+lGmZLUeojok2SwtHiUJdRdfcznyBARHcywMUjWNpKRb0qQe8huXB7pzrPJiHSKdPbfcOUqMVUIv1wNHNH9jo8XPsv3FvtDSEypCZmUZFCSnSoShA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1570638704; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Le8DNce4DLGTCoM30RfztMcPl8nU4R32S+52hmxmNEs=; b=Z/cuIxvlWOv2YGXfvXy11BTDXsJ9+IO0qsZgAGyE7/oVORCbDdUF6xIdjBcxlggU1FQ4G2VtYPGzw+sD0ElT2Y18lgu43d4qE0f/Wd4Rua2joz1N8M/ahQ0MDUjrrmLr1n6jLJ+u6aDeHhTzbze+AWcphLcvsV6rjJ0bO+HUqHk= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 157063870470034.64672330027986; Wed, 9 Oct 2019 09:31:44 -0700 (PDT) Received: from localhost ([::1]:52306 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iIEsD-0002Lb-BM for importer@patchew.org; Wed, 09 Oct 2019 12:31:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60050) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iI59E-0001XW-73 for qemu-devel@nongnu.org; Wed, 09 Oct 2019 02:08:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iI59B-0006VJ-2s for qemu-devel@nongnu.org; Wed, 09 Oct 2019 02:08:31 -0400 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:53977 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iI59A-0006PI-Mw; Wed, 09 Oct 2019 02:08:29 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 46p3gD2gkkz9sPf; Wed, 9 Oct 2019 17:08:24 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1570601304; bh=bDJ+lL6U7/EjRyMJMnAmLePHj2/5rsdcdvyY0UDu9xU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Fw0PgFZTguwK62yr30BqolDZx60aWG9qPkcfW8zi8krI8c0gMkNagxYwT6moZ4hrl luqsxymGe7P7OIlajDZk+XQJE8cIBXWBd/ec5Aw7eZWZre61RbiWSbbkXA+mW/Ba3m NTHb9uPRXRli1uZxHRIzsWKf71xEuj8zK/3pvO1Y= From: David Gibson To: qemu-devel@nongnu.org, clg@kaod.org, qemu-ppc@nongnu.org Subject: [PATCH v4 03/19] target/ppc: Fix for optimized vsl/vsr instructions Date: Wed, 9 Oct 2019 17:08:02 +1100 Message-Id: <20191009060818.29719-4-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191009060818.29719-1-david@gibson.dropbear.id.au> References: <20191009060818.29719-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stefan Brankovic , Jason Wang , Riku Voipio , Mark Cave-Ayland , groug@kaod.org, Laurent Vivier , Aleksandar Markovic , "Paul A. Clark" , Paolo Bonzini , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , philmd@redhat.com, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Stefan Brankovic In previous implementation, invocation of TCG shift function could request shift of TCG variable by 64 bits when variable 'sh' is 0, which is not supported in TCG (values can be shifted by 0 to 63 bits). This patch fixes this by using two separate invocation of TCG shift functions, with maximum shift amount of 32. Name of variable 'shifted' is changed to 'carry' so variable naming is similar to old helper implementation. Variables 'avrA' and 'avrB' are replaced with variable 'avr'. Fixes: 4e6d0920e7547e6af4bbac5ffe9adfe6ea621822 Reported-by: "Paul A. Clark" Reported-by: Mark Cave-Ayland Suggested-by: Aleksandar Markovic Signed-off-by: Stefan Brankovic Message-Id: <1570196639-7025-2-git-send-email-stefan.brankovic@rt-rk.com> Tested-by: Paul A. Clarke Signed-off-by: David Gibson --- target/ppc/translate/vmx-impl.inc.c | 84 ++++++++++++++--------------- 1 file changed, 40 insertions(+), 44 deletions(-) diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx= -impl.inc.c index 2472a5217a..81d5a7a341 100644 --- a/target/ppc/translate/vmx-impl.inc.c +++ b/target/ppc/translate/vmx-impl.inc.c @@ -590,40 +590,38 @@ static void trans_vsl(DisasContext *ctx) int VT =3D rD(ctx->opcode); int VA =3D rA(ctx->opcode); int VB =3D rB(ctx->opcode); - TCGv_i64 avrA =3D tcg_temp_new_i64(); - TCGv_i64 avrB =3D tcg_temp_new_i64(); + TCGv_i64 avr =3D tcg_temp_new_i64(); TCGv_i64 sh =3D tcg_temp_new_i64(); - TCGv_i64 shifted =3D tcg_temp_new_i64(); + TCGv_i64 carry =3D tcg_temp_new_i64(); TCGv_i64 tmp =3D tcg_temp_new_i64(); =20 - /* Place bits 125-127 of vB in sh. */ - get_avr64(avrB, VB, false); - tcg_gen_andi_i64(sh, avrB, 0x07ULL); + /* Place bits 125-127 of vB in 'sh'. */ + get_avr64(avr, VB, false); + tcg_gen_andi_i64(sh, avr, 0x07ULL); =20 /* - * Save highest sh bits of lower doubleword element of vA in variable - * shifted and perform shift on lower doubleword. + * Save highest 'sh' bits of lower doubleword element of vA in variable + * 'carry' and perform shift on lower doubleword. */ - get_avr64(avrA, VA, false); - tcg_gen_subfi_i64(tmp, 64, sh); - tcg_gen_shr_i64(shifted, avrA, tmp); - tcg_gen_andi_i64(shifted, shifted, 0x7fULL); - tcg_gen_shl_i64(avrA, avrA, sh); - set_avr64(VT, avrA, false); + get_avr64(avr, VA, false); + tcg_gen_subfi_i64(tmp, 32, sh); + tcg_gen_shri_i64(carry, avr, 32); + tcg_gen_shr_i64(carry, carry, tmp); + tcg_gen_shl_i64(avr, avr, sh); + set_avr64(VT, avr, false); =20 /* * Perform shift on higher doubleword element of vA and replace lowest - * sh bits with shifted. + * 'sh' bits with 'carry'. */ - get_avr64(avrA, VA, true); - tcg_gen_shl_i64(avrA, avrA, sh); - tcg_gen_or_i64(avrA, avrA, shifted); - set_avr64(VT, avrA, true); + get_avr64(avr, VA, true); + tcg_gen_shl_i64(avr, avr, sh); + tcg_gen_or_i64(avr, avr, carry); + set_avr64(VT, avr, true); =20 - tcg_temp_free_i64(avrA); - tcg_temp_free_i64(avrB); + tcg_temp_free_i64(avr); tcg_temp_free_i64(sh); - tcg_temp_free_i64(shifted); + tcg_temp_free_i64(carry); tcg_temp_free_i64(tmp); } =20 @@ -639,39 +637,37 @@ static void trans_vsr(DisasContext *ctx) int VT =3D rD(ctx->opcode); int VA =3D rA(ctx->opcode); int VB =3D rB(ctx->opcode); - TCGv_i64 avrA =3D tcg_temp_new_i64(); - TCGv_i64 avrB =3D tcg_temp_new_i64(); + TCGv_i64 avr =3D tcg_temp_new_i64(); TCGv_i64 sh =3D tcg_temp_new_i64(); - TCGv_i64 shifted =3D tcg_temp_new_i64(); + TCGv_i64 carry =3D tcg_temp_new_i64(); TCGv_i64 tmp =3D tcg_temp_new_i64(); =20 - /* Place bits 125-127 of vB in sh. */ - get_avr64(avrB, VB, false); - tcg_gen_andi_i64(sh, avrB, 0x07ULL); + /* Place bits 125-127 of vB in 'sh'. */ + get_avr64(avr, VB, false); + tcg_gen_andi_i64(sh, avr, 0x07ULL); =20 /* - * Save lowest sh bits of higher doubleword element of vA in variable - * shifted and perform shift on higher doubleword. + * Save lowest 'sh' bits of higher doubleword element of vA in variable + * 'carry' and perform shift on higher doubleword. */ - get_avr64(avrA, VA, true); - tcg_gen_subfi_i64(tmp, 64, sh); - tcg_gen_shl_i64(shifted, avrA, tmp); - tcg_gen_andi_i64(shifted, shifted, 0xfe00000000000000ULL); - tcg_gen_shr_i64(avrA, avrA, sh); - set_avr64(VT, avrA, true); + get_avr64(avr, VA, true); + tcg_gen_subfi_i64(tmp, 32, sh); + tcg_gen_shli_i64(carry, avr, 32); + tcg_gen_shl_i64(carry, carry, tmp); + tcg_gen_shr_i64(avr, avr, sh); + set_avr64(VT, avr, true); /* * Perform shift on lower doubleword element of vA and replace highest - * sh bits with shifted. + * 'sh' bits with 'carry'. */ - get_avr64(avrA, VA, false); - tcg_gen_shr_i64(avrA, avrA, sh); - tcg_gen_or_i64(avrA, avrA, shifted); - set_avr64(VT, avrA, false); + get_avr64(avr, VA, false); + tcg_gen_shr_i64(avr, avr, sh); + tcg_gen_or_i64(avr, avr, carry); + set_avr64(VT, avr, false); =20 - tcg_temp_free_i64(avrA); - tcg_temp_free_i64(avrB); + tcg_temp_free_i64(avr); tcg_temp_free_i64(sh); - tcg_temp_free_i64(shifted); + tcg_temp_free_i64(carry); tcg_temp_free_i64(tmp); } =20 --=20 2.21.0 From nobody Sat Apr 27 01:55:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Wed, 09 Oct 2019 02:08:28 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 46p3gD3NzCz9sPd; Wed, 9 Oct 2019 17:08:24 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1570601304; bh=QE+VjKlHW32sv6S8hNVKI2dRx7I/EdLEKnK8b1S4tII=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kalbbc3ja3trmtvTcpq1kwYFb3BeU6Szg0mNPw6rBVagcSFVMg/z2RnxSEx3iykNK Ou7uANbJsCmxjvdWJfPxjYxGGoQRSSXLfhShblASmaJtjfpWX0IeRjRBuxsoASKSy6 x6y6qHBtUB/IVBg1CM7Y1zMw5hJO/Ub3rBP2aNjs= From: David Gibson To: qemu-devel@nongnu.org, clg@kaod.org, qemu-ppc@nongnu.org Subject: [PATCH v4 04/19] spapr, xics, xive: Introduce SpaprInterruptController QOM interface Date: Wed, 9 Oct 2019 17:08:03 +1100 Message-Id: <20191009060818.29719-5-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191009060818.29719-1-david@gibson.dropbear.id.au> References: <20191009060818.29719-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jason Wang , Riku Voipio , groug@kaod.org, Laurent Vivier , Paolo Bonzini , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , philmd@redhat.com, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The SpaprIrq structure is used to represent ths spapr machine's irq backend. Except that it kind of conflates two concepts: one is the backend proper - a specific interrupt controller that we might or might not be using, the other is the irq configuration which covers the layout of irq space and which interrupt controllers are allowed. This leads to some pretty confusing code paths for the "dual" configuration where its hooks redirect to other SpaprIrq structures depending on the currently active irq controller. To clean this up, we start by introducing a new SpaprInterruptController QOM interface to represent strictly an interrupt controller backend, not counting anything configuration related. We implement this interface in the XICs and XIVE interrupt controllers, and in future we'll move relevant methods from SpaprIrq into it. Signed-off-by: David Gibson Reviewed-by: Greg Kurz Reviewed-by: C=C3=A9dric Le Goater --- hw/intc/spapr_xive.c | 4 ++++ hw/intc/xics_spapr.c | 4 ++++ hw/ppc/spapr_irq.c | 13 +++++++++++++ include/hw/ppc/spapr_irq.h | 14 ++++++++++++++ 4 files changed, 35 insertions(+) diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c index 04879abf2e..b67e9c3245 100644 --- a/hw/intc/spapr_xive.c +++ b/hw/intc/spapr_xive.c @@ -519,6 +519,10 @@ static const TypeInfo spapr_xive_info =3D { .instance_init =3D spapr_xive_instance_init, .instance_size =3D sizeof(SpaprXive), .class_init =3D spapr_xive_class_init, + .interfaces =3D (InterfaceInfo[]) { + { TYPE_SPAPR_INTC }, + { } + }, }; =20 static void spapr_xive_register_types(void) diff --git a/hw/intc/xics_spapr.c b/hw/intc/xics_spapr.c index 6e5eb24b3c..4874e6be55 100644 --- a/hw/intc/xics_spapr.c +++ b/hw/intc/xics_spapr.c @@ -343,6 +343,10 @@ static const TypeInfo ics_spapr_info =3D { .name =3D TYPE_ICS_SPAPR, .parent =3D TYPE_ICS, .class_init =3D ics_spapr_class_init, + .interfaces =3D (InterfaceInfo[]) { + { TYPE_SPAPR_INTC }, + { } + }, }; =20 static void xics_spapr_register_types(void) diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c index 457eabe24c..8791dec1ba 100644 --- a/hw/ppc/spapr_irq.c +++ b/hw/ppc/spapr_irq.c @@ -23,6 +23,12 @@ =20 #include "trace.h" =20 +static const TypeInfo spapr_intc_info =3D { + .name =3D TYPE_SPAPR_INTC, + .parent =3D TYPE_INTERFACE, + .class_size =3D sizeof(SpaprInterruptControllerClass), +}; + void spapr_irq_msi_init(SpaprMachineState *spapr, uint32_t nr_msis) { spapr->irq_map_nr =3D nr_msis; @@ -762,3 +768,10 @@ SpaprIrq spapr_irq_xics_legacy =3D { .set_irq =3D spapr_irq_set_irq_xics, .init_kvm =3D spapr_irq_init_kvm_xics, }; + +static void spapr_irq_register_types(void) +{ + type_register_static(&spapr_intc_info); +} + +type_init(spapr_irq_register_types) diff --git a/include/hw/ppc/spapr_irq.h b/include/hw/ppc/spapr_irq.h index 69a37f608e..b9398e0be3 100644 --- a/include/hw/ppc/spapr_irq.h +++ b/include/hw/ppc/spapr_irq.h @@ -31,6 +31,20 @@ =20 typedef struct SpaprMachineState SpaprMachineState; =20 +typedef struct SpaprInterruptController SpaprInterruptController; + +#define TYPE_SPAPR_INTC "spapr-interrupt-controller" +#define SPAPR_INTC(obj) \ + INTERFACE_CHECK(SpaprInterruptController, (obj), TYPE_SPAPR_INTC) +#define SPAPR_INTC_CLASS(klass) \ + OBJECT_CLASS_CHECK(SpaprInterruptControllerClass, (klass), TYPE_SPAPR_= INTC) +#define SPAPR_INTC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(SpaprInterruptControllerClass, (obj), TYPE_SPAPR_INTC) + +typedef struct SpaprInterruptControllerClass { + InterfaceClass parent; +} SpaprInterruptControllerClass; + void spapr_irq_msi_init(SpaprMachineState *spapr, uint32_t nr_msis); int spapr_irq_msi_alloc(SpaprMachineState *spapr, uint32_t num, bool align, Error **errp); --=20 2.21.0 From nobody Sat Apr 27 01:55:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; 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Wed, 09 Oct 2019 02:08:31 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 46p3gD400Gz9sPl; Wed, 9 Oct 2019 17:08:24 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1570601304; bh=6dzl8JJ8+fSiRyb7o7fBhYuTKyrLVQ6TySLo4kuU1Y0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Y08qlZKr9q9Bnu0IMUcRVBdnVKG9dvMLu+EbxNegauSW6X9RLIOWfhruyfSIMAA1h j1zZ+45y9+wPUHaYlNjZGwe5NjLq2zhcVE9N8Qd2+9y0nZq3OkktYSrwlNIF68UQ5E QOvsWbLLky9wWy4N+GoCaUMGWTz+VSA3nFSndl5A= From: David Gibson To: qemu-devel@nongnu.org, clg@kaod.org, qemu-ppc@nongnu.org Subject: [PATCH v4 05/19] spapr, xics, xive: Move cpu_intc_create from SpaprIrq to SpaprInterruptController Date: Wed, 9 Oct 2019 17:08:04 +1100 Message-Id: <20191009060818.29719-6-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191009060818.29719-1-david@gibson.dropbear.id.au> References: <20191009060818.29719-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jason Wang , Riku Voipio , groug@kaod.org, Laurent Vivier , Paolo Bonzini , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , philmd@redhat.com, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" This method essentially represents code which belongs to the interrupt controller, but needs to be called on all possible intcs, rather than just the currently active one. The "dual" version therefore calls into the xics and xive versions confusingly. Handle this more directly, by making it instead a method on the intc backend, and always calling it on every backend that exists. While we're there, streamline the error reporting a bit. Signed-off-by: David Gibson Reviewed-by: Greg Kurz Reviewed-by: C=C3=A9dric Le Goater --- hw/intc/spapr_xive.c | 25 ++++++++++++ hw/intc/xics_spapr.c | 18 +++++++++ hw/ppc/spapr_cpu_core.c | 3 +- hw/ppc/spapr_irq.c | 81 +++++++++++--------------------------- include/hw/ppc/spapr_irq.h | 13 +++++- 5 files changed, 79 insertions(+), 61 deletions(-) diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c index b67e9c3245..9338daba3d 100644 --- a/hw/intc/spapr_xive.c +++ b/hw/intc/spapr_xive.c @@ -495,10 +495,33 @@ static Property spapr_xive_properties[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 +static int spapr_xive_cpu_intc_create(SpaprInterruptController *intc, + PowerPCCPU *cpu, Error **errp) +{ + SpaprXive *xive =3D SPAPR_XIVE(intc); + Object *obj; + SpaprCpuState *spapr_cpu =3D spapr_cpu_state(cpu); + + obj =3D xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(xive), errp); + if (!obj) { + return -1; + } + + spapr_cpu->tctx =3D XIVE_TCTX(obj); + + /* + * (TCG) Early setting the OS CAM line for hotplugged CPUs as they + * don't beneficiate from the reset of the XIVE IRQ backend + */ + spapr_xive_set_tctx_os_cam(spapr_cpu->tctx); + return 0; +} + static void spapr_xive_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); XiveRouterClass *xrc =3D XIVE_ROUTER_CLASS(klass); + SpaprInterruptControllerClass *sicc =3D SPAPR_INTC_CLASS(klass); =20 dc->desc =3D "sPAPR XIVE Interrupt Controller"; dc->props =3D spapr_xive_properties; @@ -511,6 +534,8 @@ static void spapr_xive_class_init(ObjectClass *klass, v= oid *data) xrc->get_nvt =3D spapr_xive_get_nvt; xrc->write_nvt =3D spapr_xive_write_nvt; xrc->get_tctx =3D spapr_xive_get_tctx; + + sicc->cpu_intc_create =3D spapr_xive_cpu_intc_create; } =20 static const TypeInfo spapr_xive_info =3D { diff --git a/hw/intc/xics_spapr.c b/hw/intc/xics_spapr.c index 4874e6be55..946311b858 100644 --- a/hw/intc/xics_spapr.c +++ b/hw/intc/xics_spapr.c @@ -330,13 +330,31 @@ void spapr_dt_xics(SpaprMachineState *spapr, uint32_t= nr_servers, void *fdt, _FDT(fdt_setprop_cell(fdt, node, "phandle", phandle)); } =20 +static int xics_spapr_cpu_intc_create(SpaprInterruptController *intc, + PowerPCCPU *cpu, Error **errp) +{ + ICSState *ics =3D ICS_SPAPR(intc); + Object *obj; + SpaprCpuState *spapr_cpu =3D spapr_cpu_state(cpu); + + obj =3D icp_create(OBJECT(cpu), TYPE_ICP, ics->xics, errp); + if (!obj) { + return -1; + } + + spapr_cpu->icp =3D ICP(obj); + return 0; +} + static void ics_spapr_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); ICSStateClass *isc =3D ICS_CLASS(klass); + SpaprInterruptControllerClass *sicc =3D SPAPR_INTC_CLASS(klass); =20 device_class_set_parent_realize(dc, ics_spapr_realize, &isc->parent_realize); + sicc->cpu_intc_create =3D xics_spapr_cpu_intc_create; } =20 static const TypeInfo ics_spapr_info =3D { diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index 1d93de8161..3e4302c7d5 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -237,8 +237,7 @@ static void spapr_realize_vcpu(PowerPCCPU *cpu, SpaprMa= chineState *spapr, qemu_register_reset(spapr_cpu_reset, cpu); spapr_cpu_reset(cpu); =20 - spapr->irq->cpu_intc_create(spapr, cpu, &local_err); - if (local_err) { + if (spapr_irq_cpu_intc_create(spapr, cpu, &local_err) < 0) { goto error_unregister; } =20 diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c index 8791dec1ba..9cb2fc71ca 100644 --- a/hw/ppc/spapr_irq.c +++ b/hw/ppc/spapr_irq.c @@ -138,23 +138,6 @@ static void spapr_irq_print_info_xics(SpaprMachineStat= e *spapr, Monitor *mon) ics_pic_print_info(spapr->ics, mon); } =20 -static void spapr_irq_cpu_intc_create_xics(SpaprMachineState *spapr, - PowerPCCPU *cpu, Error **errp) -{ - Error *local_err =3D NULL; - Object *obj; - SpaprCpuState *spapr_cpu =3D spapr_cpu_state(cpu); - - obj =3D icp_create(OBJECT(cpu), TYPE_ICP, XICS_FABRIC(spapr), - &local_err); - if (local_err) { - error_propagate(errp, local_err); - return; - } - - spapr_cpu->icp =3D ICP(obj); -} - static int spapr_irq_post_load_xics(SpaprMachineState *spapr, int version_= id) { if (!kvm_irqchip_in_kernel()) { @@ -203,7 +186,6 @@ SpaprIrq spapr_irq_xics =3D { .free =3D spapr_irq_free_xics, .print_info =3D spapr_irq_print_info_xics, .dt_populate =3D spapr_dt_xics, - .cpu_intc_create =3D spapr_irq_cpu_intc_create_xics, .post_load =3D spapr_irq_post_load_xics, .reset =3D spapr_irq_reset_xics, .set_irq =3D spapr_irq_set_irq_xics, @@ -239,28 +221,6 @@ static void spapr_irq_print_info_xive(SpaprMachineStat= e *spapr, spapr_xive_pic_print_info(spapr->xive, mon); } =20 -static void spapr_irq_cpu_intc_create_xive(SpaprMachineState *spapr, - PowerPCCPU *cpu, Error **errp) -{ - Error *local_err =3D NULL; - Object *obj; - SpaprCpuState *spapr_cpu =3D spapr_cpu_state(cpu); - - obj =3D xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(spapr->xive), &local= _err); - if (local_err) { - error_propagate(errp, local_err); - return; - } - - spapr_cpu->tctx =3D XIVE_TCTX(obj); - - /* - * (TCG) Early setting the OS CAM line for hotplugged CPUs as they - * don't beneficiate from the reset of the XIVE IRQ backend - */ - spapr_xive_set_tctx_os_cam(spapr_cpu->tctx); -} - static int spapr_irq_post_load_xive(SpaprMachineState *spapr, int version_= id) { return spapr_xive_post_load(spapr->xive, version_id); @@ -316,7 +276,6 @@ SpaprIrq spapr_irq_xive =3D { .free =3D spapr_irq_free_xive, .print_info =3D spapr_irq_print_info_xive, .dt_populate =3D spapr_dt_xive, - .cpu_intc_create =3D spapr_irq_cpu_intc_create_xive, .post_load =3D spapr_irq_post_load_xive, .reset =3D spapr_irq_reset_xive, .set_irq =3D spapr_irq_set_irq_xive, @@ -381,20 +340,6 @@ static void spapr_irq_dt_populate_dual(SpaprMachineSta= te *spapr, spapr_irq_current(spapr)->dt_populate(spapr, nr_servers, fdt, phandle); } =20 -static void spapr_irq_cpu_intc_create_dual(SpaprMachineState *spapr, - PowerPCCPU *cpu, Error **errp) -{ - Error *local_err =3D NULL; - - spapr_irq_xive.cpu_intc_create(spapr, cpu, &local_err); - if (local_err) { - error_propagate(errp, local_err); - return; - } - - spapr_irq_xics.cpu_intc_create(spapr, cpu, errp); -} - static int spapr_irq_post_load_dual(SpaprMachineState *spapr, int version_= id) { /* @@ -460,7 +405,6 @@ SpaprIrq spapr_irq_dual =3D { .free =3D spapr_irq_free_dual, .print_info =3D spapr_irq_print_info_dual, .dt_populate =3D spapr_irq_dt_populate_dual, - .cpu_intc_create =3D spapr_irq_cpu_intc_create_dual, .post_load =3D spapr_irq_post_load_dual, .reset =3D spapr_irq_reset_dual, .set_irq =3D spapr_irq_set_irq_dual, @@ -527,6 +471,30 @@ static int spapr_irq_check(SpaprMachineState *spapr, E= rror **errp) /* * sPAPR IRQ frontend routines for devices */ +#define ALL_INTCS(spapr_) \ + { SPAPR_INTC((spapr_)->ics), SPAPR_INTC((spapr_)->xive), } + +int spapr_irq_cpu_intc_create(SpaprMachineState *spapr, + PowerPCCPU *cpu, Error **errp) +{ + SpaprInterruptController *intcs[] =3D ALL_INTCS(spapr); + int i; + int rc; + + for (i =3D 0; i < ARRAY_SIZE(intcs); i++) { + SpaprInterruptController *intc =3D intcs[i]; + if (intc) { + SpaprInterruptControllerClass *sicc =3D SPAPR_INTC_GET_CLASS(i= ntc); + rc =3D sicc->cpu_intc_create(intc, cpu, errp); + if (rc < 0) { + return rc; + } + } + } + + return 0; +} + void spapr_irq_init(SpaprMachineState *spapr, Error **errp) { MachineState *machine =3D MACHINE(spapr); @@ -762,7 +730,6 @@ SpaprIrq spapr_irq_xics_legacy =3D { .free =3D spapr_irq_free_xics, .print_info =3D spapr_irq_print_info_xics, .dt_populate =3D spapr_dt_xics, - .cpu_intc_create =3D spapr_irq_cpu_intc_create_xics, .post_load =3D spapr_irq_post_load_xics, .reset =3D spapr_irq_reset_xics, .set_irq =3D spapr_irq_set_irq_xics, diff --git a/include/hw/ppc/spapr_irq.h b/include/hw/ppc/spapr_irq.h index b9398e0be3..5e641e23c1 100644 --- a/include/hw/ppc/spapr_irq.h +++ b/include/hw/ppc/spapr_irq.h @@ -43,8 +43,19 @@ typedef struct SpaprInterruptController SpaprInterruptCo= ntroller; =20 typedef struct SpaprInterruptControllerClass { InterfaceClass parent; + + /* + * These methods will typically be called on all intcs, active and + * inactive + */ + int (*cpu_intc_create)(SpaprInterruptController *intc, + PowerPCCPU *cpu, Error **errp); } SpaprInterruptControllerClass; =20 +int spapr_irq_cpu_intc_create(SpaprMachineState *spapr, + PowerPCCPU *cpu, Error **errp); + + void spapr_irq_msi_init(SpaprMachineState *spapr, uint32_t nr_msis); int spapr_irq_msi_alloc(SpaprMachineState *spapr, uint32_t num, bool align, Error **errp); @@ -61,8 +72,6 @@ typedef struct SpaprIrq { void (*print_info)(SpaprMachineState *spapr, Monitor *mon); void (*dt_populate)(SpaprMachineState *spapr, uint32_t nr_servers, void *fdt, uint32_t phandle); - void (*cpu_intc_create)(SpaprMachineState *spapr, PowerPCCPU *cpu, - Error **errp); int (*post_load)(SpaprMachineState *spapr, int version_id); void (*reset)(SpaprMachineState *spapr, Error **errp); void (*set_irq)(void *opaque, int srcno, int val); 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Wed, 09 Oct 2019 02:08:37 -0400 Received: from bilbo.ozlabs.org ([203.11.71.1]:35991 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iI59C-0006Ub-IR; Wed, 09 Oct 2019 02:08:30 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 46p3gD4qYJz9sQw; Wed, 9 Oct 2019 17:08:24 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1570601304; bh=3rarXC+2dGixFEg3CKdOUSqUn8XUU6WBiaqJUrhqbCM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HK+nEZ5/2ZuUxpjo9UJxVt5qYQ8h7wZWW18cmF8Kl7dU4MezVOOOWH/GopYAnCzJh 7/bWXX8ze5wAKQZ6XyGjay8iGpusFz+YDfbYJFnK9/JFW/s+P5iPIUNXUyng5jklPR BbfoZGpgul3uvAoF8eHpO93vAvtDn6DwIW781eIM= From: David Gibson To: qemu-devel@nongnu.org, clg@kaod.org, qemu-ppc@nongnu.org Subject: [PATCH v4 06/19] spapr, xics, xive: Move irq claim and free from SpaprIrq to SpaprInterruptController Date: Wed, 9 Oct 2019 17:08:05 +1100 Message-Id: <20191009060818.29719-7-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191009060818.29719-1-david@gibson.dropbear.id.au> References: <20191009060818.29719-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jason Wang , Riku Voipio , groug@kaod.org, Laurent Vivier , Paolo Bonzini , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , philmd@redhat.com, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" These methods, like cpu_intc_create, really belong to the interrupt controller, but need to be called on all possible intcs. Like cpu_intc_create, therefore, make them methods on the intc and always call it for all existing intcs. Signed-off-by: David Gibson Reviewed-by: Greg Kurz Reviewed-by: C=C3=A9dric Le Goater --- hw/intc/spapr_xive.c | 71 ++++++++++++----------- hw/intc/xics_spapr.c | 29 ++++++++++ hw/ppc/spapr_irq.c | 110 +++++++++++------------------------- include/hw/ppc/spapr_irq.h | 5 +- include/hw/ppc/spapr_xive.h | 2 - 5 files changed, 102 insertions(+), 115 deletions(-) diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c index 9338daba3d..ff1a175b44 100644 --- a/hw/intc/spapr_xive.c +++ b/hw/intc/spapr_xive.c @@ -487,6 +487,42 @@ static const VMStateDescription vmstate_spapr_xive =3D= { }, }; =20 +static int spapr_xive_claim_irq(SpaprInterruptController *intc, int lisn, + bool lsi, Error **errp) +{ + SpaprXive *xive =3D SPAPR_XIVE(intc); + XiveSource *xsrc =3D &xive->source; + + assert(lisn < xive->nr_irqs); + + if (xive_eas_is_valid(&xive->eat[lisn])) { + error_setg(errp, "IRQ %d is not free", lisn); + return -EBUSY; + } + + /* + * Set default values when allocating an IRQ number + */ + xive->eat[lisn].w |=3D cpu_to_be64(EAS_VALID | EAS_MASKED); + if (lsi) { + xive_source_irq_set_lsi(xsrc, lisn); + } + + if (kvm_irqchip_in_kernel()) { + return kvmppc_xive_source_reset_one(xsrc, lisn, errp); + } + + return 0; +} + +static void spapr_xive_free_irq(SpaprInterruptController *intc, int lisn) +{ + SpaprXive *xive =3D SPAPR_XIVE(intc); + assert(lisn < xive->nr_irqs); + + xive->eat[lisn].w &=3D cpu_to_be64(~EAS_VALID); +} + static Property spapr_xive_properties[] =3D { DEFINE_PROP_UINT32("nr-irqs", SpaprXive, nr_irqs, 0), DEFINE_PROP_UINT32("nr-ends", SpaprXive, nr_ends, 0), @@ -536,6 +572,8 @@ static void spapr_xive_class_init(ObjectClass *klass, v= oid *data) xrc->get_tctx =3D spapr_xive_get_tctx; =20 sicc->cpu_intc_create =3D spapr_xive_cpu_intc_create; + sicc->claim_irq =3D spapr_xive_claim_irq; + sicc->free_irq =3D spapr_xive_free_irq; } =20 static const TypeInfo spapr_xive_info =3D { @@ -557,39 +595,6 @@ static void spapr_xive_register_types(void) =20 type_init(spapr_xive_register_types) =20 -int spapr_xive_irq_claim(SpaprXive *xive, int lisn, bool lsi, Error **errp) -{ - XiveSource *xsrc =3D &xive->source; - - assert(lisn < xive->nr_irqs); - - if (xive_eas_is_valid(&xive->eat[lisn])) { - error_setg(errp, "IRQ %d is not free", lisn); - return -EBUSY; - } - - /* - * Set default values when allocating an IRQ number - */ - xive->eat[lisn].w |=3D cpu_to_be64(EAS_VALID | EAS_MASKED); - if (lsi) { - xive_source_irq_set_lsi(xsrc, lisn); - } - - if (kvm_irqchip_in_kernel()) { - return kvmppc_xive_source_reset_one(xsrc, lisn, errp); - } - - return 0; -} - -void spapr_xive_irq_free(SpaprXive *xive, int lisn) -{ - assert(lisn < xive->nr_irqs); - - xive->eat[lisn].w &=3D cpu_to_be64(~EAS_VALID); -} - /* * XIVE hcalls * diff --git a/hw/intc/xics_spapr.c b/hw/intc/xics_spapr.c index 946311b858..224fe1efcd 100644 --- a/hw/intc/xics_spapr.c +++ b/hw/intc/xics_spapr.c @@ -346,6 +346,33 @@ static int xics_spapr_cpu_intc_create(SpaprInterruptCo= ntroller *intc, return 0; } =20 +static int xics_spapr_claim_irq(SpaprInterruptController *intc, int irq, + bool lsi, Error **errp) +{ + ICSState *ics =3D ICS_SPAPR(intc); + + assert(ics); + assert(ics_valid_irq(ics, irq)); + + if (!ics_irq_free(ics, irq - ics->offset)) { + error_setg(errp, "IRQ %d is not free", irq); + return -EBUSY; + } + + ics_set_irq_type(ics, irq - ics->offset, lsi); + return 0; +} + +static void xics_spapr_free_irq(SpaprInterruptController *intc, int irq) +{ + ICSState *ics =3D ICS_SPAPR(intc); + uint32_t srcno =3D irq - ics->offset; + + assert(ics_valid_irq(ics, irq)); + + memset(&ics->irqs[srcno], 0, sizeof(ICSIRQState)); +} + static void ics_spapr_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -355,6 +382,8 @@ static void ics_spapr_class_init(ObjectClass *klass, vo= id *data) device_class_set_parent_realize(dc, ics_spapr_realize, &isc->parent_realize); sicc->cpu_intc_create =3D xics_spapr_cpu_intc_create; + sicc->claim_irq =3D xics_spapr_claim_irq; + sicc->free_irq =3D xics_spapr_free_irq; } =20 static const TypeInfo ics_spapr_info =3D { diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c index 9cb2fc71ca..83882cfad3 100644 --- a/hw/ppc/spapr_irq.c +++ b/hw/ppc/spapr_irq.c @@ -98,33 +98,6 @@ static void spapr_irq_init_kvm(SpaprMachineState *spapr, * XICS IRQ backend. */ =20 -static int spapr_irq_claim_xics(SpaprMachineState *spapr, int irq, bool ls= i, - Error **errp) -{ - ICSState *ics =3D spapr->ics; - - assert(ics); - assert(ics_valid_irq(ics, irq)); - - if (!ics_irq_free(ics, irq - ics->offset)) { - error_setg(errp, "IRQ %d is not free", irq); - return -1; - } - - ics_set_irq_type(ics, irq - ics->offset, lsi); - return 0; -} - -static void spapr_irq_free_xics(SpaprMachineState *spapr, int irq) -{ - ICSState *ics =3D spapr->ics; - uint32_t srcno =3D irq - ics->offset; - - assert(ics_valid_irq(ics, irq)); - - memset(&ics->irqs[srcno], 0, sizeof(ICSIRQState)); -} - static void spapr_irq_print_info_xics(SpaprMachineState *spapr, Monitor *m= on) { CPUState *cs; @@ -182,8 +155,6 @@ SpaprIrq spapr_irq_xics =3D { .xics =3D true, .xive =3D false, =20 - .claim =3D spapr_irq_claim_xics, - .free =3D spapr_irq_free_xics, .print_info =3D spapr_irq_print_info_xics, .dt_populate =3D spapr_dt_xics, .post_load =3D spapr_irq_post_load_xics, @@ -196,17 +167,6 @@ SpaprIrq spapr_irq_xics =3D { * XIVE IRQ backend. */ =20 -static int spapr_irq_claim_xive(SpaprMachineState *spapr, int irq, bool ls= i, - Error **errp) -{ - return spapr_xive_irq_claim(spapr->xive, irq, lsi, errp); -} - -static void spapr_irq_free_xive(SpaprMachineState *spapr, int irq) -{ - spapr_xive_irq_free(spapr->xive, irq); -} - static void spapr_irq_print_info_xive(SpaprMachineState *spapr, Monitor *mon) { @@ -272,8 +232,6 @@ SpaprIrq spapr_irq_xive =3D { .xics =3D false, .xive =3D true, =20 - .claim =3D spapr_irq_claim_xive, - .free =3D spapr_irq_free_xive, .print_info =3D spapr_irq_print_info_xive, .dt_populate =3D spapr_dt_xive, .post_load =3D spapr_irq_post_load_xive, @@ -301,33 +259,6 @@ static SpaprIrq *spapr_irq_current(SpaprMachineState *= spapr) &spapr_irq_xive : &spapr_irq_xics; } =20 -static int spapr_irq_claim_dual(SpaprMachineState *spapr, int irq, bool ls= i, - Error **errp) -{ - Error *local_err =3D NULL; - int ret; - - ret =3D spapr_irq_xics.claim(spapr, irq, lsi, &local_err); - if (local_err) { - error_propagate(errp, local_err); - return ret; - } - - ret =3D spapr_irq_xive.claim(spapr, irq, lsi, &local_err); - if (local_err) { - error_propagate(errp, local_err); - return ret; - } - - return ret; -} - -static void spapr_irq_free_dual(SpaprMachineState *spapr, int irq) -{ - spapr_irq_xics.free(spapr, irq); - spapr_irq_xive.free(spapr, irq); -} - static void spapr_irq_print_info_dual(SpaprMachineState *spapr, Monitor *m= on) { spapr_irq_current(spapr)->print_info(spapr, mon); @@ -401,8 +332,6 @@ SpaprIrq spapr_irq_dual =3D { .xics =3D true, .xive =3D true, =20 - .claim =3D spapr_irq_claim_dual, - .free =3D spapr_irq_free_dual, .print_info =3D spapr_irq_print_info_dual, .dt_populate =3D spapr_irq_dt_populate_dual, .post_load =3D spapr_irq_post_load_dual, @@ -572,8 +501,11 @@ void spapr_irq_init(SpaprMachineState *spapr, Error **= errp) =20 /* Enable the CPU IPIs */ for (i =3D 0; i < nr_servers; ++i) { - if (spapr_xive_irq_claim(spapr->xive, SPAPR_IRQ_IPI + i, - false, errp) < 0) { + SpaprInterruptControllerClass *sicc + =3D SPAPR_INTC_GET_CLASS(spapr->xive); + + if (sicc->claim_irq(SPAPR_INTC(spapr->xive), SPAPR_IRQ_IPI + i, + false, errp) < 0) { return; } } @@ -587,21 +519,45 @@ void spapr_irq_init(SpaprMachineState *spapr, Error *= *errp) =20 int spapr_irq_claim(SpaprMachineState *spapr, int irq, bool lsi, Error **e= rrp) { + SpaprInterruptController *intcs[] =3D ALL_INTCS(spapr); + int i; + int rc; + assert(irq >=3D SPAPR_XIRQ_BASE); assert(irq < (spapr->irq->nr_xirqs + SPAPR_XIRQ_BASE)); =20 - return spapr->irq->claim(spapr, irq, lsi, errp); + for (i =3D 0; i < ARRAY_SIZE(intcs); i++) { + SpaprInterruptController *intc =3D intcs[i]; + if (intc) { + SpaprInterruptControllerClass *sicc =3D SPAPR_INTC_GET_CLASS(i= ntc); + rc =3D sicc->claim_irq(intc, irq, lsi, errp); + if (rc < 0) { + return rc; + } + } + } + + return 0; } =20 void spapr_irq_free(SpaprMachineState *spapr, int irq, int num) { - int i; + SpaprInterruptController *intcs[] =3D ALL_INTCS(spapr); + int i, j; =20 assert(irq >=3D SPAPR_XIRQ_BASE); assert((irq + num) <=3D (spapr->irq->nr_xirqs + SPAPR_XIRQ_BASE)); =20 for (i =3D irq; i < (irq + num); i++) { - spapr->irq->free(spapr, i); + for (j =3D 0; j < ARRAY_SIZE(intcs); j++) { + SpaprInterruptController *intc =3D intcs[j]; + + if (intc) { + SpaprInterruptControllerClass *sicc + =3D SPAPR_INTC_GET_CLASS(intc); + sicc->free_irq(intc, i); + } + } } } =20 @@ -726,8 +682,6 @@ SpaprIrq spapr_irq_xics_legacy =3D { .xics =3D true, .xive =3D false, =20 - .claim =3D spapr_irq_claim_xics, - .free =3D spapr_irq_free_xics, .print_info =3D spapr_irq_print_info_xics, .dt_populate =3D spapr_dt_xics, .post_load =3D spapr_irq_post_load_xics, diff --git a/include/hw/ppc/spapr_irq.h b/include/hw/ppc/spapr_irq.h index 5e641e23c1..adfef0fcbe 100644 --- a/include/hw/ppc/spapr_irq.h +++ b/include/hw/ppc/spapr_irq.h @@ -50,6 +50,9 @@ typedef struct SpaprInterruptControllerClass { */ int (*cpu_intc_create)(SpaprInterruptController *intc, PowerPCCPU *cpu, Error **errp); + int (*claim_irq)(SpaprInterruptController *intc, int irq, bool lsi, + Error **errp); + void (*free_irq)(SpaprInterruptController *intc, int irq); } SpaprInterruptControllerClass; =20 int spapr_irq_cpu_intc_create(SpaprMachineState *spapr, @@ -67,8 +70,6 @@ typedef struct SpaprIrq { bool xics; bool xive; =20 - int (*claim)(SpaprMachineState *spapr, int irq, bool lsi, Error **errp= ); - void (*free)(SpaprMachineState *spapr, int irq); void (*print_info)(SpaprMachineState *spapr, Monitor *mon); void (*dt_populate)(SpaprMachineState *spapr, uint32_t nr_servers, void *fdt, uint32_t phandle); diff --git a/include/hw/ppc/spapr_xive.h b/include/hw/ppc/spapr_xive.h index 0df20a6590..8f875673f5 100644 --- a/include/hw/ppc/spapr_xive.h +++ b/include/hw/ppc/spapr_xive.h @@ -54,8 +54,6 @@ typedef struct SpaprXive { */ #define SPAPR_XIVE_BLOCK_ID 0x0 =20 -int spapr_xive_irq_claim(SpaprXive *xive, int lisn, bool lsi, Error **errp= ); -void spapr_xive_irq_free(SpaprXive *xive, int lisn); void spapr_xive_pic_print_info(SpaprXive *xive, Monitor *mon); int spapr_xive_post_load(SpaprXive *xive, int version_id); =20 --=20 2.21.0 From nobody Sat Apr 27 01:55:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1570638275; cv=none; d=zoho.com; s=zohoarc; b=iEQzCDpcIDT3fzj3XrNycmxZMJJwCSPnoG/yUoFZuwUXNBg+fiGen8cTZQv8F3ok0AgvAnyoMC2qOd2Gl275Tcz/oEg6K3YCgtjKHPibW/+Yxyl67nETK9LgkcNX1Qyz4U10DYGEyzaQqSpWgWQYpXtrAi3EPZXyKY4HtOg9XM8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1570638275; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Wed, 09 Oct 2019 02:08:34 -0400 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:59717 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iI59C-0006Uh-Qj; Wed, 09 Oct 2019 02:08:32 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 46p3gD5Xq7z9sPw; Wed, 9 Oct 2019 17:08:24 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1570601304; bh=XUPxcRcTe2kkMQz3PgmYd462tBPoK4iFHjEdYV6FO8s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oAYFrAjcRgaoJpkPMk/l2hzdCn/7PKSwStpGpUHvjYfPST1BN1Xd8FLFM+KJKFcJZ qaLR+pkCZHn9oHEPceW78MenqYhxfErHFyq+2ZDDlNOgc9+4/INI52IAYr7qdNgjVY +fIfDPmxwi4nS2zqwP0H5Nfcfw4tdEq/gg0HHGZE= From: David Gibson To: qemu-devel@nongnu.org, clg@kaod.org, qemu-ppc@nongnu.org Subject: [PATCH v4 07/19] spapr: Formalize notion of active interrupt controller Date: Wed, 9 Oct 2019 17:08:06 +1100 Message-Id: <20191009060818.29719-8-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191009060818.29719-1-david@gibson.dropbear.id.au> References: <20191009060818.29719-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jason Wang , Riku Voipio , groug@kaod.org, Laurent Vivier , Paolo Bonzini , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , philmd@redhat.com, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" spapr now has the mechanism of constructing both XICS and XIVE instances of the SpaprInterruptController interface. However, only one of the interrupt controllers will actually be active at any given time, depending on feature negotiation with the guest. This is handled in the current code via spapr_irq_current() which checks the OV5 vector from feature negotiation to determine the current backend. Determining the active controller at the point we need it like this can be pretty confusing, because it makes it very non obvious at what points the active controller can change. This can make it difficult to reason about the code and where a change of active controller could appear in sequence with other events. Make this mechanism more explicit by adding an 'active_intc' pointer and an explicit spapr_irq_update_active_intc() function to update it from the CAS state. We also add hooks on the intc backend which will get called when it is activated or deactivated. For now we just introduce the switch and hooks, later patches will actually start using them. Signed-off-by: David Gibson Reviewed-by: Greg Kurz Reviewed-by: C=C3=A9dric Le Goater --- hw/ppc/spapr_irq.c | 51 ++++++++++++++++++++++++++++++++++++++ include/hw/ppc/spapr.h | 5 ++-- include/hw/ppc/spapr_irq.h | 5 ++++ 3 files changed, 59 insertions(+), 2 deletions(-) diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c index 83882cfad3..249a2688ac 100644 --- a/hw/ppc/spapr_irq.c +++ b/hw/ppc/spapr_irq.c @@ -586,6 +586,7 @@ qemu_irq spapr_qirq(SpaprMachineState *spapr, int irq) =20 int spapr_irq_post_load(SpaprMachineState *spapr, int version_id) { + spapr_irq_update_active_intc(spapr); return spapr->irq->post_load(spapr, version_id); } =20 @@ -593,6 +594,8 @@ void spapr_irq_reset(SpaprMachineState *spapr, Error **= errp) { assert(!spapr->irq_map || bitmap_empty(spapr->irq_map, spapr->irq_map_= nr)); =20 + spapr_irq_update_active_intc(spapr); + if (spapr->irq->reset) { spapr->irq->reset(spapr, errp); } @@ -619,6 +622,54 @@ int spapr_irq_get_phandle(SpaprMachineState *spapr, vo= id *fdt, Error **errp) return phandle; } =20 +static void set_active_intc(SpaprMachineState *spapr, + SpaprInterruptController *new_intc) +{ + SpaprInterruptControllerClass *sicc; + + assert(new_intc); + + if (new_intc =3D=3D spapr->active_intc) { + /* Nothing to do */ + return; + } + + if (spapr->active_intc) { + sicc =3D SPAPR_INTC_GET_CLASS(spapr->active_intc); + if (sicc->deactivate) { + sicc->deactivate(spapr->active_intc); + } + } + + sicc =3D SPAPR_INTC_GET_CLASS(new_intc); + if (sicc->activate) { + sicc->activate(new_intc, &error_fatal); + } + + spapr->active_intc =3D new_intc; +} + +void spapr_irq_update_active_intc(SpaprMachineState *spapr) +{ + SpaprInterruptController *new_intc; + + if (!spapr->ics) { + /* + * XXX before we run CAS, ov5_cas is initialized empty, which + * indicates XICS, even if we have ic-mode=3Dxive. TODO: clean + * up the CAS path so that we have a clearer way of handling + * this. + */ + new_intc =3D SPAPR_INTC(spapr->xive); + } else if (spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { + new_intc =3D SPAPR_INTC(spapr->xive); + } else { + new_intc =3D SPAPR_INTC(spapr->ics); + } + + set_active_intc(spapr, new_intc); +} + /* * XICS legacy routines - to deprecate one day */ diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index cbd1a4c9f3..763da757f0 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -143,7 +143,6 @@ struct SpaprMachineState { struct SpaprVioBus *vio_bus; QLIST_HEAD(, SpaprPhbState) phbs; struct SpaprNvram *nvram; - ICSState *ics; SpaprRtcState rtc; =20 SpaprResizeHpt resize_hpt; @@ -195,9 +194,11 @@ struct SpaprMachineState { =20 int32_t irq_map_nr; unsigned long *irq_map; - SpaprXive *xive; SpaprIrq *irq; qemu_irq *qirqs; + SpaprInterruptController *active_intc; + ICSState *ics; + SpaprXive *xive; =20 bool cmd_line_caps[SPAPR_CAP_NUM]; SpaprCapabilities def, eff, mig; diff --git a/include/hw/ppc/spapr_irq.h b/include/hw/ppc/spapr_irq.h index adfef0fcbe..593059eff5 100644 --- a/include/hw/ppc/spapr_irq.h +++ b/include/hw/ppc/spapr_irq.h @@ -44,6 +44,9 @@ typedef struct SpaprInterruptController SpaprInterruptCon= troller; typedef struct SpaprInterruptControllerClass { InterfaceClass parent; =20 + int (*activate)(SpaprInterruptController *intc, Error **errp); + void (*deactivate)(SpaprInterruptController *intc); + /* * These methods will typically be called on all intcs, active and * inactive @@ -55,6 +58,8 @@ typedef struct SpaprInterruptControllerClass { void (*free_irq)(SpaprInterruptController *intc, int irq); } SpaprInterruptControllerClass; =20 +void spapr_irq_update_active_intc(SpaprMachineState *spapr); + int spapr_irq_cpu_intc_create(SpaprMachineState *spapr, PowerPCCPU *cpu, Error **errp); =20 --=20 2.21.0 From nobody Sat Apr 27 01:55:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Wed, 09 Oct 2019 02:08:30 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 46p3gD67TJz9sQy; Wed, 9 Oct 2019 17:08:24 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1570601304; bh=Ab9C6EnO+kA6bxgu5OZl2lcLxTVVDXXeqlil5mmBZOk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iwLEGMbo2DPukU9uycDbzp/AEj2P8NGqBUFraCVEdt2/jykTrzh7YR+vSJwkyHuMg m6iy/USZ3IycnNSZDWcbdgIp5ZYvo3lj74HGUYyf080U4zj0206iHDJmXTlfm8faUv CyhEPjinjEVFtyEx4KbSnZl8AQYjHjy8CYj67pjU= From: David Gibson To: qemu-devel@nongnu.org, clg@kaod.org, qemu-ppc@nongnu.org Subject: [PATCH v4 08/19] spapr, xics, xive: Move set_irq from SpaprIrq to SpaprInterruptController Date: Wed, 9 Oct 2019 17:08:07 +1100 Message-Id: <20191009060818.29719-9-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191009060818.29719-1-david@gibson.dropbear.id.au> References: <20191009060818.29719-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jason Wang , Riku Voipio , groug@kaod.org, Laurent Vivier , Paolo Bonzini , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , philmd@redhat.com, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" This method depends only on the active irq controller. Now that we've formalized the notion of active controller we can dispatch directly through that, rather than dispatching via SpaprIrq with the dual version having to do a second conditional dispatch. Signed-off-by: David Gibson Reviewed-by: Greg Kurz Reviewed-by: C=C3=A9dric Le Goater --- hw/intc/spapr_xive.c | 12 +++++++++++ hw/intc/xics_spapr.c | 9 +++++++++ hw/ppc/spapr_irq.c | 41 ++++++++++---------------------------- include/hw/ppc/spapr_irq.h | 4 +++- 4 files changed, 34 insertions(+), 32 deletions(-) diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c index ff1a175b44..52d5e71793 100644 --- a/hw/intc/spapr_xive.c +++ b/hw/intc/spapr_xive.c @@ -553,6 +553,17 @@ static int spapr_xive_cpu_intc_create(SpaprInterruptCo= ntroller *intc, return 0; } =20 +static void spapr_xive_set_irq(SpaprInterruptController *intc, int irq, in= t val) +{ + SpaprXive *xive =3D SPAPR_XIVE(intc); + + if (kvm_irqchip_in_kernel()) { + kvmppc_xive_source_set_irq(&xive->source, irq, val); + } else { + xive_source_set_irq(&xive->source, irq, val); + } +} + static void spapr_xive_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -574,6 +585,7 @@ static void spapr_xive_class_init(ObjectClass *klass, v= oid *data) sicc->cpu_intc_create =3D spapr_xive_cpu_intc_create; sicc->claim_irq =3D spapr_xive_claim_irq; sicc->free_irq =3D spapr_xive_free_irq; + sicc->set_irq =3D spapr_xive_set_irq; } =20 static const TypeInfo spapr_xive_info =3D { diff --git a/hw/intc/xics_spapr.c b/hw/intc/xics_spapr.c index 224fe1efcd..02372697f6 100644 --- a/hw/intc/xics_spapr.c +++ b/hw/intc/xics_spapr.c @@ -373,6 +373,14 @@ static void xics_spapr_free_irq(SpaprInterruptControll= er *intc, int irq) memset(&ics->irqs[srcno], 0, sizeof(ICSIRQState)); } =20 +static void xics_spapr_set_irq(SpaprInterruptController *intc, int irq, in= t val) +{ + ICSState *ics =3D ICS_SPAPR(intc); + uint32_t srcno =3D irq - ics->offset; + + ics_set_irq(ics, srcno, val); +} + static void ics_spapr_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -384,6 +392,7 @@ static void ics_spapr_class_init(ObjectClass *klass, vo= id *data) sicc->cpu_intc_create =3D xics_spapr_cpu_intc_create; sicc->claim_irq =3D xics_spapr_claim_irq; sicc->free_irq =3D xics_spapr_free_irq; + sicc->set_irq =3D xics_spapr_set_irq; } =20 static const TypeInfo ics_spapr_info =3D { diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c index 249a2688ac..bfccb815ed 100644 --- a/hw/ppc/spapr_irq.c +++ b/hw/ppc/spapr_irq.c @@ -123,14 +123,6 @@ static int spapr_irq_post_load_xics(SpaprMachineState = *spapr, int version_id) return 0; } =20 -static void spapr_irq_set_irq_xics(void *opaque, int irq, int val) -{ - SpaprMachineState *spapr =3D opaque; - uint32_t srcno =3D irq - spapr->ics->offset; - - ics_set_irq(spapr->ics, srcno, val); -} - static void spapr_irq_reset_xics(SpaprMachineState *spapr, Error **errp) { Error *local_err =3D NULL; @@ -159,7 +151,6 @@ SpaprIrq spapr_irq_xics =3D { .dt_populate =3D spapr_dt_xics, .post_load =3D spapr_irq_post_load_xics, .reset =3D spapr_irq_reset_xics, - .set_irq =3D spapr_irq_set_irq_xics, .init_kvm =3D spapr_irq_init_kvm_xics, }; =20 @@ -208,17 +199,6 @@ static void spapr_irq_reset_xive(SpaprMachineState *sp= apr, Error **errp) spapr_xive_mmio_set_enabled(spapr->xive, true); } =20 -static void spapr_irq_set_irq_xive(void *opaque, int irq, int val) -{ - SpaprMachineState *spapr =3D opaque; - - if (kvm_irqchip_in_kernel()) { - kvmppc_xive_source_set_irq(&spapr->xive->source, irq, val); - } else { - xive_source_set_irq(&spapr->xive->source, irq, val); - } -} - static void spapr_irq_init_kvm_xive(SpaprMachineState *spapr, Error **errp) { if (kvm_enabled()) { @@ -236,7 +216,6 @@ SpaprIrq spapr_irq_xive =3D { .dt_populate =3D spapr_dt_xive, .post_load =3D spapr_irq_post_load_xive, .reset =3D spapr_irq_reset_xive, - .set_irq =3D spapr_irq_set_irq_xive, .init_kvm =3D spapr_irq_init_kvm_xive, }; =20 @@ -316,13 +295,6 @@ static void spapr_irq_reset_dual(SpaprMachineState *sp= apr, Error **errp) spapr_irq_current(spapr)->reset(spapr, errp); } =20 -static void spapr_irq_set_irq_dual(void *opaque, int irq, int val) -{ - SpaprMachineState *spapr =3D opaque; - - spapr_irq_current(spapr)->set_irq(spapr, irq, val); -} - /* * Define values in sync with the XIVE and XICS backend */ @@ -336,7 +308,6 @@ SpaprIrq spapr_irq_dual =3D { .dt_populate =3D spapr_irq_dt_populate_dual, .post_load =3D spapr_irq_post_load_dual, .reset =3D spapr_irq_reset_dual, - .set_irq =3D spapr_irq_set_irq_dual, .init_kvm =3D NULL, /* should not be used */ }; =20 @@ -424,6 +395,15 @@ int spapr_irq_cpu_intc_create(SpaprMachineState *spapr, return 0; } =20 +static void spapr_set_irq(void *opaque, int irq, int level) +{ + SpaprMachineState *spapr =3D SPAPR_MACHINE(opaque); + SpaprInterruptControllerClass *sicc + =3D SPAPR_INTC_GET_CLASS(spapr->active_intc); + + sicc->set_irq(spapr->active_intc, irq, level); +} + void spapr_irq_init(SpaprMachineState *spapr, Error **errp) { MachineState *machine =3D MACHINE(spapr); @@ -513,7 +493,7 @@ void spapr_irq_init(SpaprMachineState *spapr, Error **e= rrp) spapr_xive_hcall_init(spapr); } =20 - spapr->qirqs =3D qemu_allocate_irqs(spapr->irq->set_irq, spapr, + spapr->qirqs =3D qemu_allocate_irqs(spapr_set_irq, spapr, spapr->irq->nr_xirqs + SPAPR_XIRQ_BA= SE); } =20 @@ -737,7 +717,6 @@ SpaprIrq spapr_irq_xics_legacy =3D { .dt_populate =3D spapr_dt_xics, .post_load =3D spapr_irq_post_load_xics, .reset =3D spapr_irq_reset_xics, - .set_irq =3D spapr_irq_set_irq_xics, .init_kvm =3D spapr_irq_init_kvm_xics, }; =20 diff --git a/include/hw/ppc/spapr_irq.h b/include/hw/ppc/spapr_irq.h index 593059eff5..ece8d2ea48 100644 --- a/include/hw/ppc/spapr_irq.h +++ b/include/hw/ppc/spapr_irq.h @@ -56,6 +56,9 @@ typedef struct SpaprInterruptControllerClass { int (*claim_irq)(SpaprInterruptController *intc, int irq, bool lsi, Error **errp); void (*free_irq)(SpaprInterruptController *intc, int irq); + + /* These methods should only be called on the active intc */ + void (*set_irq)(SpaprInterruptController *intc, int irq, int val); } SpaprInterruptControllerClass; =20 void spapr_irq_update_active_intc(SpaprMachineState *spapr); @@ -80,7 +83,6 @@ typedef struct SpaprIrq { void *fdt, uint32_t phandle); int (*post_load)(SpaprMachineState *spapr, int version_id); void (*reset)(SpaprMachineState *spapr, Error **errp); - void (*set_irq)(void *opaque, int srcno, int val); void (*init_kvm)(SpaprMachineState *spapr, Error **errp); } SpaprIrq; =20 --=20 2.21.0 From nobody Sat Apr 27 01:55:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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s=201602; t=1570601304; bh=rDC9en2NhOoZSU23HaAIbKZkTSIJujfTw7OzEO3MZNk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=F6e/mGVxXLBYhxvzGsh8258Q2Ht4m+fyO0pttYtKd/l/ufbgQBw01i0pyV+G/mP2/ JSZQJxLHxqVxZsfOXpZW6Bl7+NMSxa3NEfiKuKRTWYhQY0qHNdlK5ghJhrfVG8u2Se Pkj7tIqwuCk+UTSbsot3etJ8pkE5V0CUBsmJW9Zs= From: David Gibson To: qemu-devel@nongnu.org, clg@kaod.org, qemu-ppc@nongnu.org Subject: [PATCH v4 09/19] spapr, xics, xive: Move print_info from SpaprIrq to SpaprInterruptController Date: Wed, 9 Oct 2019 17:08:08 +1100 Message-Id: <20191009060818.29719-10-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191009060818.29719-1-david@gibson.dropbear.id.au> References: <20191009060818.29719-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jason Wang , Riku Voipio , groug@kaod.org, Laurent Vivier , Paolo Bonzini , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , philmd@redhat.com, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" This method depends only on the active irq controller. Now that we've formalized the notion of active controller we can dispatch directly through that, rather than dispatching via SpaprIrq with the dual version having to do a second conditional dispatch. Signed-off-by: David Gibson Reviewed-by: Greg Kurz Reviewed-by: C=C3=A9dric Le Goater --- hw/intc/spapr_xive.c | 15 +++++++++++++ hw/intc/xics_spapr.c | 15 +++++++++++++ hw/ppc/spapr.c | 2 +- hw/ppc/spapr_irq.c | 44 +++++++------------------------------- include/hw/ppc/spapr_irq.h | 4 ++-- 5 files changed, 41 insertions(+), 39 deletions(-) diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c index 52d5e71793..700ec5c9c1 100644 --- a/hw/intc/spapr_xive.c +++ b/hw/intc/spapr_xive.c @@ -564,6 +564,20 @@ static void spapr_xive_set_irq(SpaprInterruptControlle= r *intc, int irq, int val) } } =20 +static void spapr_xive_print_info(SpaprInterruptController *intc, Monitor = *mon) +{ + SpaprXive *xive =3D SPAPR_XIVE(intc); + CPUState *cs; + + CPU_FOREACH(cs) { + PowerPCCPU *cpu =3D POWERPC_CPU(cs); + + xive_tctx_pic_print_info(spapr_cpu_state(cpu)->tctx, mon); + } + + spapr_xive_pic_print_info(xive, mon); +} + static void spapr_xive_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -586,6 +600,7 @@ static void spapr_xive_class_init(ObjectClass *klass, v= oid *data) sicc->claim_irq =3D spapr_xive_claim_irq; sicc->free_irq =3D spapr_xive_free_irq; sicc->set_irq =3D spapr_xive_set_irq; + sicc->print_info =3D spapr_xive_print_info; } =20 static const TypeInfo spapr_xive_info =3D { diff --git a/hw/intc/xics_spapr.c b/hw/intc/xics_spapr.c index 02372697f6..415defe394 100644 --- a/hw/intc/xics_spapr.c +++ b/hw/intc/xics_spapr.c @@ -381,6 +381,20 @@ static void xics_spapr_set_irq(SpaprInterruptControlle= r *intc, int irq, int val) ics_set_irq(ics, srcno, val); } =20 +static void xics_spapr_print_info(SpaprInterruptController *intc, Monitor = *mon) +{ + ICSState *ics =3D ICS_SPAPR(intc); + CPUState *cs; + + CPU_FOREACH(cs) { + PowerPCCPU *cpu =3D POWERPC_CPU(cs); + + icp_pic_print_info(spapr_cpu_state(cpu)->icp, mon); + } + + ics_pic_print_info(ics, mon); +} + static void ics_spapr_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -393,6 +407,7 @@ static void ics_spapr_class_init(ObjectClass *klass, vo= id *data) sicc->claim_irq =3D xics_spapr_claim_irq; sicc->free_irq =3D xics_spapr_free_irq; sicc->set_irq =3D xics_spapr_set_irq; + sicc->print_info =3D xics_spapr_print_info; } =20 static const TypeInfo ics_spapr_info =3D { diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 514a17ae74..6c38de5927 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -4271,7 +4271,7 @@ static void spapr_pic_print_info(InterruptStatsProvid= er *obj, { SpaprMachineState *spapr =3D SPAPR_MACHINE(obj); =20 - spapr->irq->print_info(spapr, mon); + spapr_irq_print_info(spapr, mon); monitor_printf(mon, "irqchip: %s\n", kvm_irqchip_in_kernel() ? "in-kernel" : "emulated"); } diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c index bfccb815ed..a29b527232 100644 --- a/hw/ppc/spapr_irq.c +++ b/hw/ppc/spapr_irq.c @@ -98,19 +98,6 @@ static void spapr_irq_init_kvm(SpaprMachineState *spapr, * XICS IRQ backend. */ =20 -static void spapr_irq_print_info_xics(SpaprMachineState *spapr, Monitor *m= on) -{ - CPUState *cs; - - CPU_FOREACH(cs) { - PowerPCCPU *cpu =3D POWERPC_CPU(cs); - - icp_pic_print_info(spapr_cpu_state(cpu)->icp, mon); - } - - ics_pic_print_info(spapr->ics, mon); -} - static int spapr_irq_post_load_xics(SpaprMachineState *spapr, int version_= id) { if (!kvm_irqchip_in_kernel()) { @@ -147,7 +134,6 @@ SpaprIrq spapr_irq_xics =3D { .xics =3D true, .xive =3D false, =20 - .print_info =3D spapr_irq_print_info_xics, .dt_populate =3D spapr_dt_xics, .post_load =3D spapr_irq_post_load_xics, .reset =3D spapr_irq_reset_xics, @@ -158,20 +144,6 @@ SpaprIrq spapr_irq_xics =3D { * XIVE IRQ backend. */ =20 -static void spapr_irq_print_info_xive(SpaprMachineState *spapr, - Monitor *mon) -{ - CPUState *cs; - - CPU_FOREACH(cs) { - PowerPCCPU *cpu =3D POWERPC_CPU(cs); - - xive_tctx_pic_print_info(spapr_cpu_state(cpu)->tctx, mon); - } - - spapr_xive_pic_print_info(spapr->xive, mon); -} - static int spapr_irq_post_load_xive(SpaprMachineState *spapr, int version_= id) { return spapr_xive_post_load(spapr->xive, version_id); @@ -212,7 +184,6 @@ SpaprIrq spapr_irq_xive =3D { .xics =3D false, .xive =3D true, =20 - .print_info =3D spapr_irq_print_info_xive, .dt_populate =3D spapr_dt_xive, .post_load =3D spapr_irq_post_load_xive, .reset =3D spapr_irq_reset_xive, @@ -238,11 +209,6 @@ static SpaprIrq *spapr_irq_current(SpaprMachineState *= spapr) &spapr_irq_xive : &spapr_irq_xics; } =20 -static void spapr_irq_print_info_dual(SpaprMachineState *spapr, Monitor *m= on) -{ - spapr_irq_current(spapr)->print_info(spapr, mon); -} - static void spapr_irq_dt_populate_dual(SpaprMachineState *spapr, uint32_t nr_servers, void *fdt, uint32_t phandle) @@ -304,7 +270,6 @@ SpaprIrq spapr_irq_dual =3D { .xics =3D true, .xive =3D true, =20 - .print_info =3D spapr_irq_print_info_dual, .dt_populate =3D spapr_irq_dt_populate_dual, .post_load =3D spapr_irq_post_load_dual, .reset =3D spapr_irq_reset_dual, @@ -404,6 +369,14 @@ static void spapr_set_irq(void *opaque, int irq, int l= evel) sicc->set_irq(spapr->active_intc, irq, level); } =20 +void spapr_irq_print_info(SpaprMachineState *spapr, Monitor *mon) +{ + SpaprInterruptControllerClass *sicc + =3D SPAPR_INTC_GET_CLASS(spapr->active_intc); + + sicc->print_info(spapr->active_intc, mon); +} + void spapr_irq_init(SpaprMachineState *spapr, Error **errp) { MachineState *machine =3D MACHINE(spapr); @@ -713,7 +686,6 @@ SpaprIrq spapr_irq_xics_legacy =3D { .xics =3D true, .xive =3D false, =20 - .print_info =3D spapr_irq_print_info_xics, .dt_populate =3D spapr_dt_xics, .post_load =3D spapr_irq_post_load_xics, .reset =3D spapr_irq_reset_xics, diff --git a/include/hw/ppc/spapr_irq.h b/include/hw/ppc/spapr_irq.h index ece8d2ea48..bdfeb3b107 100644 --- a/include/hw/ppc/spapr_irq.h +++ b/include/hw/ppc/spapr_irq.h @@ -59,13 +59,14 @@ typedef struct SpaprInterruptControllerClass { =20 /* These methods should only be called on the active intc */ void (*set_irq)(SpaprInterruptController *intc, int irq, int val); + void (*print_info)(SpaprInterruptController *intc, Monitor *mon); } SpaprInterruptControllerClass; =20 void spapr_irq_update_active_intc(SpaprMachineState *spapr); =20 int spapr_irq_cpu_intc_create(SpaprMachineState *spapr, PowerPCCPU *cpu, Error **errp); - +void spapr_irq_print_info(SpaprMachineState *spapr, Monitor *mon); =20 void spapr_irq_msi_init(SpaprMachineState *spapr, uint32_t nr_msis); int spapr_irq_msi_alloc(SpaprMachineState *spapr, uint32_t num, bool align, @@ -78,7 +79,6 @@ typedef struct SpaprIrq { bool xics; bool xive; =20 - void (*print_info)(SpaprMachineState *spapr, Monitor *mon); void (*dt_populate)(SpaprMachineState *spapr, uint32_t nr_servers, void *fdt, uint32_t phandle); int (*post_load)(SpaprMachineState *spapr, int version_id); --=20 2.21.0 From nobody Sat Apr 27 01:55:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; 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s=201602; t=1570601305; bh=/FMcuDxWdVA/d9Jlyp+IKrI+II7IqXIVFk0oTgqL1Vw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AwZv5tEXo+C/+QxNDa0eTRPUjpZaBgWmJfr7yust2DwpB3hBf4RvCA2m/lqNDtF7P dpSsxAOODyH1FsRUrFHGwGJSKP2fjqXzQC4AQ4tmRh04HherXE4UFjeoDkg8ovzEqy VrqMStYWC1wRlz54gbF4Ji9fWTZlbqT94x0Q3srY= From: David Gibson To: qemu-devel@nongnu.org, clg@kaod.org, qemu-ppc@nongnu.org Subject: [PATCH v4 10/19] spapr, xics, xive: Move dt_populate from SpaprIrq to SpaprInterruptController Date: Wed, 9 Oct 2019 17:08:09 +1100 Message-Id: <20191009060818.29719-11-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191009060818.29719-1-david@gibson.dropbear.id.au> References: <20191009060818.29719-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jason Wang , Riku Voipio , groug@kaod.org, Laurent Vivier , Paolo Bonzini , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , philmd@redhat.com, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" This method depends only on the active irq controller. Now that we've formalized the notion of active controller we can dispatch directly through that, rather than dispatching via SpaprIrq with the dual version having to do a second conditional dispatch. Signed-off-by: David Gibson Reviewed-by: Greg Kurz Reviewed-by: C=C3=A9dric Le Goater --- hw/intc/spapr_xive.c | 125 ++++++++++++++++++------------------ hw/intc/xics_spapr.c | 5 +- hw/ppc/spapr.c | 3 +- hw/ppc/spapr_irq.c | 20 +++--- include/hw/ppc/spapr_irq.h | 6 +- include/hw/ppc/spapr_xive.h | 2 - include/hw/ppc/xics_spapr.h | 2 - 7 files changed, 80 insertions(+), 83 deletions(-) diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c index 700ec5c9c1..37ffb74ca5 100644 --- a/hw/intc/spapr_xive.c +++ b/hw/intc/spapr_xive.c @@ -578,6 +578,68 @@ static void spapr_xive_print_info(SpaprInterruptContro= ller *intc, Monitor *mon) spapr_xive_pic_print_info(xive, mon); } =20 +static void spapr_xive_dt(SpaprInterruptController *intc, uint32_t nr_serv= ers, + void *fdt, uint32_t phandle) +{ + SpaprXive *xive =3D SPAPR_XIVE(intc); + int node; + uint64_t timas[2 * 2]; + /* Interrupt number ranges for the IPIs */ + uint32_t lisn_ranges[] =3D { + cpu_to_be32(0), + cpu_to_be32(nr_servers), + }; + /* + * EQ size - the sizes of pages supported by the system 4K, 64K, + * 2M, 16M. We only advertise 64K for the moment. + */ + uint32_t eq_sizes[] =3D { + cpu_to_be32(16), /* 64K */ + }; + /* + * The following array is in sync with the reserved priorities + * defined by the 'spapr_xive_priority_is_reserved' routine. + */ + uint32_t plat_res_int_priorities[] =3D { + cpu_to_be32(7), /* start */ + cpu_to_be32(0xf8), /* count */ + }; + + /* Thread Interrupt Management Area : User (ring 3) and OS (ring 2) */ + timas[0] =3D cpu_to_be64(xive->tm_base + + XIVE_TM_USER_PAGE * (1ull << TM_SHIFT)); + timas[1] =3D cpu_to_be64(1ull << TM_SHIFT); + timas[2] =3D cpu_to_be64(xive->tm_base + + XIVE_TM_OS_PAGE * (1ull << TM_SHIFT)); + timas[3] =3D cpu_to_be64(1ull << TM_SHIFT); + + _FDT(node =3D fdt_add_subnode(fdt, 0, xive->nodename)); + + _FDT(fdt_setprop_string(fdt, node, "device_type", "power-ivpe")); + _FDT(fdt_setprop(fdt, node, "reg", timas, sizeof(timas))); + + _FDT(fdt_setprop_string(fdt, node, "compatible", "ibm,power-ivpe")); + _FDT(fdt_setprop(fdt, node, "ibm,xive-eq-sizes", eq_sizes, + sizeof(eq_sizes))); + _FDT(fdt_setprop(fdt, node, "ibm,xive-lisn-ranges", lisn_ranges, + sizeof(lisn_ranges))); + + /* For Linux to link the LSIs to the interrupt controller. */ + _FDT(fdt_setprop(fdt, node, "interrupt-controller", NULL, 0)); + _FDT(fdt_setprop_cell(fdt, node, "#interrupt-cells", 2)); + + /* For SLOF */ + _FDT(fdt_setprop_cell(fdt, node, "linux,phandle", phandle)); + _FDT(fdt_setprop_cell(fdt, node, "phandle", phandle)); + + /* + * The "ibm,plat-res-int-priorities" property defines the priority + * ranges reserved by the hypervisor + */ + _FDT(fdt_setprop(fdt, 0, "ibm,plat-res-int-priorities", + plat_res_int_priorities, sizeof(plat_res_int_prioriti= es))); +} + static void spapr_xive_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -601,6 +663,7 @@ static void spapr_xive_class_init(ObjectClass *klass, v= oid *data) sicc->free_irq =3D spapr_xive_free_irq; sicc->set_irq =3D spapr_xive_set_irq; sicc->print_info =3D spapr_xive_print_info; + sicc->dt =3D spapr_xive_dt; } =20 static const TypeInfo spapr_xive_info =3D { @@ -1601,65 +1664,3 @@ void spapr_xive_hcall_init(SpaprMachineState *spapr) spapr_register_hypercall(H_INT_SYNC, h_int_sync); spapr_register_hypercall(H_INT_RESET, h_int_reset); } - -void spapr_dt_xive(SpaprMachineState *spapr, uint32_t nr_servers, void *fd= t, - uint32_t phandle) -{ - SpaprXive *xive =3D spapr->xive; - int node; - uint64_t timas[2 * 2]; - /* Interrupt number ranges for the IPIs */ - uint32_t lisn_ranges[] =3D { - cpu_to_be32(0), - cpu_to_be32(nr_servers), - }; - /* - * EQ size - the sizes of pages supported by the system 4K, 64K, - * 2M, 16M. We only advertise 64K for the moment. - */ - uint32_t eq_sizes[] =3D { - cpu_to_be32(16), /* 64K */ - }; - /* - * The following array is in sync with the reserved priorities - * defined by the 'spapr_xive_priority_is_reserved' routine. - */ - uint32_t plat_res_int_priorities[] =3D { - cpu_to_be32(7), /* start */ - cpu_to_be32(0xf8), /* count */ - }; - - /* Thread Interrupt Management Area : User (ring 3) and OS (ring 2) */ - timas[0] =3D cpu_to_be64(xive->tm_base + - XIVE_TM_USER_PAGE * (1ull << TM_SHIFT)); - timas[1] =3D cpu_to_be64(1ull << TM_SHIFT); - timas[2] =3D cpu_to_be64(xive->tm_base + - XIVE_TM_OS_PAGE * (1ull << TM_SHIFT)); - timas[3] =3D cpu_to_be64(1ull << TM_SHIFT); - - _FDT(node =3D fdt_add_subnode(fdt, 0, xive->nodename)); - - _FDT(fdt_setprop_string(fdt, node, "device_type", "power-ivpe")); - _FDT(fdt_setprop(fdt, node, "reg", timas, sizeof(timas))); - - _FDT(fdt_setprop_string(fdt, node, "compatible", "ibm,power-ivpe")); - _FDT(fdt_setprop(fdt, node, "ibm,xive-eq-sizes", eq_sizes, - sizeof(eq_sizes))); - _FDT(fdt_setprop(fdt, node, "ibm,xive-lisn-ranges", lisn_ranges, - sizeof(lisn_ranges))); - - /* For Linux to link the LSIs to the interrupt controller. */ - _FDT(fdt_setprop(fdt, node, "interrupt-controller", NULL, 0)); - _FDT(fdt_setprop_cell(fdt, node, "#interrupt-cells", 2)); - - /* For SLOF */ - _FDT(fdt_setprop_cell(fdt, node, "linux,phandle", phandle)); - _FDT(fdt_setprop_cell(fdt, node, "phandle", phandle)); - - /* - * The "ibm,plat-res-int-priorities" property defines the priority - * ranges reserved by the hypervisor - */ - _FDT(fdt_setprop(fdt, 0, "ibm,plat-res-int-priorities", - plat_res_int_priorities, sizeof(plat_res_int_prioriti= es))); -} diff --git a/hw/intc/xics_spapr.c b/hw/intc/xics_spapr.c index 415defe394..4eabafc7e1 100644 --- a/hw/intc/xics_spapr.c +++ b/hw/intc/xics_spapr.c @@ -308,8 +308,8 @@ static void ics_spapr_realize(DeviceState *dev, Error *= *errp) spapr_register_hypercall(H_IPOLL, h_ipoll); } =20 -void spapr_dt_xics(SpaprMachineState *spapr, uint32_t nr_servers, void *fd= t, - uint32_t phandle) +static void xics_spapr_dt(SpaprInterruptController *intc, uint32_t nr_serv= ers, + void *fdt, uint32_t phandle) { uint32_t interrupt_server_ranges_prop[] =3D { 0, cpu_to_be32(nr_servers), @@ -408,6 +408,7 @@ static void ics_spapr_class_init(ObjectClass *klass, vo= id *data) sicc->free_irq =3D xics_spapr_free_irq; sicc->set_irq =3D xics_spapr_set_irq; sicc->print_info =3D xics_spapr_print_info; + sicc->dt =3D xics_spapr_dt; } =20 static const TypeInfo ics_spapr_info =3D { diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 6c38de5927..e880db5d38 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -1255,8 +1255,7 @@ static void *spapr_build_fdt(SpaprMachineState *spapr) _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); =20 /* /interrupt controller */ - spapr->irq->dt_populate(spapr, spapr_max_server_number(spapr), fdt, - PHANDLE_INTC); + spapr_irq_dt(spapr, spapr_max_server_number(spapr), fdt, PHANDLE_INTC); =20 ret =3D spapr_populate_memory(spapr, fdt); if (ret < 0) { diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c index a29b527232..a8005072e6 100644 --- a/hw/ppc/spapr_irq.c +++ b/hw/ppc/spapr_irq.c @@ -134,7 +134,6 @@ SpaprIrq spapr_irq_xics =3D { .xics =3D true, .xive =3D false, =20 - .dt_populate =3D spapr_dt_xics, .post_load =3D spapr_irq_post_load_xics, .reset =3D spapr_irq_reset_xics, .init_kvm =3D spapr_irq_init_kvm_xics, @@ -184,7 +183,6 @@ SpaprIrq spapr_irq_xive =3D { .xics =3D false, .xive =3D true, =20 - .dt_populate =3D spapr_dt_xive, .post_load =3D spapr_irq_post_load_xive, .reset =3D spapr_irq_reset_xive, .init_kvm =3D spapr_irq_init_kvm_xive, @@ -209,13 +207,6 @@ static SpaprIrq *spapr_irq_current(SpaprMachineState *= spapr) &spapr_irq_xive : &spapr_irq_xics; } =20 -static void spapr_irq_dt_populate_dual(SpaprMachineState *spapr, - uint32_t nr_servers, void *fdt, - uint32_t phandle) -{ - spapr_irq_current(spapr)->dt_populate(spapr, nr_servers, fdt, phandle); -} - static int spapr_irq_post_load_dual(SpaprMachineState *spapr, int version_= id) { /* @@ -270,7 +261,6 @@ SpaprIrq spapr_irq_dual =3D { .xics =3D true, .xive =3D true, =20 - .dt_populate =3D spapr_irq_dt_populate_dual, .post_load =3D spapr_irq_post_load_dual, .reset =3D spapr_irq_reset_dual, .init_kvm =3D NULL, /* should not be used */ @@ -377,6 +367,15 @@ void spapr_irq_print_info(SpaprMachineState *spapr, Mo= nitor *mon) sicc->print_info(spapr->active_intc, mon); } =20 +void spapr_irq_dt(SpaprMachineState *spapr, uint32_t nr_servers, + void *fdt, uint32_t phandle) +{ + SpaprInterruptControllerClass *sicc + =3D SPAPR_INTC_GET_CLASS(spapr->active_intc); + + sicc->dt(spapr->active_intc, nr_servers, fdt, phandle); +} + void spapr_irq_init(SpaprMachineState *spapr, Error **errp) { MachineState *machine =3D MACHINE(spapr); @@ -686,7 +685,6 @@ SpaprIrq spapr_irq_xics_legacy =3D { .xics =3D true, .xive =3D false, =20 - .dt_populate =3D spapr_dt_xics, .post_load =3D spapr_irq_post_load_xics, .reset =3D spapr_irq_reset_xics, .init_kvm =3D spapr_irq_init_kvm_xics, diff --git a/include/hw/ppc/spapr_irq.h b/include/hw/ppc/spapr_irq.h index bdfeb3b107..0df95e1b5a 100644 --- a/include/hw/ppc/spapr_irq.h +++ b/include/hw/ppc/spapr_irq.h @@ -60,6 +60,8 @@ typedef struct SpaprInterruptControllerClass { /* These methods should only be called on the active intc */ void (*set_irq)(SpaprInterruptController *intc, int irq, int val); void (*print_info)(SpaprInterruptController *intc, Monitor *mon); + void (*dt)(SpaprInterruptController *intc, uint32_t nr_servers, + void *fdt, uint32_t phandle); } SpaprInterruptControllerClass; =20 void spapr_irq_update_active_intc(SpaprMachineState *spapr); @@ -67,6 +69,8 @@ void spapr_irq_update_active_intc(SpaprMachineState *spap= r); int spapr_irq_cpu_intc_create(SpaprMachineState *spapr, PowerPCCPU *cpu, Error **errp); void spapr_irq_print_info(SpaprMachineState *spapr, Monitor *mon); +void spapr_irq_dt(SpaprMachineState *spapr, uint32_t nr_servers, + void *fdt, uint32_t phandle); =20 void spapr_irq_msi_init(SpaprMachineState *spapr, uint32_t nr_msis); int spapr_irq_msi_alloc(SpaprMachineState *spapr, uint32_t num, bool align, @@ -79,8 +83,6 @@ typedef struct SpaprIrq { bool xics; bool xive; =20 - void (*dt_populate)(SpaprMachineState *spapr, uint32_t nr_servers, - void *fdt, uint32_t phandle); int (*post_load)(SpaprMachineState *spapr, int version_id); void (*reset)(SpaprMachineState *spapr, Error **errp); void (*init_kvm)(SpaprMachineState *spapr, Error **errp); diff --git a/include/hw/ppc/spapr_xive.h b/include/hw/ppc/spapr_xive.h index 8f875673f5..ebe156eb30 100644 --- a/include/hw/ppc/spapr_xive.h +++ b/include/hw/ppc/spapr_xive.h @@ -58,8 +58,6 @@ void spapr_xive_pic_print_info(SpaprXive *xive, Monitor *= mon); int spapr_xive_post_load(SpaprXive *xive, int version_id); =20 void spapr_xive_hcall_init(SpaprMachineState *spapr); -void spapr_dt_xive(SpaprMachineState *spapr, uint32_t nr_servers, void *fd= t, - uint32_t phandle); void spapr_xive_set_tctx_os_cam(XiveTCTX *tctx); void spapr_xive_mmio_set_enabled(SpaprXive *xive, bool enable); void spapr_xive_map_mmio(SpaprXive *xive); diff --git a/include/hw/ppc/xics_spapr.h b/include/hw/ppc/xics_spapr.h index 0b35e85c26..8e4fb6adce 100644 --- a/include/hw/ppc/xics_spapr.h +++ b/include/hw/ppc/xics_spapr.h @@ -32,8 +32,6 @@ #define TYPE_ICS_SPAPR "ics-spapr" #define ICS_SPAPR(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS_SPAPR) =20 -void spapr_dt_xics(SpaprMachineState *spapr, uint32_t nr_servers, void *fd= t, - uint32_t phandle); int xics_kvm_connect(SpaprMachineState *spapr, Error **errp); void xics_kvm_disconnect(SpaprMachineState *spapr, Error **errp); bool xics_kvm_has_broken_disconnect(SpaprMachineState *spapr); --=20 2.21.0 From nobody Sat Apr 27 01:55:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Wed, 09 Oct 2019 02:08:32 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 46p3gF0llQz9sR3; Wed, 9 Oct 2019 17:08:25 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1570601305; bh=14lr9JEGz77/t8EG1ZaezP7gMjFaSymG2CgVirQ0kyg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ciTqY4tGEu4CTAWRkuQI9NWB5o/pVMUPlvz/S+Y9gmgrcg8cSjAHbyfuAoCmTvZoN jejeN0Ks6iQ7ausXDxloH3kzTcaUHtaes52ZbKnsPspSbh+Ya/y2XWJn58XFAnFats OckVhiGQFGJx5Wj0R0vZNEbJRbNHtdpqyCsWeHXk= From: David Gibson To: qemu-devel@nongnu.org, clg@kaod.org, qemu-ppc@nongnu.org Subject: [PATCH v4 11/19] spapr, xics, xive: Match signatures for XICS and XIVE KVM connect routines Date: Wed, 9 Oct 2019 17:08:10 +1100 Message-Id: <20191009060818.29719-12-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191009060818.29719-1-david@gibson.dropbear.id.au> References: <20191009060818.29719-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jason Wang , Riku Voipio , groug@kaod.org, Laurent Vivier , Paolo Bonzini , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , philmd@redhat.com, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Both XICS and XIVE have routines to connect and disconnect KVM with similar but not identical signatures. This adjusts them to match exactly, which will be useful for further cleanups later. While we're there, we add an explicit return value to the connect path to streamline error reporting in the callers. We remove error reporting the disconnect path. In the XICS case this wasn't used at all. In the XIVE case the only error case was if the KVM device was set up, but KVM didn't have the capability to do so which is pretty obviously impossible. Signed-off-by: David Gibson Reviewed-by: Greg Kurz Reviewed-by: C=C3=A9dric Le Goater --- hw/intc/spapr_xive_kvm.c | 22 ++++++++++------------ hw/intc/xics_kvm.c | 9 +++++---- hw/ppc/spapr_irq.c | 22 +++++----------------- include/hw/ppc/spapr_xive.h | 4 ++-- include/hw/ppc/xics_spapr.h | 4 ++-- 5 files changed, 24 insertions(+), 37 deletions(-) diff --git a/hw/intc/spapr_xive_kvm.c b/hw/intc/spapr_xive_kvm.c index 51b334b676..08012ac7cd 100644 --- a/hw/intc/spapr_xive_kvm.c +++ b/hw/intc/spapr_xive_kvm.c @@ -740,8 +740,9 @@ static void *kvmppc_xive_mmap(SpaprXive *xive, int pgof= f, size_t len, * All the XIVE memory regions are now backed by mappings from the KVM * XIVE device. */ -void kvmppc_xive_connect(SpaprXive *xive, Error **errp) +int kvmppc_xive_connect(SpaprInterruptController *intc, Error **errp) { + SpaprXive *xive =3D SPAPR_XIVE(intc); XiveSource *xsrc =3D &xive->source; Error *local_err =3D NULL; size_t esb_len =3D (1ull << xsrc->esb_shift) * xsrc->nr_irqs; @@ -753,19 +754,19 @@ void kvmppc_xive_connect(SpaprXive *xive, Error **err= p) * rebooting under the XIVE-only interrupt mode. */ if (xive->fd !=3D -1) { - return; + return 0; } =20 if (!kvmppc_has_cap_xive()) { error_setg(errp, "IRQ_XIVE capability must be present for KVM"); - return; + return -1; } =20 /* First, create the KVM XIVE device */ xive->fd =3D kvm_create_device(kvm_state, KVM_DEV_TYPE_XIVE, false); if (xive->fd < 0) { error_setg_errno(errp, -xive->fd, "XIVE: error creating KVM device= "); - return; + return -1; } =20 /* @@ -821,15 +822,17 @@ void kvmppc_xive_connect(SpaprXive *xive, Error **err= p) kvm_kernel_irqchip =3D true; kvm_msi_via_irqfd_allowed =3D true; kvm_gsi_direct_mapping =3D true; - return; + return 0; =20 fail: error_propagate(errp, local_err); - kvmppc_xive_disconnect(xive, NULL); + kvmppc_xive_disconnect(intc); + return -1; } =20 -void kvmppc_xive_disconnect(SpaprXive *xive, Error **errp) +void kvmppc_xive_disconnect(SpaprInterruptController *intc) { + SpaprXive *xive =3D SPAPR_XIVE(intc); XiveSource *xsrc; size_t esb_len; =20 @@ -838,11 +841,6 @@ void kvmppc_xive_disconnect(SpaprXive *xive, Error **e= rrp) return; } =20 - if (!kvmppc_has_cap_xive()) { - error_setg(errp, "IRQ_XIVE capability must be present for KVM"); - return; - } - /* Clear the KVM mapping */ xsrc =3D &xive->source; esb_len =3D (1ull << xsrc->esb_shift) * xsrc->nr_irqs; diff --git a/hw/intc/xics_kvm.c b/hw/intc/xics_kvm.c index ba90d6dc96..954c424b36 100644 --- a/hw/intc/xics_kvm.c +++ b/hw/intc/xics_kvm.c @@ -342,8 +342,9 @@ void ics_kvm_set_irq(ICSState *ics, int srcno, int val) } } =20 -int xics_kvm_connect(SpaprMachineState *spapr, Error **errp) +int xics_kvm_connect(SpaprInterruptController *intc, Error **errp) { + ICSState *ics =3D ICS_SPAPR(intc); int rc; CPUState *cs; Error *local_err =3D NULL; @@ -413,7 +414,7 @@ int xics_kvm_connect(SpaprMachineState *spapr, Error **= errp) } =20 /* Update the KVM sources */ - ics_set_kvm_state(spapr->ics, &local_err); + ics_set_kvm_state(ics, &local_err); if (local_err) { goto fail; } @@ -431,11 +432,11 @@ int xics_kvm_connect(SpaprMachineState *spapr, Error = **errp) =20 fail: error_propagate(errp, local_err); - xics_kvm_disconnect(spapr, NULL); + xics_kvm_disconnect(intc); return -1; } =20 -void xics_kvm_disconnect(SpaprMachineState *spapr, Error **errp) +void xics_kvm_disconnect(SpaprInterruptController *intc) { /* * Only on P9 using the XICS-on XIVE KVM device: diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c index a8005072e6..5c8ffb27da 100644 --- a/hw/ppc/spapr_irq.c +++ b/hw/ppc/spapr_irq.c @@ -124,7 +124,7 @@ static void spapr_irq_reset_xics(SpaprMachineState *spa= pr, Error **errp) static void spapr_irq_init_kvm_xics(SpaprMachineState *spapr, Error **errp) { if (kvm_enabled()) { - xics_kvm_connect(spapr, errp); + xics_kvm_connect(SPAPR_INTC(spapr->ics), errp); } } =20 @@ -173,7 +173,7 @@ static void spapr_irq_reset_xive(SpaprMachineState *spa= pr, Error **errp) static void spapr_irq_init_kvm_xive(SpaprMachineState *spapr, Error **errp) { if (kvm_enabled()) { - kvmppc_xive_connect(spapr->xive, errp); + kvmppc_xive_connect(SPAPR_INTC(spapr->xive), errp); } } =20 @@ -215,7 +215,7 @@ static int spapr_irq_post_load_dual(SpaprMachineState *= spapr, int version_id) */ if (spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { if (kvm_irqchip_in_kernel()) { - xics_kvm_disconnect(spapr, &error_fatal); + xics_kvm_disconnect(SPAPR_INTC(spapr->ics)); } spapr_irq_xive.reset(spapr, &error_fatal); } @@ -225,8 +225,6 @@ static int spapr_irq_post_load_dual(SpaprMachineState *= spapr, int version_id) =20 static void spapr_irq_reset_dual(SpaprMachineState *spapr, Error **errp) { - Error *local_err =3D NULL; - /* * Deactivate the XIVE MMIOs. The XIVE backend will reenable them * if selected. @@ -235,18 +233,8 @@ static void spapr_irq_reset_dual(SpaprMachineState *sp= apr, Error **errp) =20 /* Destroy all KVM devices */ if (kvm_irqchip_in_kernel()) { - xics_kvm_disconnect(spapr, &local_err); - if (local_err) { - error_propagate(errp, local_err); - error_prepend(errp, "KVM XICS disconnect failed: "); - return; - } - kvmppc_xive_disconnect(spapr->xive, &local_err); - if (local_err) { - error_propagate(errp, local_err); - error_prepend(errp, "KVM XIVE disconnect failed: "); - return; - } + xics_kvm_disconnect(SPAPR_INTC(spapr->ics)); + kvmppc_xive_disconnect(SPAPR_INTC(spapr->xive)); } =20 spapr_irq_current(spapr)->reset(spapr, errp); diff --git a/include/hw/ppc/spapr_xive.h b/include/hw/ppc/spapr_xive.h index ebe156eb30..64972754f9 100644 --- a/include/hw/ppc/spapr_xive.h +++ b/include/hw/ppc/spapr_xive.h @@ -68,8 +68,8 @@ int spapr_xive_end_to_target(uint8_t end_blk, uint32_t en= d_idx, /* * KVM XIVE device helpers */ -void kvmppc_xive_connect(SpaprXive *xive, Error **errp); -void kvmppc_xive_disconnect(SpaprXive *xive, Error **errp); +int kvmppc_xive_connect(SpaprInterruptController *intc, Error **errp); +void kvmppc_xive_disconnect(SpaprInterruptController *intc); void kvmppc_xive_reset(SpaprXive *xive, Error **errp); void kvmppc_xive_set_source_config(SpaprXive *xive, uint32_t lisn, XiveEAS= *eas, Error **errp); diff --git a/include/hw/ppc/xics_spapr.h b/include/hw/ppc/xics_spapr.h index 8e4fb6adce..28b87038c8 100644 --- a/include/hw/ppc/xics_spapr.h +++ b/include/hw/ppc/xics_spapr.h @@ -32,8 +32,8 @@ #define TYPE_ICS_SPAPR "ics-spapr" #define ICS_SPAPR(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS_SPAPR) =20 -int xics_kvm_connect(SpaprMachineState *spapr, Error **errp); -void xics_kvm_disconnect(SpaprMachineState *spapr, Error **errp); +int xics_kvm_connect(SpaprInterruptController *intc, Error **errp); +void xics_kvm_disconnect(SpaprInterruptController *intc); bool xics_kvm_has_broken_disconnect(SpaprMachineState *spapr); =20 #endif /* XICS_SPAPR_H */ --=20 2.21.0 From nobody Sat Apr 27 01:55:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Wed, 09 Oct 2019 02:08:32 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 46p3gF3Ldhz9sRD; Wed, 9 Oct 2019 17:08:25 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1570601305; bh=LIu/9orQqM+uHUGN1XbfnZlinvHNg01lhAvD+xkXWok=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WvMPddUhlSAGqXfCoAxejyT1/gO2uhamE5C/gwGSHNcVQay0WgI8uBOb8zOp42cwH bCKSd8WUNNVCS7I+uW1gBpARaeLlNkrmntmjCrN535NA/SbuSeou0HdbMHkgYBODNq 1POxuFDa1nRLwcSP163dn5v/uNgHQA+bholBOHrw= From: David Gibson To: qemu-devel@nongnu.org, clg@kaod.org, qemu-ppc@nongnu.org Subject: [PATCH v4 12/19] spapr: Remove SpaprIrq::init_kvm hook Date: Wed, 9 Oct 2019 17:08:11 +1100 Message-Id: <20191009060818.29719-13-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191009060818.29719-1-david@gibson.dropbear.id.au> References: <20191009060818.29719-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jason Wang , Riku Voipio , groug@kaod.org, Laurent Vivier , Paolo Bonzini , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , philmd@redhat.com, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" This hook is a bit odd. The only caller is spapr_irq_init_kvm(), but it explicitly takes an SpaprIrq *, so it's never really called through the current SpaprIrq. Essentially this is just a way of passing through a function pointer so that spapr_irq_init_kvm() can handle some configuration and error handling logic without duplicating it between the xics and xive reset paths. So, make it just take that function pointer. Because of earlier reworks to the KVM connect/disconnect code in the xics and xive backends we can also eliminate some wrapper functions and streamline error handling a bit. Signed-off-by: David Gibson Reviewed-by: Greg Kurz Reviewed-by: C=C3=A9dric Le Goater --- hw/ppc/spapr_irq.c | 74 +++++++++++++------------------------- include/hw/ppc/spapr_irq.h | 1 - 2 files changed, 25 insertions(+), 50 deletions(-) diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c index 5c8ffb27da..7cd18e5b15 100644 --- a/hw/ppc/spapr_irq.c +++ b/hw/ppc/spapr_irq.c @@ -65,33 +65,35 @@ void spapr_irq_msi_free(SpaprMachineState *spapr, int i= rq, uint32_t num) bitmap_clear(spapr->irq_map, irq - SPAPR_IRQ_MSI, num); } =20 -static void spapr_irq_init_kvm(SpaprMachineState *spapr, - SpaprIrq *irq, Error **errp) +static int spapr_irq_init_kvm(int (*fn)(SpaprInterruptController *, Error = **), + SpaprInterruptController *intc, + Error **errp) { - MachineState *machine =3D MACHINE(spapr); + MachineState *machine =3D MACHINE(qdev_get_machine()); Error *local_err =3D NULL; =20 if (kvm_enabled() && machine_kernel_irqchip_allowed(machine)) { - irq->init_kvm(spapr, &local_err); - if (local_err && machine_kernel_irqchip_required(machine)) { - error_prepend(&local_err, - "kernel_irqchip requested but unavailable: "); - error_propagate(errp, local_err); - return; - } + if (fn(intc, &local_err) < 0) { + if (machine_kernel_irqchip_required(machine)) { + error_prepend(&local_err, + "kernel_irqchip requested but unavailable: "= ); + error_propagate(errp, local_err); + return -1; + } =20 - if (!local_err) { - return; + /* + * We failed to initialize the KVM device, fallback to + * emulated mode + */ + error_prepend(&local_err, + "kernel_irqchip allowed but unavailable: "); + error_append_hint(&local_err, + "Falling back to kernel-irqchip=3Doff\n"); + warn_report_err(local_err); } - - /* - * We failed to initialize the KVM device, fallback to - * emulated mode - */ - error_prepend(&local_err, "kernel_irqchip allowed but unavailable:= "); - error_append_hint(&local_err, "Falling back to kernel-irqchip=3Dof= f\n"); - warn_report_err(local_err); } + + return 0; } =20 /* @@ -112,20 +114,7 @@ static int spapr_irq_post_load_xics(SpaprMachineState = *spapr, int version_id) =20 static void spapr_irq_reset_xics(SpaprMachineState *spapr, Error **errp) { - Error *local_err =3D NULL; - - spapr_irq_init_kvm(spapr, &spapr_irq_xics, &local_err); - if (local_err) { - error_propagate(errp, local_err); - return; - } -} - -static void spapr_irq_init_kvm_xics(SpaprMachineState *spapr, Error **errp) -{ - if (kvm_enabled()) { - xics_kvm_connect(SPAPR_INTC(spapr->ics), errp); - } + spapr_irq_init_kvm(xics_kvm_connect, SPAPR_INTC(spapr->ics), errp); } =20 SpaprIrq spapr_irq_xics =3D { @@ -136,7 +125,6 @@ SpaprIrq spapr_irq_xics =3D { =20 .post_load =3D spapr_irq_post_load_xics, .reset =3D spapr_irq_reset_xics, - .init_kvm =3D spapr_irq_init_kvm_xics, }; =20 /* @@ -151,7 +139,6 @@ static int spapr_irq_post_load_xive(SpaprMachineState *= spapr, int version_id) static void spapr_irq_reset_xive(SpaprMachineState *spapr, Error **errp) { CPUState *cs; - Error *local_err =3D NULL; =20 CPU_FOREACH(cs) { PowerPCCPU *cpu =3D POWERPC_CPU(cs); @@ -160,9 +147,8 @@ static void spapr_irq_reset_xive(SpaprMachineState *spa= pr, Error **errp) spapr_xive_set_tctx_os_cam(spapr_cpu_state(cpu)->tctx); } =20 - spapr_irq_init_kvm(spapr, &spapr_irq_xive, &local_err); - if (local_err) { - error_propagate(errp, local_err); + if (spapr_irq_init_kvm(kvmppc_xive_connect, + SPAPR_INTC(spapr->xive), errp) < 0) { return; } =20 @@ -170,13 +156,6 @@ static void spapr_irq_reset_xive(SpaprMachineState *sp= apr, Error **errp) spapr_xive_mmio_set_enabled(spapr->xive, true); } =20 -static void spapr_irq_init_kvm_xive(SpaprMachineState *spapr, Error **errp) -{ - if (kvm_enabled()) { - kvmppc_xive_connect(SPAPR_INTC(spapr->xive), errp); - } -} - SpaprIrq spapr_irq_xive =3D { .nr_xirqs =3D SPAPR_NR_XIRQS, .nr_msis =3D SPAPR_NR_MSIS, @@ -185,7 +164,6 @@ SpaprIrq spapr_irq_xive =3D { =20 .post_load =3D spapr_irq_post_load_xive, .reset =3D spapr_irq_reset_xive, - .init_kvm =3D spapr_irq_init_kvm_xive, }; =20 /* @@ -251,7 +229,6 @@ SpaprIrq spapr_irq_dual =3D { =20 .post_load =3D spapr_irq_post_load_dual, .reset =3D spapr_irq_reset_dual, - .init_kvm =3D NULL, /* should not be used */ }; =20 =20 @@ -675,7 +652,6 @@ SpaprIrq spapr_irq_xics_legacy =3D { =20 .post_load =3D spapr_irq_post_load_xics, .reset =3D spapr_irq_reset_xics, - .init_kvm =3D spapr_irq_init_kvm_xics, }; =20 static void spapr_irq_register_types(void) diff --git a/include/hw/ppc/spapr_irq.h b/include/hw/ppc/spapr_irq.h index 0df95e1b5a..06179b271f 100644 --- a/include/hw/ppc/spapr_irq.h +++ b/include/hw/ppc/spapr_irq.h @@ -85,7 +85,6 @@ typedef struct SpaprIrq { =20 int (*post_load)(SpaprMachineState *spapr, int version_id); void (*reset)(SpaprMachineState *spapr, Error **errp); - void (*init_kvm)(SpaprMachineState *spapr, Error **errp); } SpaprIrq; =20 extern SpaprIrq spapr_irq_xics; --=20 2.21.0 From nobody Sat Apr 27 01:55:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; 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Wed, 9 Oct 2019 10:01:26 -0700 (PDT) Received: from localhost ([::1]:52674 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iIFL2-0002Li-9W for importer@patchew.org; Wed, 09 Oct 2019 13:01:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60386) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iI59c-0001bH-Jt for qemu-devel@nongnu.org; Wed, 09 Oct 2019 02:08:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iI59a-0006yX-PS for qemu-devel@nongnu.org; Wed, 09 Oct 2019 02:08:56 -0400 Received: from bilbo.ozlabs.org ([203.11.71.1]:44643 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iI59Z-0006Y3-DR; Wed, 09 Oct 2019 02:08:54 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 46p3gF4Z0gz9sR6; Wed, 9 Oct 2019 17:08:25 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1570601305; bh=2cuy/0jdokLLzeybNt8oIsyBe/xbthchGAjiFqfUByI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZGGONLsi6FsnBP6Yz0pznbwt4jXzp0+3pYWiUVeLOl37Fp9UsfAn3nUh6KejEp1O+ iE3W22vlYrN5QbGIv5HStCsvm5e3PhouXEN6oYc+6F2XpZk1DFNNDUuffTGL5PNUAL vU/p4aI4nD7gk7LKScgpG5zSyGiDnwkw0Z1GPnQ8= From: David Gibson To: qemu-devel@nongnu.org, clg@kaod.org, qemu-ppc@nongnu.org Subject: [PATCH v4 13/19] spapr, xics, xive: Move SpaprIrq::reset hook logic into activate/deactivate Date: Wed, 9 Oct 2019 17:08:12 +1100 Message-Id: <20191009060818.29719-14-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191009060818.29719-1-david@gibson.dropbear.id.au> References: <20191009060818.29719-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jason Wang , Riku Voipio , groug@kaod.org, Laurent Vivier , Paolo Bonzini , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , philmd@redhat.com, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" It turns out that all the logic in the SpaprIrq::reset hooks (and some in the SpaprIrq::post_load hooks) isn't really related to resetting the irq backend (that's handled by the backends' own reset routines). Rather its about getting the backend ready to be the active interrupt controller or stopping being the active interrupt controller - reset (and post_load) is just the only time that changes at present. To make this flow clearer, move the logic into the explicit backend activate and deactivate hooks. Signed-off-by: David Gibson Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Greg Kurz --- hw/intc/spapr_xive.c | 38 +++++++++++++++++++++ hw/intc/xics_spapr.c | 17 ++++++++++ hw/ppc/spapr_irq.c | 67 ++------------------------------------ include/hw/ppc/spapr_irq.h | 4 ++- 4 files changed, 61 insertions(+), 65 deletions(-) diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c index 37ffb74ca5..1811653aac 100644 --- a/hw/intc/spapr_xive.c +++ b/hw/intc/spapr_xive.c @@ -640,6 +640,42 @@ static void spapr_xive_dt(SpaprInterruptController *in= tc, uint32_t nr_servers, plat_res_int_priorities, sizeof(plat_res_int_prioriti= es))); } =20 +static int spapr_xive_activate(SpaprInterruptController *intc, Error **err= p) +{ + SpaprXive *xive =3D SPAPR_XIVE(intc); + CPUState *cs; + + CPU_FOREACH(cs) { + PowerPCCPU *cpu =3D POWERPC_CPU(cs); + + /* (TCG) Set the OS CAM line of the thread interrupt context. */ + spapr_xive_set_tctx_os_cam(spapr_cpu_state(cpu)->tctx); + } + + if (kvm_enabled()) { + int rc =3D spapr_irq_init_kvm(kvmppc_xive_connect, intc, errp); + if (rc < 0) { + return rc; + } + } + + /* Activate the XIVE MMIOs */ + spapr_xive_mmio_set_enabled(xive, true); + + return 0; +} + +static void spapr_xive_deactivate(SpaprInterruptController *intc) +{ + SpaprXive *xive =3D SPAPR_XIVE(intc); + + spapr_xive_mmio_set_enabled(xive, false); + + if (kvm_irqchip_in_kernel()) { + kvmppc_xive_disconnect(intc); + } +} + static void spapr_xive_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -658,6 +694,8 @@ static void spapr_xive_class_init(ObjectClass *klass, v= oid *data) xrc->write_nvt =3D spapr_xive_write_nvt; xrc->get_tctx =3D spapr_xive_get_tctx; =20 + sicc->activate =3D spapr_xive_activate; + sicc->deactivate =3D spapr_xive_deactivate; sicc->cpu_intc_create =3D spapr_xive_cpu_intc_create; sicc->claim_irq =3D spapr_xive_claim_irq; sicc->free_irq =3D spapr_xive_free_irq; diff --git a/hw/intc/xics_spapr.c b/hw/intc/xics_spapr.c index 4eabafc7e1..90b4d48877 100644 --- a/hw/intc/xics_spapr.c +++ b/hw/intc/xics_spapr.c @@ -395,6 +395,21 @@ static void xics_spapr_print_info(SpaprInterruptContro= ller *intc, Monitor *mon) ics_pic_print_info(ics, mon); } =20 +static int xics_spapr_activate(SpaprInterruptController *intc, Error **err= p) +{ + if (kvm_enabled()) { + return spapr_irq_init_kvm(xics_kvm_connect, intc, errp); + } + return 0; +} + +static void xics_spapr_deactivate(SpaprInterruptController *intc) +{ + if (kvm_irqchip_in_kernel()) { + xics_kvm_disconnect(intc); + } +} + static void ics_spapr_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -403,6 +418,8 @@ static void ics_spapr_class_init(ObjectClass *klass, vo= id *data) =20 device_class_set_parent_realize(dc, ics_spapr_realize, &isc->parent_realize); + sicc->activate =3D xics_spapr_activate; + sicc->deactivate =3D xics_spapr_deactivate; sicc->cpu_intc_create =3D xics_spapr_cpu_intc_create; sicc->claim_irq =3D xics_spapr_claim_irq; sicc->free_irq =3D xics_spapr_free_irq; diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c index 7cd18e5b15..f70b331f44 100644 --- a/hw/ppc/spapr_irq.c +++ b/hw/ppc/spapr_irq.c @@ -65,9 +65,9 @@ void spapr_irq_msi_free(SpaprMachineState *spapr, int irq= , uint32_t num) bitmap_clear(spapr->irq_map, irq - SPAPR_IRQ_MSI, num); } =20 -static int spapr_irq_init_kvm(int (*fn)(SpaprInterruptController *, Error = **), - SpaprInterruptController *intc, - Error **errp) +int spapr_irq_init_kvm(int (*fn)(SpaprInterruptController *, Error **), + SpaprInterruptController *intc, + Error **errp) { MachineState *machine =3D MACHINE(qdev_get_machine()); Error *local_err =3D NULL; @@ -112,11 +112,6 @@ static int spapr_irq_post_load_xics(SpaprMachineState = *spapr, int version_id) return 0; } =20 -static void spapr_irq_reset_xics(SpaprMachineState *spapr, Error **errp) -{ - spapr_irq_init_kvm(xics_kvm_connect, SPAPR_INTC(spapr->ics), errp); -} - SpaprIrq spapr_irq_xics =3D { .nr_xirqs =3D SPAPR_NR_XIRQS, .nr_msis =3D SPAPR_NR_MSIS, @@ -124,7 +119,6 @@ SpaprIrq spapr_irq_xics =3D { .xive =3D false, =20 .post_load =3D spapr_irq_post_load_xics, - .reset =3D spapr_irq_reset_xics, }; =20 /* @@ -136,26 +130,6 @@ static int spapr_irq_post_load_xive(SpaprMachineState = *spapr, int version_id) return spapr_xive_post_load(spapr->xive, version_id); } =20 -static void spapr_irq_reset_xive(SpaprMachineState *spapr, Error **errp) -{ - CPUState *cs; - - CPU_FOREACH(cs) { - PowerPCCPU *cpu =3D POWERPC_CPU(cs); - - /* (TCG) Set the OS CAM line of the thread interrupt context. */ - spapr_xive_set_tctx_os_cam(spapr_cpu_state(cpu)->tctx); - } - - if (spapr_irq_init_kvm(kvmppc_xive_connect, - SPAPR_INTC(spapr->xive), errp) < 0) { - return; - } - - /* Activate the XIVE MMIOs */ - spapr_xive_mmio_set_enabled(spapr->xive, true); -} - SpaprIrq spapr_irq_xive =3D { .nr_xirqs =3D SPAPR_NR_XIRQS, .nr_msis =3D SPAPR_NR_MSIS, @@ -163,7 +137,6 @@ SpaprIrq spapr_irq_xive =3D { .xive =3D true, =20 .post_load =3D spapr_irq_post_load_xive, - .reset =3D spapr_irq_reset_xive, }; =20 /* @@ -187,37 +160,9 @@ static SpaprIrq *spapr_irq_current(SpaprMachineState *= spapr) =20 static int spapr_irq_post_load_dual(SpaprMachineState *spapr, int version_= id) { - /* - * Force a reset of the XIVE backend after migration. The machine - * defaults to XICS at startup. - */ - if (spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { - if (kvm_irqchip_in_kernel()) { - xics_kvm_disconnect(SPAPR_INTC(spapr->ics)); - } - spapr_irq_xive.reset(spapr, &error_fatal); - } - return spapr_irq_current(spapr)->post_load(spapr, version_id); } =20 -static void spapr_irq_reset_dual(SpaprMachineState *spapr, Error **errp) -{ - /* - * Deactivate the XIVE MMIOs. The XIVE backend will reenable them - * if selected. - */ - spapr_xive_mmio_set_enabled(spapr->xive, false); - - /* Destroy all KVM devices */ - if (kvm_irqchip_in_kernel()) { - xics_kvm_disconnect(SPAPR_INTC(spapr->ics)); - kvmppc_xive_disconnect(SPAPR_INTC(spapr->xive)); - } - - spapr_irq_current(spapr)->reset(spapr, errp); -} - /* * Define values in sync with the XIVE and XICS backend */ @@ -228,7 +173,6 @@ SpaprIrq spapr_irq_dual =3D { .xive =3D true, =20 .post_load =3D spapr_irq_post_load_dual, - .reset =3D spapr_irq_reset_dual, }; =20 =20 @@ -512,10 +456,6 @@ void spapr_irq_reset(SpaprMachineState *spapr, Error *= *errp) assert(!spapr->irq_map || bitmap_empty(spapr->irq_map, spapr->irq_map_= nr)); =20 spapr_irq_update_active_intc(spapr); - - if (spapr->irq->reset) { - spapr->irq->reset(spapr, errp); - } } =20 int spapr_irq_get_phandle(SpaprMachineState *spapr, void *fdt, Error **err= p) @@ -651,7 +591,6 @@ SpaprIrq spapr_irq_xics_legacy =3D { .xive =3D false, =20 .post_load =3D spapr_irq_post_load_xics, - .reset =3D spapr_irq_reset_xics, }; =20 static void spapr_irq_register_types(void) diff --git a/include/hw/ppc/spapr_irq.h b/include/hw/ppc/spapr_irq.h index 06179b271f..e02e44624b 100644 --- a/include/hw/ppc/spapr_irq.h +++ b/include/hw/ppc/spapr_irq.h @@ -84,7 +84,6 @@ typedef struct SpaprIrq { bool xive; =20 int (*post_load)(SpaprMachineState *spapr, int version_id); - void (*reset)(SpaprMachineState *spapr, Error **errp); } SpaprIrq; =20 extern SpaprIrq spapr_irq_xics; @@ -99,6 +98,9 @@ qemu_irq spapr_qirq(SpaprMachineState *spapr, int irq); int spapr_irq_post_load(SpaprMachineState *spapr, int version_id); void spapr_irq_reset(SpaprMachineState *spapr, Error **errp); int spapr_irq_get_phandle(SpaprMachineState *spapr, void *fdt, Error **err= p); +int spapr_irq_init_kvm(int (*fn)(SpaprInterruptController *, Error **), + SpaprInterruptController *intc, + Error **errp); =20 /* * XICS legacy routines --=20 2.21.0 From nobody Sat Apr 27 01:55:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Wed, 09 Oct 2019 02:08:33 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 46p3gF58dvz9sRQ; Wed, 9 Oct 2019 17:08:25 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1570601305; bh=u+VNZMRj35Tr3YeqImASDIDQ2XKgQjzroD98TrDkA9w=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Op2PDBP8ZXZIGH+3sEj6PZxjrIhRimlmo8KcAt2eEzIJIvP5hlW3a9RB78QAwfI5i 8IfEEVB+oo/Q/HxNQd09j7wbkFFMTdJCp96xIYqFG3X36UXFvcDSQp9I8n8dac+Qjn 0w21Dh8sfekMv4DXhg+JpSP0U8D/W7kVneOkz8Ek= From: David Gibson To: qemu-devel@nongnu.org, clg@kaod.org, qemu-ppc@nongnu.org Subject: [PATCH v4 14/19] spapr, xics, xive: Move SpaprIrq::post_load hook to backends Date: Wed, 9 Oct 2019 17:08:13 +1100 Message-Id: <20191009060818.29719-15-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191009060818.29719-1-david@gibson.dropbear.id.au> References: <20191009060818.29719-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jason Wang , Riku Voipio , groug@kaod.org, Laurent Vivier , Paolo Bonzini , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , philmd@redhat.com, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The remaining logic in the post_load hook really belongs to the interrupt controller backends, and just needs to be called on the active controller (after the active controller is set to the right thing based on the incoming migration in the generic spapr_irq_post_load() logic). Signed-off-by: David Gibson Reviewed-by: Greg Kurz Reviewed-by: C=C3=A9dric Le Goater --- hw/intc/spapr_xive.c | 5 +++-- hw/intc/xics_spapr.c | 13 +++++++++++ hw/ppc/spapr_irq.c | 45 ++++--------------------------------- include/hw/ppc/spapr_irq.h | 3 +-- include/hw/ppc/spapr_xive.h | 1 - 5 files changed, 21 insertions(+), 46 deletions(-) diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c index 1811653aac..ba32d2cc5b 100644 --- a/hw/intc/spapr_xive.c +++ b/hw/intc/spapr_xive.c @@ -462,10 +462,10 @@ static int vmstate_spapr_xive_pre_save(void *opaque) * Called by the sPAPR IRQ backend 'post_load' method at the machine * level. */ -int spapr_xive_post_load(SpaprXive *xive, int version_id) +static int spapr_xive_post_load(SpaprInterruptController *intc, int versio= n_id) { if (kvm_irqchip_in_kernel()) { - return kvmppc_xive_post_load(xive, version_id); + return kvmppc_xive_post_load(SPAPR_XIVE(intc), version_id); } =20 return 0; @@ -702,6 +702,7 @@ static void spapr_xive_class_init(ObjectClass *klass, v= oid *data) sicc->set_irq =3D spapr_xive_set_irq; sicc->print_info =3D spapr_xive_print_info; sicc->dt =3D spapr_xive_dt; + sicc->post_load =3D spapr_xive_post_load; } =20 static const TypeInfo spapr_xive_info =3D { diff --git a/hw/intc/xics_spapr.c b/hw/intc/xics_spapr.c index 90b4d48877..4f64b9a9fc 100644 --- a/hw/intc/xics_spapr.c +++ b/hw/intc/xics_spapr.c @@ -395,6 +395,18 @@ static void xics_spapr_print_info(SpaprInterruptContro= ller *intc, Monitor *mon) ics_pic_print_info(ics, mon); } =20 +static int xics_spapr_post_load(SpaprInterruptController *intc, int versio= n_id) +{ + if (!kvm_irqchip_in_kernel()) { + CPUState *cs; + CPU_FOREACH(cs) { + PowerPCCPU *cpu =3D POWERPC_CPU(cs); + icp_resend(spapr_cpu_state(cpu)->icp); + } + } + return 0; +} + static int xics_spapr_activate(SpaprInterruptController *intc, Error **err= p) { if (kvm_enabled()) { @@ -426,6 +438,7 @@ static void ics_spapr_class_init(ObjectClass *klass, vo= id *data) sicc->set_irq =3D xics_spapr_set_irq; sicc->print_info =3D xics_spapr_print_info; sicc->dt =3D xics_spapr_dt; + sicc->post_load =3D xics_spapr_post_load; } =20 static const TypeInfo ics_spapr_info =3D { diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c index f70b331f44..f3d18b1dad 100644 --- a/hw/ppc/spapr_irq.c +++ b/hw/ppc/spapr_irq.c @@ -100,43 +100,22 @@ int spapr_irq_init_kvm(int (*fn)(SpaprInterruptContro= ller *, Error **), * XICS IRQ backend. */ =20 -static int spapr_irq_post_load_xics(SpaprMachineState *spapr, int version_= id) -{ - if (!kvm_irqchip_in_kernel()) { - CPUState *cs; - CPU_FOREACH(cs) { - PowerPCCPU *cpu =3D POWERPC_CPU(cs); - icp_resend(spapr_cpu_state(cpu)->icp); - } - } - return 0; -} - SpaprIrq spapr_irq_xics =3D { .nr_xirqs =3D SPAPR_NR_XIRQS, .nr_msis =3D SPAPR_NR_MSIS, .xics =3D true, .xive =3D false, - - .post_load =3D spapr_irq_post_load_xics, }; =20 /* * XIVE IRQ backend. */ =20 -static int spapr_irq_post_load_xive(SpaprMachineState *spapr, int version_= id) -{ - return spapr_xive_post_load(spapr->xive, version_id); -} - SpaprIrq spapr_irq_xive =3D { .nr_xirqs =3D SPAPR_NR_XIRQS, .nr_msis =3D SPAPR_NR_MSIS, .xics =3D false, .xive =3D true, - - .post_load =3D spapr_irq_post_load_xive, }; =20 /* @@ -148,21 +127,6 @@ SpaprIrq spapr_irq_xive =3D { * activated after an extra machine reset. */ =20 -/* - * Returns the sPAPR IRQ backend negotiated by CAS. XICS is the - * default. - */ -static SpaprIrq *spapr_irq_current(SpaprMachineState *spapr) -{ - return spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT) ? - &spapr_irq_xive : &spapr_irq_xics; -} - -static int spapr_irq_post_load_dual(SpaprMachineState *spapr, int version_= id) -{ - return spapr_irq_current(spapr)->post_load(spapr, version_id); -} - /* * Define values in sync with the XIVE and XICS backend */ @@ -171,8 +135,6 @@ SpaprIrq spapr_irq_dual =3D { .nr_msis =3D SPAPR_NR_MSIS, .xics =3D true, .xive =3D true, - - .post_load =3D spapr_irq_post_load_dual, }; =20 =20 @@ -447,8 +409,11 @@ qemu_irq spapr_qirq(SpaprMachineState *spapr, int irq) =20 int spapr_irq_post_load(SpaprMachineState *spapr, int version_id) { + SpaprInterruptControllerClass *sicc; + spapr_irq_update_active_intc(spapr); - return spapr->irq->post_load(spapr, version_id); + sicc =3D SPAPR_INTC_GET_CLASS(spapr->active_intc); + return sicc->post_load(spapr->active_intc, version_id); } =20 void spapr_irq_reset(SpaprMachineState *spapr, Error **errp) @@ -589,8 +554,6 @@ SpaprIrq spapr_irq_xics_legacy =3D { .nr_msis =3D SPAPR_IRQ_XICS_LEGACY_NR_XIRQS, .xics =3D true, .xive =3D false, - - .post_load =3D spapr_irq_post_load_xics, }; =20 static void spapr_irq_register_types(void) diff --git a/include/hw/ppc/spapr_irq.h b/include/hw/ppc/spapr_irq.h index e02e44624b..08173e714c 100644 --- a/include/hw/ppc/spapr_irq.h +++ b/include/hw/ppc/spapr_irq.h @@ -62,6 +62,7 @@ typedef struct SpaprInterruptControllerClass { void (*print_info)(SpaprInterruptController *intc, Monitor *mon); void (*dt)(SpaprInterruptController *intc, uint32_t nr_servers, void *fdt, uint32_t phandle); + int (*post_load)(SpaprInterruptController *intc, int version_id); } SpaprInterruptControllerClass; =20 void spapr_irq_update_active_intc(SpaprMachineState *spapr); @@ -82,8 +83,6 @@ typedef struct SpaprIrq { uint32_t nr_msis; bool xics; bool xive; - - int (*post_load)(SpaprMachineState *spapr, int version_id); } SpaprIrq; =20 extern SpaprIrq spapr_irq_xics; diff --git a/include/hw/ppc/spapr_xive.h b/include/hw/ppc/spapr_xive.h index 64972754f9..d84bd5c229 100644 --- a/include/hw/ppc/spapr_xive.h +++ b/include/hw/ppc/spapr_xive.h @@ -55,7 +55,6 @@ typedef struct SpaprXive { #define SPAPR_XIVE_BLOCK_ID 0x0 =20 void spapr_xive_pic_print_info(SpaprXive *xive, Monitor *mon); -int spapr_xive_post_load(SpaprXive *xive, int version_id); =20 void spapr_xive_hcall_init(SpaprMachineState *spapr); void spapr_xive_set_tctx_os_cam(XiveTCTX *tctx); --=20 2.21.0 From nobody Sat Apr 27 01:55:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1570640258; cv=none; d=zoho.com; s=zohoarc; b=f1hHP2LJ1U1+U7GwGqfU2E+1r5w+co5J9safMBn5vVsSDn6CvNjZijky/cQoFA61oARZkFyOs/7EXuK7HRj7kNVslvl55o9xvMG0BzvOb2wgtxmsNrk5q97HME+EO2VBCVVXMKbsJUqOMPra8QiGIdkQJJv87GKg5KsOo5ACNC8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1570640258; 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Wed, 09 Oct 2019 02:08:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iI59a-0006ye-Qd for qemu-devel@nongnu.org; Wed, 09 Oct 2019 02:08:56 -0400 Received: from bilbo.ozlabs.org ([203.11.71.1]:49505 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iI59Z-0006YK-Fb; Wed, 09 Oct 2019 02:08:54 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 46p3gF68zTz9sRV; Wed, 9 Oct 2019 17:08:25 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1570601305; bh=79kRG/Lr74o1v3I9G3aWELqBkUgiyirJyENd84HNoaU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=huojG8d4VguYvSoUvhzDONPQz4DE9ofCndwpQs401tiYqz4K/wly9vU+/NhCBzWtx MnDdCUJ26SDjJoAw5sNbPLlTcNhw6BDxbMkbD0tmmCnoWgmJbHswCGvU+s8wq/PRh/ FABLGhezIXzzuDxF5fZRiSNsRMQWJdcnYe0MVYYA= From: David Gibson To: qemu-devel@nongnu.org, clg@kaod.org, qemu-ppc@nongnu.org Subject: [PATCH v4 15/19] spapr: Remove SpaprIrq::nr_msis Date: Wed, 9 Oct 2019 17:08:14 +1100 Message-Id: <20191009060818.29719-16-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191009060818.29719-1-david@gibson.dropbear.id.au> References: <20191009060818.29719-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jason Wang , Riku Voipio , groug@kaod.org, Laurent Vivier , Paolo Bonzini , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , philmd@redhat.com, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The nr_msis value we use here has to line up with whether we're using legacy or modern irq allocation. Therefore it's safer to derive it based on legacy_irq_allocation rather than having SpaprIrq contain a canned value. Signed-off-by: David Gibson Reviewed-by: Greg Kurz Reviewed-by: C=C3=A9dric Le Goater --- hw/ppc/spapr.c | 5 ++--- hw/ppc/spapr_irq.c | 26 +++++++++++++++++--------- hw/ppc/spapr_pci.c | 7 ++++--- include/hw/pci-host/spapr.h | 4 ++-- include/hw/ppc/spapr_irq.h | 4 +--- 5 files changed, 26 insertions(+), 20 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index e880db5d38..153cc54354 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -1275,7 +1275,7 @@ static void *spapr_build_fdt(SpaprMachineState *spapr) } =20 QLIST_FOREACH(phb, &spapr->phbs, list) { - ret =3D spapr_dt_phb(phb, PHANDLE_INTC, fdt, spapr->irq->nr_msis, = NULL); + ret =3D spapr_dt_phb(spapr, phb, PHANDLE_INTC, fdt, NULL); if (ret < 0) { error_report("couldn't setup PCI devices in fdt"); exit(1); @@ -3910,8 +3910,7 @@ int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachine= State *spapr, return -1; } =20 - if (spapr_dt_phb(sphb, intc_phandle, fdt, spapr->irq->nr_msis, - fdt_start_offset)) { + if (spapr_dt_phb(spapr, sphb, intc_phandle, fdt, fdt_start_offset)) { error_setg(errp, "unable to create FDT node for PHB %d", sphb->ind= ex); return -1; } diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c index f3d18b1dad..076da31501 100644 --- a/hw/ppc/spapr_irq.c +++ b/hw/ppc/spapr_irq.c @@ -29,9 +29,14 @@ static const TypeInfo spapr_intc_info =3D { .class_size =3D sizeof(SpaprInterruptControllerClass), }; =20 -void spapr_irq_msi_init(SpaprMachineState *spapr, uint32_t nr_msis) +static void spapr_irq_msi_init(SpaprMachineState *spapr) { - spapr->irq_map_nr =3D nr_msis; + if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { + /* Legacy mode doesn't use this allocater */ + return; + } + + spapr->irq_map_nr =3D spapr_irq_nr_msis(spapr); spapr->irq_map =3D bitmap_new(spapr->irq_map_nr); } =20 @@ -102,7 +107,6 @@ int spapr_irq_init_kvm(int (*fn)(SpaprInterruptControll= er *, Error **), =20 SpaprIrq spapr_irq_xics =3D { .nr_xirqs =3D SPAPR_NR_XIRQS, - .nr_msis =3D SPAPR_NR_MSIS, .xics =3D true, .xive =3D false, }; @@ -113,7 +117,6 @@ SpaprIrq spapr_irq_xics =3D { =20 SpaprIrq spapr_irq_xive =3D { .nr_xirqs =3D SPAPR_NR_XIRQS, - .nr_msis =3D SPAPR_NR_MSIS, .xics =3D false, .xive =3D true, }; @@ -132,7 +135,6 @@ SpaprIrq spapr_irq_xive =3D { */ SpaprIrq spapr_irq_dual =3D { .nr_xirqs =3D SPAPR_NR_XIRQS, - .nr_msis =3D SPAPR_NR_MSIS, .xics =3D true, .xive =3D true, }; @@ -247,6 +249,15 @@ void spapr_irq_dt(SpaprMachineState *spapr, uint32_t n= r_servers, sicc->dt(spapr->active_intc, nr_servers, fdt, phandle); } =20 +uint32_t spapr_irq_nr_msis(SpaprMachineState *spapr) +{ + if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { + return spapr->irq->nr_xirqs; + } else { + return SPAPR_XIRQ_BASE + spapr->irq->nr_xirqs - SPAPR_IRQ_MSI; + } +} + void spapr_irq_init(SpaprMachineState *spapr, Error **errp) { MachineState *machine =3D MACHINE(spapr); @@ -267,9 +278,7 @@ void spapr_irq_init(SpaprMachineState *spapr, Error **e= rrp) } =20 /* Initialize the MSI IRQ allocator. */ - if (!SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { - spapr_irq_msi_init(spapr, spapr->irq->nr_msis); - } + spapr_irq_msi_init(spapr); =20 if (spapr->irq->xics) { Error *local_err =3D NULL; @@ -551,7 +560,6 @@ int spapr_irq_find(SpaprMachineState *spapr, int num, b= ool align, Error **errp) =20 SpaprIrq spapr_irq_xics_legacy =3D { .nr_xirqs =3D SPAPR_IRQ_XICS_LEGACY_NR_XIRQS, - .nr_msis =3D SPAPR_IRQ_XICS_LEGACY_NR_XIRQS, .xics =3D true, .xive =3D false, }; diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index 01ff41d4c4..cc0e7829b6 100644 --- a/hw/ppc/spapr_pci.c +++ b/hw/ppc/spapr_pci.c @@ -2277,8 +2277,8 @@ static void spapr_phb_pci_enumerate(SpaprPhbState *ph= b) =20 } =20 -int spapr_dt_phb(SpaprPhbState *phb, uint32_t intc_phandle, void *fdt, - uint32_t nr_msis, int *node_offset) +int spapr_dt_phb(SpaprMachineState *spapr, SpaprPhbState *phb, + uint32_t intc_phandle, void *fdt, int *node_offset) { int bus_off, i, j, ret; uint32_t bus_range[] =3D { cpu_to_be32(0), cpu_to_be32(0xff) }; @@ -2343,7 +2343,8 @@ int spapr_dt_phb(SpaprPhbState *phb, uint32_t intc_ph= andle, void *fdt, _FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof_ranges)); _FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg))); _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1)); - _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pe-total-#msi", nr_msis)); + _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pe-total-#msi", + spapr_irq_nr_msis(spapr))); =20 /* Dynamic DMA window */ if (phb->ddw_enabled) { diff --git a/include/hw/pci-host/spapr.h b/include/hw/pci-host/spapr.h index 23506f05d9..8877ff51fb 100644 --- a/include/hw/pci-host/spapr.h +++ b/include/hw/pci-host/spapr.h @@ -128,8 +128,8 @@ struct SpaprPhbState { #define SPAPR_PCI_NV2ATSD_WIN_SIZE (NVGPU_MAX_NUM * NVGPU_MAX_LINKS * \ 64 * KiB) =20 -int spapr_dt_phb(SpaprPhbState *phb, uint32_t intc_phandle, void *fdt, - uint32_t nr_msis, int *node_offset); +int spapr_dt_phb(SpaprMachineState *spapr, SpaprPhbState *phb, + uint32_t intc_phandle, void *fdt, int *node_offset); =20 void spapr_pci_rtas_init(void); =20 diff --git a/include/hw/ppc/spapr_irq.h b/include/hw/ppc/spapr_irq.h index 08173e714c..befe8e01dc 100644 --- a/include/hw/ppc/spapr_irq.h +++ b/include/hw/ppc/spapr_irq.h @@ -27,7 +27,6 @@ #define SPAPR_IRQ_MSI (SPAPR_XIRQ_BASE + 0x0300) =20 #define SPAPR_NR_XIRQS 0x1000 -#define SPAPR_NR_MSIS (SPAPR_XIRQ_BASE + SPAPR_NR_XIRQS - SPAPR_IRQ= _MSI) =20 typedef struct SpaprMachineState SpaprMachineState; =20 @@ -73,14 +72,13 @@ void spapr_irq_print_info(SpaprMachineState *spapr, Mon= itor *mon); void spapr_irq_dt(SpaprMachineState *spapr, uint32_t nr_servers, void *fdt, uint32_t phandle); =20 -void spapr_irq_msi_init(SpaprMachineState *spapr, uint32_t nr_msis); +uint32_t spapr_irq_nr_msis(SpaprMachineState *spapr); int spapr_irq_msi_alloc(SpaprMachineState *spapr, uint32_t num, bool align, Error **errp); void spapr_irq_msi_free(SpaprMachineState *spapr, int irq, uint32_t num); =20 typedef struct SpaprIrq { uint32_t nr_xirqs; - uint32_t nr_msis; bool xics; bool xive; } SpaprIrq; --=20 2.21.0 From nobody Sat Apr 27 01:55:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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Wed, 9 Oct 2019 09:39:16 -0700 (PDT) Received: from localhost ([::1]:52404 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iIEzY-00023X-Ce for importer@patchew.org; Wed, 09 Oct 2019 12:39:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60212) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iI59K-0001Yn-OM for qemu-devel@nongnu.org; Wed, 09 Oct 2019 02:08:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iI59I-0006dk-0y for qemu-devel@nongnu.org; Wed, 09 Oct 2019 02:08:38 -0400 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:52203 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iI59H-0006Zt-Gr; Wed, 09 Oct 2019 02:08:35 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 46p3gG16Wxz9sRX; Wed, 9 Oct 2019 17:08:25 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1570601306; bh=ordIfB5runr6H/Zd54LCEUbmiUQM9wPjNQzDIhuibZg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Jp0+4ZCJYQASIWp3aW2rKVbX2qj4FeWl/c47T8DynQdVozDAQwU6q0Sp/ZWSfgKWe Efh2wnnaGdroXxMk8g+2MGTA7YlhLhSPhZ/CHVBy4vIm2v6MRfaAHUoGnk3j5MkcwZ K5AQzpHa0a9gunjUOTYFcHQYsZoPmqArA9/KOVFA= From: David Gibson To: qemu-devel@nongnu.org, clg@kaod.org, qemu-ppc@nongnu.org Subject: [PATCH v4 16/19] spapr: Move SpaprIrq::nr_xirqs to SpaprMachineClass Date: Wed, 9 Oct 2019 17:08:15 +1100 Message-Id: <20191009060818.29719-17-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191009060818.29719-1-david@gibson.dropbear.id.au> References: <20191009060818.29719-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jason Wang , Riku Voipio , groug@kaod.org, Laurent Vivier , Paolo Bonzini , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , philmd@redhat.com, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" For the benefit of peripheral device allocation, the number of available irqs really wants to be the same on a given machine type version, regardless of what irq backends we are using. That's the case now, but only because we make sure the different SpaprIrq instances have the same value except for the special legacy one. Since this really only depends on machine type version, move the value to SpaprMachineClass instead of SpaprIrq. This also puts the code to set it to the lower value on old machine types right next to setting legacy_irq_allocation, which needs to go hand in hand. Signed-off-by: David Gibson Reviewed-by: Greg Kurz Reviewed-by: C=C3=A9dric Le Goater --- hw/ppc/spapr.c | 2 ++ hw/ppc/spapr_irq.c | 33 ++++++++++++++++----------------- include/hw/ppc/spapr.h | 1 + include/hw/ppc/spapr_irq.h | 1 - 4 files changed, 19 insertions(+), 18 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 153cc54354..e1ff03152e 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -4443,6 +4443,7 @@ static void spapr_machine_class_init(ObjectClass *oc,= void *data) smc->irq =3D &spapr_irq_dual; smc->dr_phb_enabled =3D true; smc->linux_pci_probe =3D true; + smc->nr_xirqs =3D SPAPR_NR_XIRQS; } =20 static const TypeInfo spapr_machine_info =3D { @@ -4578,6 +4579,7 @@ static void spapr_machine_3_0_class_options(MachineCl= ass *mc) compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); =20 smc->legacy_irq_allocation =3D true; + smc->nr_xirqs =3D 0x400; smc->irq =3D &spapr_irq_xics_legacy; } =20 diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c index 076da31501..2768f9a765 100644 --- a/hw/ppc/spapr_irq.c +++ b/hw/ppc/spapr_irq.c @@ -106,7 +106,6 @@ int spapr_irq_init_kvm(int (*fn)(SpaprInterruptControll= er *, Error **), */ =20 SpaprIrq spapr_irq_xics =3D { - .nr_xirqs =3D SPAPR_NR_XIRQS, .xics =3D true, .xive =3D false, }; @@ -116,7 +115,6 @@ SpaprIrq spapr_irq_xics =3D { */ =20 SpaprIrq spapr_irq_xive =3D { - .nr_xirqs =3D SPAPR_NR_XIRQS, .xics =3D false, .xive =3D true, }; @@ -134,7 +132,6 @@ SpaprIrq spapr_irq_xive =3D { * Define values in sync with the XIVE and XICS backend */ SpaprIrq spapr_irq_dual =3D { - .nr_xirqs =3D SPAPR_NR_XIRQS, .xics =3D true, .xive =3D true, }; @@ -251,16 +248,19 @@ void spapr_irq_dt(SpaprMachineState *spapr, uint32_t = nr_servers, =20 uint32_t spapr_irq_nr_msis(SpaprMachineState *spapr) { - if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { - return spapr->irq->nr_xirqs; + SpaprMachineClass *smc =3D SPAPR_MACHINE_GET_CLASS(spapr); + + if (smc->legacy_irq_allocation) { + return smc->nr_xirqs; } else { - return SPAPR_XIRQ_BASE + spapr->irq->nr_xirqs - SPAPR_IRQ_MSI; + return SPAPR_XIRQ_BASE + smc->nr_xirqs - SPAPR_IRQ_MSI; } } =20 void spapr_irq_init(SpaprMachineState *spapr, Error **errp) { MachineState *machine =3D MACHINE(spapr); + SpaprMachineClass *smc =3D SPAPR_MACHINE_GET_CLASS(spapr); =20 if (machine_kernel_irqchip_split(machine)) { error_setg(errp, "kernel_irqchip split mode not supported on pseri= es"); @@ -298,8 +298,7 @@ void spapr_irq_init(SpaprMachineState *spapr, Error **e= rrp) return; } =20 - object_property_set_int(obj, spapr->irq->nr_xirqs, "nr-irqs", - &local_err); + object_property_set_int(obj, smc->nr_xirqs, "nr-irqs", &local_err); if (local_err) { error_propagate(errp, local_err); return; @@ -320,8 +319,7 @@ void spapr_irq_init(SpaprMachineState *spapr, Error **e= rrp) int i; =20 dev =3D qdev_create(NULL, TYPE_SPAPR_XIVE); - qdev_prop_set_uint32(dev, "nr-irqs", - spapr->irq->nr_xirqs + SPAPR_XIRQ_BASE); + qdev_prop_set_uint32(dev, "nr-irqs", smc->nr_xirqs + SPAPR_XIRQ_BA= SE); /* * 8 XIVE END structures per CPU. One for each available * priority @@ -346,17 +344,18 @@ void spapr_irq_init(SpaprMachineState *spapr, Error *= *errp) } =20 spapr->qirqs =3D qemu_allocate_irqs(spapr_set_irq, spapr, - spapr->irq->nr_xirqs + SPAPR_XIRQ_BA= SE); + smc->nr_xirqs + SPAPR_XIRQ_BASE); } =20 int spapr_irq_claim(SpaprMachineState *spapr, int irq, bool lsi, Error **e= rrp) { SpaprInterruptController *intcs[] =3D ALL_INTCS(spapr); int i; + SpaprMachineClass *smc =3D SPAPR_MACHINE_GET_CLASS(spapr); int rc; =20 assert(irq >=3D SPAPR_XIRQ_BASE); - assert(irq < (spapr->irq->nr_xirqs + SPAPR_XIRQ_BASE)); + assert(irq < (smc->nr_xirqs + SPAPR_XIRQ_BASE)); =20 for (i =3D 0; i < ARRAY_SIZE(intcs); i++) { SpaprInterruptController *intc =3D intcs[i]; @@ -376,9 +375,10 @@ void spapr_irq_free(SpaprMachineState *spapr, int irq,= int num) { SpaprInterruptController *intcs[] =3D ALL_INTCS(spapr); int i, j; + SpaprMachineClass *smc =3D SPAPR_MACHINE_GET_CLASS(spapr); =20 assert(irq >=3D SPAPR_XIRQ_BASE); - assert((irq + num) <=3D (spapr->irq->nr_xirqs + SPAPR_XIRQ_BASE)); + assert((irq + num) <=3D (smc->nr_xirqs + SPAPR_XIRQ_BASE)); =20 for (i =3D irq; i < (irq + num); i++) { for (j =3D 0; j < ARRAY_SIZE(intcs); j++) { @@ -395,6 +395,8 @@ void spapr_irq_free(SpaprMachineState *spapr, int irq, = int num) =20 qemu_irq spapr_qirq(SpaprMachineState *spapr, int irq) { + SpaprMachineClass *smc =3D SPAPR_MACHINE_GET_CLASS(spapr); + /* * This interface is basically for VIO and PHB devices to find the * right qemu_irq to manipulate, so we only allow access to the @@ -403,7 +405,7 @@ qemu_irq spapr_qirq(SpaprMachineState *spapr, int irq) * interfaces, we can change this if we need to in future. */ assert(irq >=3D SPAPR_XIRQ_BASE); - assert(irq < (spapr->irq->nr_xirqs + SPAPR_XIRQ_BASE)); + assert(irq < (smc->nr_xirqs + SPAPR_XIRQ_BASE)); =20 if (spapr->ics) { assert(ics_valid_irq(spapr->ics, irq)); @@ -556,10 +558,7 @@ int spapr_irq_find(SpaprMachineState *spapr, int num, = bool align, Error **errp) return first + ics->offset; } =20 -#define SPAPR_IRQ_XICS_LEGACY_NR_XIRQS 0x400 - SpaprIrq spapr_irq_xics_legacy =3D { - .nr_xirqs =3D SPAPR_IRQ_XICS_LEGACY_NR_XIRQS, .xics =3D true, .xive =3D false, }; diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index 763da757f0..623e8e3f93 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -119,6 +119,7 @@ struct SpaprMachineClass { bool use_ohci_by_default; /* use USB-OHCI instead of XHCI */ bool pre_2_10_has_unused_icps; bool legacy_irq_allocation; + uint32_t nr_xirqs; bool broken_host_serial_model; /* present real host info to the guest = */ bool pre_4_1_migration; /* don't migrate hpt-max-page-size */ bool linux_pci_probe; diff --git a/include/hw/ppc/spapr_irq.h b/include/hw/ppc/spapr_irq.h index befe8e01dc..5e150a6679 100644 --- a/include/hw/ppc/spapr_irq.h +++ b/include/hw/ppc/spapr_irq.h @@ -78,7 +78,6 @@ int spapr_irq_msi_alloc(SpaprMachineState *spapr, uint32_= t num, bool align, void spapr_irq_msi_free(SpaprMachineState *spapr, int irq, uint32_t num); =20 typedef struct SpaprIrq { - uint32_t nr_xirqs; bool xics; bool xive; } SpaprIrq; --=20 2.21.0 From nobody Sat Apr 27 01:55:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Wed, 09 Oct 2019 02:08:55 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 46p3gG0JQbz9sRR; Wed, 9 Oct 2019 17:08:26 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1570601306; bh=9yTcNpiWVKGQaswx1Ofh85ohqoWgUqX+55lDpGPWHt8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jQzmHZVEEWRRgYIeVaJ/CwOC99B/YySR4KrCmtUD7mlCTapCqdhdm1OE2Ze78hKOG gg3amARQ8zXQY16yH4C/As+cEojWyOSvH5IyL8v1RxN+98LOe9EyFLNrYq6NV3tk+I mSwXZjl27aSLl+CatpFCEovj8Vp/IO2JgJSmFEf8= From: David Gibson To: qemu-devel@nongnu.org, clg@kaod.org, qemu-ppc@nongnu.org Subject: [PATCH v4 17/19] spapr: Remove last pieces of SpaprIrq Date: Wed, 9 Oct 2019 17:08:16 +1100 Message-Id: <20191009060818.29719-18-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191009060818.29719-1-david@gibson.dropbear.id.au> References: <20191009060818.29719-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jason Wang , Riku Voipio , groug@kaod.org, Laurent Vivier , Paolo Bonzini , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , philmd@redhat.com, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The only thing remaining in this structure are the flags to allow either XICS or XIVE to be present. These actually make more sense as spapr capabilities - that way they can take advantage of the existing infrastructure to sanity check capability states across migration and so forth. Signed-off-by: David Gibson Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Greg Kurz --- hw/ppc/spapr.c | 40 ++++++++++-------- hw/ppc/spapr_caps.c | 64 +++++++++++++++++++++++++++++ hw/ppc/spapr_hcall.c | 7 ++-- hw/ppc/spapr_irq.c | 84 ++------------------------------------ include/hw/ppc/spapr.h | 10 +++-- include/hw/ppc/spapr_irq.h | 10 ----- 6 files changed, 103 insertions(+), 112 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index e1ff03152e..bf9fdb1693 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -1072,12 +1072,13 @@ static void spapr_dt_ov5_platform_support(SpaprMach= ineState *spapr, void *fdt, 26, 0x40, /* Radix options: GTSE =3D=3D yes. */ }; =20 - if (spapr->irq->xics && spapr->irq->xive) { + if (spapr_get_cap(spapr, SPAPR_CAP_XICS) + && spapr_get_cap(spapr, SPAPR_CAP_XIVE)) { val[1] =3D SPAPR_OV5_XIVE_BOTH; - } else if (spapr->irq->xive) { + } else if (spapr_get_cap(spapr, SPAPR_CAP_XIVE)) { val[1] =3D SPAPR_OV5_XIVE_EXPLOIT; } else { - assert(spapr->irq->xics); + assert(spapr_get_cap(spapr, SPAPR_CAP_XICS)); val[1] =3D SPAPR_OV5_XIVE_LEGACY; } =20 @@ -2075,6 +2076,8 @@ static const VMStateDescription vmstate_spapr =3D { &vmstate_spapr_dtb, &vmstate_spapr_cap_large_decr, &vmstate_spapr_cap_ccf_assist, + &vmstate_spapr_cap_xics, + &vmstate_spapr_cap_xive, NULL } }; @@ -2775,7 +2778,7 @@ static void spapr_machine_init(MachineState *machine) spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); =20 /* advertise XIVE on POWER9 machines */ - if (spapr->irq->xive) { + if (spapr_get_cap(spapr, SPAPR_CAP_XIVE)) { spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); } =20 @@ -3242,14 +3245,18 @@ static void spapr_set_vsmt(Object *obj, Visitor *v,= const char *name, static char *spapr_get_ic_mode(Object *obj, Error **errp) { SpaprMachineState *spapr =3D SPAPR_MACHINE(obj); + SpaprMachineClass *smc =3D SPAPR_MACHINE_GET_CLASS(spapr); =20 - if (spapr->irq =3D=3D &spapr_irq_xics_legacy) { + if (smc->legacy_irq_allocation) { return g_strdup("legacy"); - } else if (spapr->irq =3D=3D &spapr_irq_xics) { + } else if (spapr_get_cap(spapr, SPAPR_CAP_XICS) + && !spapr_get_cap(spapr, SPAPR_CAP_XIVE)) { return g_strdup("xics"); - } else if (spapr->irq =3D=3D &spapr_irq_xive) { + } else if (!spapr_get_cap(spapr, SPAPR_CAP_XICS) + && spapr_get_cap(spapr, SPAPR_CAP_XIVE)) { return g_strdup("xive"); - } else if (spapr->irq =3D=3D &spapr_irq_dual) { + } else if (spapr_get_cap(spapr, SPAPR_CAP_XICS) + && spapr_get_cap(spapr, SPAPR_CAP_XIVE)) { return g_strdup("dual"); } g_assert_not_reached(); @@ -3266,11 +3273,14 @@ static void spapr_set_ic_mode(Object *obj, const ch= ar *value, Error **errp) =20 /* The legacy IRQ backend can not be set */ if (strcmp(value, "xics") =3D=3D 0) { - spapr->irq =3D &spapr_irq_xics; + object_property_set_bool(obj, true, "cap-xics", errp); + object_property_set_bool(obj, false, "cap-xive", errp); } else if (strcmp(value, "xive") =3D=3D 0) { - spapr->irq =3D &spapr_irq_xive; + object_property_set_bool(obj, false, "cap-xics", errp); + object_property_set_bool(obj, true, "cap-xive", errp); } else if (strcmp(value, "dual") =3D=3D 0) { - spapr->irq =3D &spapr_irq_dual; + object_property_set_bool(obj, true, "cap-xics", errp); + object_property_set_bool(obj, true, "cap-xive", errp); } else { error_setg(errp, "Bad value for \"ic-mode\" property"); } @@ -3309,7 +3319,6 @@ static void spapr_set_host_serial(Object *obj, const = char *value, Error **errp) static void spapr_instance_init(Object *obj) { SpaprMachineState *spapr =3D SPAPR_MACHINE(obj); - SpaprMachineClass *smc =3D SPAPR_MACHINE_GET_CLASS(spapr); =20 spapr->htab_fd =3D -1; spapr->use_hotplug_event_source =3D true; @@ -3345,7 +3354,6 @@ static void spapr_instance_init(Object *obj) spapr_get_msix_emulation, NULL, NULL); =20 /* The machine class defines the default interrupt controller mode */ - spapr->irq =3D smc->irq; object_property_add_str(obj, "ic-mode", spapr_get_ic_mode, spapr_set_ic_mode, NULL); object_property_set_description(obj, "ic-mode", @@ -4439,8 +4447,9 @@ static void spapr_machine_class_init(ObjectClass *oc,= void *data) smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] =3D SPAPR_CAP_OFF; smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] =3D SPAPR_CAP_ON; smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] =3D SPAPR_CAP_OFF; + smc->default_caps.caps[SPAPR_CAP_XICS] =3D SPAPR_CAP_ON; + smc->default_caps.caps[SPAPR_CAP_XIVE] =3D SPAPR_CAP_ON; spapr_caps_add_properties(smc, &error_abort); - smc->irq =3D &spapr_irq_dual; smc->dr_phb_enabled =3D true; smc->linux_pci_probe =3D true; smc->nr_xirqs =3D SPAPR_NR_XIRQS; @@ -4539,7 +4548,7 @@ static void spapr_machine_4_0_class_options(MachineCl= ass *mc) spapr_machine_4_1_class_options(mc); compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); smc->phb_placement =3D phb_placement_4_0; - smc->irq =3D &spapr_irq_xics; + smc->default_caps.caps[SPAPR_CAP_XIVE] =3D SPAPR_CAP_OFF; smc->pre_4_1_migration =3D true; } =20 @@ -4580,7 +4589,6 @@ static void spapr_machine_3_0_class_options(MachineCl= ass *mc) =20 smc->legacy_irq_allocation =3D true; smc->nr_xirqs =3D 0x400; - smc->irq =3D &spapr_irq_xics_legacy; } =20 DEFINE_SPAPR_MACHINE(3_0, "3.0", false); diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c index 481dfd2a27..e06fd386f6 100644 --- a/hw/ppc/spapr_caps.c +++ b/hw/ppc/spapr_caps.c @@ -496,6 +496,42 @@ static void cap_ccf_assist_apply(SpaprMachineState *sp= apr, uint8_t val, } } =20 +static void cap_xics_apply(SpaprMachineState *spapr, uint8_t val, Error **= errp) +{ + SpaprMachineClass *smc =3D SPAPR_MACHINE_GET_CLASS(spapr); + + if (!val) { + if (!spapr_get_cap(spapr, SPAPR_CAP_XIVE)) { + error_setg(errp, +"No interrupt controllers enabled, try cap-xics=3Don or cap-xive=3Don"); + return; + } + + if (smc->legacy_irq_allocation) { + error_setg(errp, "This machine version requires XICS support"); + return; + } + } +} + +static void cap_xive_apply(SpaprMachineState *spapr, uint8_t val, Error **= errp) +{ + SpaprMachineClass *smc =3D SPAPR_MACHINE_GET_CLASS(spapr); + PowerPCCPU *cpu =3D POWERPC_CPU(first_cpu); + + if (val) { + if (smc->legacy_irq_allocation) { + error_setg(errp, "This machine version cannot support XIVE"); + return; + } + if (!ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, + spapr->max_compat_pvr)) { + error_setg(errp, "XIVE requires POWER9 CPU"); + return; + } + } +} + SpaprCapabilityInfo capability_table[SPAPR_CAP_NUM] =3D { [SPAPR_CAP_HTM] =3D { .name =3D "htm", @@ -595,6 +631,24 @@ SpaprCapabilityInfo capability_table[SPAPR_CAP_NUM] = =3D { .type =3D "bool", .apply =3D cap_ccf_assist_apply, }, + [SPAPR_CAP_XICS] =3D { + .name =3D "xics", + .description =3D "Allow XICS interrupt controller", + .index =3D SPAPR_CAP_XICS, + .get =3D spapr_cap_get_bool, + .set =3D spapr_cap_set_bool, + .type =3D "bool", + .apply =3D cap_xics_apply, + }, + [SPAPR_CAP_XIVE] =3D { + .name =3D "xive", + .description =3D "Allow XIVE interrupt controller", + .index =3D SPAPR_CAP_XIVE, + .get =3D spapr_cap_get_bool, + .set =3D spapr_cap_set_bool, + .type =3D "bool", + .apply =3D cap_xive_apply, + }, }; =20 static SpaprCapabilities default_caps_with_cpu(SpaprMachineState *spapr, @@ -641,6 +695,14 @@ static SpaprCapabilities default_caps_with_cpu(SpaprMa= chineState *spapr, caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] =3D mps; } =20 + /* + * POWER8 machines don't have XIVE + */ + if (!ppc_type_check_compat(cputype, CPU_POWERPC_LOGICAL_3_00, + 0, spapr->max_compat_pvr)) { + caps.caps[SPAPR_CAP_XIVE] =3D SPAPR_CAP_OFF; + } + return caps; } =20 @@ -734,6 +796,8 @@ SPAPR_CAP_MIG_STATE(hpt_maxpagesize, SPAPR_CAP_HPT_MAXP= AGESIZE); SPAPR_CAP_MIG_STATE(nested_kvm_hv, SPAPR_CAP_NESTED_KVM_HV); SPAPR_CAP_MIG_STATE(large_decr, SPAPR_CAP_LARGE_DECREMENTER); SPAPR_CAP_MIG_STATE(ccf_assist, SPAPR_CAP_CCF_ASSIST); +SPAPR_CAP_MIG_STATE(xics, SPAPR_CAP_XICS); +SPAPR_CAP_MIG_STATE(xive, SPAPR_CAP_XIVE); =20 void spapr_caps_init(SpaprMachineState *spapr) { diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index 140f05c1c6..cb4c6edf63 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc/spapr_hcall.c @@ -1784,13 +1784,13 @@ static target_ulong h_client_architecture_support(P= owerPCCPU *cpu, * terminate the boot. */ if (guest_xive) { - if (!spapr->irq->xive) { + if (!spapr_get_cap(spapr, SPAPR_CAP_XIVE)) { error_report( "Guest requested unavailable interrupt mode (XIVE), try the ic-mode=3Dxive= or ic-mode=3Ddual machine property"); exit(EXIT_FAILURE); } } else { - if (!spapr->irq->xics) { + if (!spapr_get_cap(spapr, SPAPR_CAP_XICS)) { error_report( "Guest requested unavailable interrupt mode (XICS), either don't set the i= c-mode machine property or try ic-mode=3Dxics or ic-mode=3Ddual"); exit(EXIT_FAILURE); @@ -1804,7 +1804,8 @@ static target_ulong h_client_architecture_support(Pow= erPCCPU *cpu, */ if (!spapr->cas_reboot) { spapr->cas_reboot =3D spapr_ovec_test(ov5_updates, OV5_XIVE_EXPLOI= T) - && spapr->irq->xics && spapr->irq->xive; + && spapr_get_cap(spapr, SPAPR_CAP_XICS) + && spapr_get_cap(spapr, SPAPR_CAP_XIVE); } =20 spapr_ovec_cleanup(ov5_updates); diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c index 2768f9a765..473fc8780a 100644 --- a/hw/ppc/spapr_irq.c +++ b/hw/ppc/spapr_irq.c @@ -101,90 +101,19 @@ int spapr_irq_init_kvm(int (*fn)(SpaprInterruptContro= ller *, Error **), return 0; } =20 -/* - * XICS IRQ backend. - */ - -SpaprIrq spapr_irq_xics =3D { - .xics =3D true, - .xive =3D false, -}; - -/* - * XIVE IRQ backend. - */ - -SpaprIrq spapr_irq_xive =3D { - .xics =3D false, - .xive =3D true, -}; - -/* - * Dual XIVE and XICS IRQ backend. - * - * Both interrupt mode, XIVE and XICS, objects are created but the - * machine starts in legacy interrupt mode (XICS). It can be changed - * by the CAS negotiation process and, in that case, the new mode is - * activated after an extra machine reset. - */ - -/* - * Define values in sync with the XIVE and XICS backend - */ -SpaprIrq spapr_irq_dual =3D { - .xics =3D true, - .xive =3D true, -}; - - static int spapr_irq_check(SpaprMachineState *spapr, Error **errp) { MachineState *machine =3D MACHINE(spapr); =20 - /* - * Sanity checks on non-P9 machines. On these, XIVE is not - * advertised, see spapr_dt_ov5_platform_support() - */ - if (!ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, - 0, spapr->max_compat_pvr)) { - /* - * If the 'dual' interrupt mode is selected, force XICS as CAS - * negotiation is useless. - */ - if (spapr->irq =3D=3D &spapr_irq_dual) { - spapr->irq =3D &spapr_irq_xics; - return 0; - } - - /* - * Non-P9 machines using only XIVE is a bogus setup. We have two - * scenarios to take into account because of the compat mode: - * - * 1. POWER7/8 machines should fail to init later on when creating - * the XIVE interrupt presenters because a POWER9 exception - * model is required. - - * 2. POWER9 machines using the POWER8 compat mode won't fail and - * will let the OS boot with a partial XIVE setup : DT - * properties but no hcalls. - * - * To cover both and not confuse the OS, add an early failure in - * QEMU. - */ - if (spapr->irq =3D=3D &spapr_irq_xive) { - error_setg(errp, "XIVE-only machines require a POWER9 CPU"); - return -1; - } - } - /* * On a POWER9 host, some older KVM XICS devices cannot be destroyed a= nd * re-created. Detect that early to avoid QEMU to exit later when the * guest reboots. */ if (kvm_enabled() && - spapr->irq =3D=3D &spapr_irq_dual && machine_kernel_irqchip_required(machine) && + spapr_get_cap(spapr, SPAPR_CAP_XICS) && + spapr_get_cap(spapr, SPAPR_CAP_XIVE) && xics_kvm_has_broken_disconnect(spapr)) { error_setg(errp, "KVM is too old to support ic-mode=3Ddual,kernel-= irqchip=3Don"); return -1; @@ -280,7 +209,7 @@ void spapr_irq_init(SpaprMachineState *spapr, Error **e= rrp) /* Initialize the MSI IRQ allocator. */ spapr_irq_msi_init(spapr); =20 - if (spapr->irq->xics) { + if (spapr_get_cap(spapr, SPAPR_CAP_XICS)) { Error *local_err =3D NULL; Object *obj; =20 @@ -313,7 +242,7 @@ void spapr_irq_init(SpaprMachineState *spapr, Error **e= rrp) spapr->ics =3D ICS_SPAPR(obj); } =20 - if (spapr->irq->xive) { + if (spapr_get_cap(spapr, SPAPR_CAP_XIVE)) { uint32_t nr_servers =3D spapr_max_server_number(spapr); DeviceState *dev; int i; @@ -558,11 +487,6 @@ int spapr_irq_find(SpaprMachineState *spapr, int num, = bool align, Error **errp) return first + ics->offset; } =20 -SpaprIrq spapr_irq_xics_legacy =3D { - .xics =3D true, - .xive =3D false, -}; - static void spapr_irq_register_types(void) { type_register_static(&spapr_intc_info); diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index 623e8e3f93..d3b4dd7de3 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -79,8 +79,12 @@ typedef enum { #define SPAPR_CAP_LARGE_DECREMENTER 0x08 /* Count Cache Flush Assist HW Instruction */ #define SPAPR_CAP_CCF_ASSIST 0x09 +/* XICS interrupt controller */ +#define SPAPR_CAP_XICS 0x0a +/* XIVE interrupt controller */ +#define SPAPR_CAP_XIVE 0x0b /* Num Caps */ -#define SPAPR_CAP_NUM (SPAPR_CAP_CCF_ASSIST + 1) +#define SPAPR_CAP_NUM (SPAPR_CAP_XIVE + 1) =20 /* * Capability Values @@ -131,7 +135,6 @@ struct SpaprMachineClass { hwaddr *nv2atsd, Error **errp); SpaprResizeHpt resize_hpt_default; SpaprCapabilities default_caps; - SpaprIrq *irq; }; =20 /** @@ -195,7 +198,6 @@ struct SpaprMachineState { =20 int32_t irq_map_nr; unsigned long *irq_map; - SpaprIrq *irq; qemu_irq *qirqs; SpaprInterruptController *active_intc; ICSState *ics; @@ -870,6 +872,8 @@ extern const VMStateDescription vmstate_spapr_cap_hpt_m= axpagesize; extern const VMStateDescription vmstate_spapr_cap_nested_kvm_hv; extern const VMStateDescription vmstate_spapr_cap_large_decr; extern const VMStateDescription vmstate_spapr_cap_ccf_assist; +extern const VMStateDescription vmstate_spapr_cap_xics; +extern const VMStateDescription vmstate_spapr_cap_xive; =20 static inline uint8_t spapr_get_cap(SpaprMachineState *spapr, int cap) { diff --git a/include/hw/ppc/spapr_irq.h b/include/hw/ppc/spapr_irq.h index 5e150a6679..71aee13743 100644 --- a/include/hw/ppc/spapr_irq.h +++ b/include/hw/ppc/spapr_irq.h @@ -77,16 +77,6 @@ int spapr_irq_msi_alloc(SpaprMachineState *spapr, uint32= _t num, bool align, Error **errp); void spapr_irq_msi_free(SpaprMachineState *spapr, int irq, uint32_t num); =20 -typedef struct SpaprIrq { - bool xics; - bool xive; -} SpaprIrq; - -extern SpaprIrq spapr_irq_xics; -extern SpaprIrq spapr_irq_xics_legacy; -extern SpaprIrq spapr_irq_xive; -extern SpaprIrq spapr_irq_dual; - void spapr_irq_init(SpaprMachineState *spapr, Error **errp); int spapr_irq_claim(SpaprMachineState *spapr, int irq, bool lsi, Error **e= rrp); void spapr_irq_free(SpaprMachineState *spapr, int irq, int num); --=20 2.21.0 From nobody Sat Apr 27 01:55:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1570640966; cv=none; d=zoho.com; s=zohoarc; b=KA/vr3dh9pLN7aRsJzvRpReK9r3wPc+ZuDgeDK4M5+OKOGpPbmF8Kpp3+H9aAkr7eIwiik14ZkY1xzu/NabSeuuUg/S4l4hKrLDfcNzNnJsrZdxN4L4XW5gFu6ODg16rDIqqfYfaiAl+Mofcl2QcmnL1JOqmGRNMq4AzVYY6+tU= ARC-Message-Signature: i=1; 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Wed, 09 Oct 2019 13:09:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60195) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iI59K-0001Yh-2r for qemu-devel@nongnu.org; Wed, 09 Oct 2019 02:08:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iI59I-0006dr-1I for qemu-devel@nongnu.org; Wed, 09 Oct 2019 02:08:37 -0400 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:45563 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iI59H-0006Zx-IZ; Wed, 09 Oct 2019 02:08:35 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 46p3gG28KMz9sRY; Wed, 9 Oct 2019 17:08:26 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1570601306; bh=Kuc1pbdxxbDbylKP4SVx8Y6ay10yqb5zujtXnKhy4EE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=othFgXRGFot13/pBUQXCtcSm+rRQyQ7zrI1qI49/R02SekkahWHyt7G6rDESRnnkP neZOvozUizj4WoX+NovtCvU23g8L/nn/ykmj5Qu9f97kGTVH8xzldeR20+IJNRhTXT 2SWBLNkoUljo4JiVyJX5/BatEoUYJKUpliQzr1Xw= From: David Gibson To: qemu-devel@nongnu.org, clg@kaod.org, qemu-ppc@nongnu.org Subject: [PATCH v4 18/19] spapr: Handle irq backend changes with VFIO PCI devices Date: Wed, 9 Oct 2019 17:08:17 +1100 Message-Id: <20191009060818.29719-19-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191009060818.29719-1-david@gibson.dropbear.id.au> References: <20191009060818.29719-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexey Kardashevskiy , Jason Wang , Riku Voipio , groug@kaod.org, Laurent Vivier , Alex Williamson , Paolo Bonzini , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , philmd@redhat.com, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" pseries machine type can have one of two different interrupt controllers in use depending on feature negotiation with the guest. Usually this is invisible to devices, because they route to a common set of qemu_irqs which in turn dispatch to the correct back end. VFIO passthrough devices, however, wire themselves up directly to the KVM irqchip for performance, which means they are affected by this change in interrupt controller. Luckily, there's a notifier chain that will tell VFIO devices to update their mappings - we just need to call it whenever the intc backend might change. In addition, we make sure we set an active intc earlier, because otherwise vfio can issue a false warning, because it doesn't think a KVM irqchip is in use (which is essentially for good INTx performance). Cc: Alex Williamson Cc: Alexey Kardashevskiy Signed-off-by: David Gibson --- hw/ppc/spapr_irq.c | 6 ++++++ hw/ppc/spapr_pci.c | 9 +++++++++ include/hw/ppc/spapr.h | 1 + 3 files changed, 16 insertions(+) diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c index 473fc8780a..7964e4a1b8 100644 --- a/hw/ppc/spapr_irq.c +++ b/hw/ppc/spapr_irq.c @@ -409,6 +409,12 @@ static void set_active_intc(SpaprMachineState *spapr, } =20 spapr->active_intc =3D new_intc; + + /* + * We've changed the interrupt routing at the KVM level, let VFIO + * devices know they need to readjust. + */ + spapr_pci_fire_intx_routing_notifiers(spapr); } =20 void spapr_irq_update_active_intc(SpaprMachineState *spapr) diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index cc0e7829b6..3bcf6325d4 100644 --- a/hw/ppc/spapr_pci.c +++ b/hw/ppc/spapr_pci.c @@ -93,6 +93,15 @@ PCIDevice *spapr_pci_find_dev(SpaprMachineState *spapr, = uint64_t buid, return pci_find_device(phb->bus, bus_num, devfn); } =20 +void spapr_pci_fire_intx_routing_notifiers(SpaprMachineState *spapr) +{ + SpaprPhbState *sphb; + + QLIST_FOREACH(sphb, &spapr->phbs, list) { + pci_bus_fire_intx_routing_notifier(PCI_HOST_BRIDGE(sphb)->bus); + } +} + static uint32_t rtas_pci_cfgaddr(uint32_t arg) { /* This handles the encoding of extended config space addresses */ diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index d3b4dd7de3..66b68fdd5e 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -805,6 +805,7 @@ void spapr_clear_pending_events(SpaprMachineState *spap= r); int spapr_max_server_number(SpaprMachineState *spapr); void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, uint64_t pte0, uint64_t pte1); +void spapr_pci_fire_intx_routing_notifiers(SpaprMachineState *spapr); =20 /* DRC callbacks. */ void spapr_core_release(DeviceState *dev); --=20 2.21.0 From nobody Sat Apr 27 01:55:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Wed, 09 Oct 2019 02:08:55 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 46p3gG2hDYz9sRW; Wed, 9 Oct 2019 17:08:26 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1570601306; bh=P19XTnLDc5zaBQFC5rg5tlmv5YglHHtbZRWyyk9OMWw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BD8zsfyJoFG9xUBavxd6Ba6ezZv8GfJta6rGmlRFgMzopoY+RkLw4OXk0LA1jWAwX YaDahK1VPYebg0KVw4xEwAmLPWIdJXIeCCeu8q8kjhQuIj84Lwo3OCS2kGR7GLBWyn L0/OmuZAosCmkdQpYQiGis2vWcYTLjO8zQId+6TI= From: David Gibson To: qemu-devel@nongnu.org, clg@kaod.org, qemu-ppc@nongnu.org Subject: [PATCH v4 19/19] spapr: Work around spurious warnings from vfio INTx initialization Date: Wed, 9 Oct 2019 17:08:18 +1100 Message-Id: <20191009060818.29719-20-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191009060818.29719-1-david@gibson.dropbear.id.au> References: <20191009060818.29719-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexey Kardashevskiy , Jason Wang , Riku Voipio , groug@kaod.org, Laurent Vivier , Alex Williamson , Paolo Bonzini , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , philmd@redhat.com, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Traditional PCI INTx for vfio devices can only perform well if using an in-kernel irqchip. Therefore, vfio_intx_update() issues a warning if an in kernel irqchip is not available. We usually do have an in-kernel irqchip available for pseries machines on POWER hosts. However, because the platform allows feature negotiation of what interrupt controller model to use, we don't currently initialize it until machine reset. vfio_intx_update() is called (first) from vfio_realize() before that, so it can issue a spurious warning, even if we will have an in kernel irqchip by the time we need it. To workaround this, make a call to spapr_irq_update_active_intc() from spapr_irq_init() which is called at machine realize time, before the vfio realize. This call will be pretty much obsoleted by the later call at reset time, but it serves to suppress the spurious warning from VFIO. Cc: Alex Williamson Cc: Alexey Kardashevskiy Signed-off-by: David Gibson --- hw/ppc/spapr_irq.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c index 7964e4a1b8..3aeb523f3e 100644 --- a/hw/ppc/spapr_irq.c +++ b/hw/ppc/spapr_irq.c @@ -274,6 +274,14 @@ void spapr_irq_init(SpaprMachineState *spapr, Error **= errp) =20 spapr->qirqs =3D qemu_allocate_irqs(spapr_set_irq, spapr, smc->nr_xirqs + SPAPR_XIRQ_BASE); + + /* + * Mostly we don't actually need this until reset, except that not + * having this set up can cause VFIO devices to issue a + * false-positive warning during realize(), because they don't yet + * have an in-kernel irq chip. + */ + spapr_irq_update_active_intc(spapr); } =20 int spapr_irq_claim(SpaprMachineState *spapr, int irq, bool lsi, Error **e= rrp) @@ -429,7 +437,8 @@ void spapr_irq_update_active_intc(SpaprMachineState *sp= apr) * this. */ new_intc =3D SPAPR_INTC(spapr->xive); - } else if (spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { + } else if (spapr->ov5_cas + && spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { new_intc =3D SPAPR_INTC(spapr->xive); } else { new_intc =3D SPAPR_INTC(spapr->ics); --=20 2.21.0