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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id z9sm19135541wrl.35.2019.10.08.10.18.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Oct 2019 10:18:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6nsvqi4Uzwusg0ywFGM1w0nIdrA70CDt5J8J4ZUSnF0=; b=vVqr5RLRSOcHUcGvlEnyp75DhJaCjBVVrtKHAyxmr3kyJ3CZNl5IdcAlpSmaTvlEkT baHySrNONEkgAS8XSE5OwCtw5ALHRqL7PfmO7SfwI0F0pPaYn8wzzxCzQk+IvQDsGO+Y ODpW5FMMrJHxXgvFgZSA6x0Ee2Ixq6/5y6a3IhbDiYwwCkIDG7MKDV1as4OabbPBW4wS j6rF8R8ipXjqh6Y9vnEh6Uu5g0Jp3OO8P07fv+iqGIrwIPYPwZaJJSt8oyo4S1Ix2kaX 5wdZD0dE2D4I5ZoE50sxFECjDMRcJ6EGfjD9DMMp4e1mG+rHuCe9MPim8ersxkZvqjY+ Gm2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6nsvqi4Uzwusg0ywFGM1w0nIdrA70CDt5J8J4ZUSnF0=; b=hjKs730xXgb1ntyEmIGXCDNl6k3oexZBEmBz/+93DXXQGzfVT3DbQWDujQe+YdkUX5 raf9foVDOtUtHeC6IfDuuUxz+Wzn97NFPLqIOHIh3FwfqLf3Vx7xpdrPW0FNDqViGR3y Q+x8wZj+tfuLuhELfV3sTuiV3rFMLldS4YWHOaATDBKzOeermOV98wkfhf5fIOXPiUJb 1xOhE1lYuVqK3uoTtknEm/AJeRW2ViDGX486B0HxRFvSs8HffvWZHluuJOri+mmGmgvu GUzjBhkm3wwjoZIBHVMEOhnCPaqn5EtgYXGyGKXw8h+Xi/wKCz/LA/NuElCR82ejrdpm rvqA== X-Gm-Message-State: APjAAAUPvDZdFrcU4or8Q/Cr2FmEm8oz8zak0ak7GcanDEHnNYLNWyMP 9y5lcZJ4tPp5VH5xvov/3dCJTA== X-Google-Smtp-Source: APXvYqyyub6rfJwPu8Dp+4ayE7S51tuHKmAISNBQBk+R9mNsKXulW3lYNoBJNs60Mk52IYVog608JQ== X-Received: by 2002:a5d:4090:: with SMTP id o16mr10300916wrp.172.1570555086158; Tue, 08 Oct 2019 10:18:06 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 18/21] hw/timer/imx_gpt.c: Switch to transaction-based ptimer API Date: Tue, 8 Oct 2019 18:17:37 +0100 Message-Id: <20191008171740.9679-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191008171740.9679-1-peter.maydell@linaro.org> References: <20191008171740.9679-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Paolo Bonzini Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Switch the imx_epit.c code away from bottom-half based ptimers to the new transaction-based ptimer API. This just requires adding begin/commit calls around the various places that modify the ptimer state, and using the new ptimer_init() function to create the timer. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/timer/imx_gpt.c | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/hw/timer/imx_gpt.c b/hw/timer/imx_gpt.c index c535d191292..5c0d9a269ce 100644 --- a/hw/timer/imx_gpt.c +++ b/hw/timer/imx_gpt.c @@ -16,7 +16,6 @@ #include "hw/irq.h" #include "hw/timer/imx_gpt.h" #include "migration/vmstate.h" -#include "qemu/main-loop.h" #include "qemu/module.h" #include "qemu/log.h" =20 @@ -127,6 +126,7 @@ static const IMXClk imx7_gpt_clocks[] =3D { CLK_NONE, /* 111 not defined */ }; =20 +/* Must be called from within ptimer_transaction_begin/commit block */ static void imx_gpt_set_freq(IMXGPTState *s) { uint32_t clksrc =3D extract32(s->cr, GPT_CR_CLKSRC_SHIFT, 3); @@ -167,6 +167,7 @@ static inline uint32_t imx_gpt_find_limit(uint32_t coun= t, uint32_t reg, return timeout; } =20 +/* Must be called from within ptimer_transaction_begin/commit block */ static void imx_gpt_compute_next_timeout(IMXGPTState *s, bool event) { uint32_t timeout =3D GPT_TIMER_MAX; @@ -313,6 +314,7 @@ static uint64_t imx_gpt_read(void *opaque, hwaddr offse= t, unsigned size) =20 static void imx_gpt_reset_common(IMXGPTState *s, bool is_soft_reset) { + ptimer_transaction_begin(s->timer); /* stop timer */ ptimer_stop(s->timer); =20 @@ -350,6 +352,7 @@ static void imx_gpt_reset_common(IMXGPTState *s, bool i= s_soft_reset) if (s->freq && (s->cr & GPT_CR_EN)) { ptimer_run(s->timer, 1); } + ptimer_transaction_commit(s->timer); } =20 static void imx_gpt_soft_reset(DeviceState *dev) @@ -382,6 +385,7 @@ static void imx_gpt_write(void *opaque, hwaddr offset, = uint64_t value, imx_gpt_soft_reset(DEVICE(s)); } else { /* set our freq, as the source might have changed */ + ptimer_transaction_begin(s->timer); imx_gpt_set_freq(s); =20 if ((oldreg ^ s->cr) & GPT_CR_EN) { @@ -397,12 +401,15 @@ static void imx_gpt_write(void *opaque, hwaddr offset= , uint64_t value, ptimer_stop(s->timer); } } + ptimer_transaction_commit(s->timer); } break; =20 case 1: /* Prescaler */ s->pr =3D value & 0xfff; + ptimer_transaction_begin(s->timer); imx_gpt_set_freq(s); + ptimer_transaction_commit(s->timer); break; =20 case 2: /* SR */ @@ -414,13 +421,16 @@ static void imx_gpt_write(void *opaque, hwaddr offset= , uint64_t value, s->ir =3D value & 0x3f; imx_gpt_update_int(s); =20 + ptimer_transaction_begin(s->timer); imx_gpt_compute_next_timeout(s, false); + ptimer_transaction_commit(s->timer); =20 break; =20 case 4: /* OCR1 -- output compare register */ s->ocr1 =3D value; =20 + ptimer_transaction_begin(s->timer); /* In non-freerun mode, reset count when this register is written = */ if (!(s->cr & GPT_CR_FRR)) { s->next_timeout =3D GPT_TIMER_MAX; @@ -429,6 +439,7 @@ static void imx_gpt_write(void *opaque, hwaddr offset, = uint64_t value, =20 /* compute the new timeout */ imx_gpt_compute_next_timeout(s, false); + ptimer_transaction_commit(s->timer); =20 break; =20 @@ -436,7 +447,9 @@ static void imx_gpt_write(void *opaque, hwaddr offset, = uint64_t value, s->ocr2 =3D value; =20 /* compute the new timeout */ + ptimer_transaction_begin(s->timer); imx_gpt_compute_next_timeout(s, false); + ptimer_transaction_commit(s->timer); =20 break; =20 @@ -444,7 +457,9 @@ static void imx_gpt_write(void *opaque, hwaddr offset, = uint64_t value, s->ocr3 =3D value; =20 /* compute the new timeout */ + ptimer_transaction_begin(s->timer); imx_gpt_compute_next_timeout(s, false); + ptimer_transaction_commit(s->timer); =20 break; =20 @@ -484,15 +499,13 @@ static void imx_gpt_realize(DeviceState *dev, Error *= *errp) { IMXGPTState *s =3D IMX_GPT(dev); SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); - QEMUBH *bh; =20 sysbus_init_irq(sbd, &s->irq); memory_region_init_io(&s->iomem, OBJECT(s), &imx_gpt_ops, s, TYPE_IMX_= GPT, 0x00001000); sysbus_init_mmio(sbd, &s->iomem); =20 - bh =3D qemu_bh_new(imx_gpt_timeout, s); - s->timer =3D ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); + s->timer =3D ptimer_init(imx_gpt_timeout, s, PTIMER_POLICY_DEFAULT); } =20 static void imx_gpt_class_init(ObjectClass *klass, void *data) --=20 2.20.1