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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id z9sm19135541wrl.35.2019.10.08.10.17.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Oct 2019 10:17:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kdkcGfyiI4qEGDjR65U9kIW9WP0Rp2kjWPo/AtqSxYY=; b=N4fO2Swrq3xqtJUhi08rxICcOAEPEkFwSLlTJvYdYq9IPf7PVQNXySwXvBeVHPhKtF 81YyH3lb+5bPV7AX29GT9mq/7PQ9OQgHc+RPhT3so8P3B+lPCkxesY5em26wCYtctbnO a66VtmOC5v9NJnoHJrrEomE+7wC2DLymR9PMwZGrhR3n/c8hd0pEm03xotKS/wjh1214 JIOU/5Aek5zyuK9k25R42Nm+EzlYyfvCOXlllevRwyLk/IEP1eDbkGUO1IZKT7a0+dKz U4gQb8ZLgLV24hy8w0aGaRxjdVmaBQFk2/fR54TVzEjnulPIz44Mm3RICFh/Y8AaRrkJ vGCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kdkcGfyiI4qEGDjR65U9kIW9WP0Rp2kjWPo/AtqSxYY=; b=XJ//GI7ia2bD0QwRLAxn1MS6JYir8sZJe2ypRW96utb4uOsvnro59vTJ9US9drELVH VpIFzJOf6nQ57eVmkZmv2d+mVbJ1ynXD9/DZNZi0tC5qraqjARDNZEQ20TJ51IFj4stN ceZY3YPbwojHdzqhgJqfPlUEhY5IzJyYrLhgzsutTFXpUX2C0OzKSSwlpiXWCt5s34Pc rgYOjlWwb0S26j7hfWKDmcHwF6mRxGz5aB3wFA7SrzeCCkR0o78fb/osZcMkzXA5WS1S fTGq+qatTdRxUQH2SO87bHK3v2uTQ6SLVdUkLQCUOq15EqQdrHfX0djFHrUXNxdPEUdB pfHQ== X-Gm-Message-State: APjAAAXCShkt0UrflixRrKRMtER7xV2/fxSWwNPjjrz5/EHWdeRHprFa Fbgtpn/PdwlgW8BDagmecL36sw== X-Google-Smtp-Source: APXvYqxZyOUWujqy8fbLhBPhUPib77/Q0H+j3NMy6GkQG2zkT49U4p54bIUpRhAGaDN6LbyWSeBW3g== X-Received: by 2002:a5d:4f8a:: with SMTP id d10mr29699566wru.276.1570555064833; Tue, 08 Oct 2019 10:17:44 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 01/21] ptimer: Rename ptimer_init() to ptimer_init_with_bh() Date: Tue, 8 Oct 2019 18:17:20 +0100 Message-Id: <20191008171740.9679-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191008171740.9679-1-peter.maydell@linaro.org> References: <20191008171740.9679-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::429 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Paolo Bonzini Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Currently the ptimer design uses a QEMU bottom-half as its mechanism for calling back into the device model using the ptimer when the timer has expired. Unfortunately this design is fatally flawed, because it means that there is a lag between the ptimer updating its own state and the device callback function updating device state, and guest accesses to device registers between the two can return inconsistent device state. We want to replace the bottom-half design with one where the guest device's callback is called either immediately (when the ptimer triggers by timeout) or when the device model code closes a transaction-begin/end section (when the ptimer triggers because the device model changed the ptimer's count value or other state). As the first step, rename ptimer_init() to ptimer_init_with_bh(), to free up the ptimer_init() name for the new API. We can then convert all the ptimer users away from ptimer_init_with_bh() before removing it entirely. (Commit created with git grep -l ptimer_init | xargs sed -i -e 's/ptimer_init/ptimer_init_with_= bh/' and three overlong lines folded by hand.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/hw/ptimer.h | 11 ++++++----- hw/arm/musicpal.c | 2 +- hw/core/ptimer.c | 2 +- hw/dma/xilinx_axidma.c | 2 +- hw/m68k/mcf5206.c | 2 +- hw/m68k/mcf5208.c | 2 +- hw/net/fsl_etsec/etsec.c | 2 +- hw/net/lan9118.c | 2 +- hw/timer/allwinner-a10-pit.c | 2 +- hw/timer/altera_timer.c | 2 +- hw/timer/arm_mptimer.c | 6 +++--- hw/timer/arm_timer.c | 2 +- hw/timer/cmsdk-apb-dualtimer.c | 2 +- hw/timer/cmsdk-apb-timer.c | 2 +- hw/timer/digic-timer.c | 2 +- hw/timer/etraxfs_timer.c | 6 +++--- hw/timer/exynos4210_mct.c | 7 ++++--- hw/timer/exynos4210_pwm.c | 2 +- hw/timer/exynos4210_rtc.c | 4 ++-- hw/timer/grlib_gptimer.c | 2 +- hw/timer/imx_epit.c | 4 ++-- hw/timer/imx_gpt.c | 2 +- hw/timer/lm32_timer.c | 2 +- hw/timer/milkymist-sysctl.c | 4 ++-- hw/timer/mss-timer.c | 2 +- hw/timer/puv3_ost.c | 2 +- hw/timer/sh_timer.c | 2 +- hw/timer/slavio_timer.c | 2 +- hw/timer/xilinx_timer.c | 2 +- hw/watchdog/cmsdk-apb-watchdog.c | 2 +- tests/ptimer-test.c | 22 +++++++++++----------- 31 files changed, 56 insertions(+), 54 deletions(-) diff --git a/include/hw/ptimer.h b/include/hw/ptimer.h index 9c770552290..2fb9ba1915e 100644 --- a/include/hw/ptimer.h +++ b/include/hw/ptimer.h @@ -72,7 +72,7 @@ * ptimer_set_count() or ptimer_set_limit() will not trigger the timer * (though it will cause a reload). Only a counter decrement to "0" * will cause a trigger. Not compatible with NO_IMMEDIATE_TRIGGER; - * ptimer_init() will assert() that you don't set both. + * ptimer_init_with_bh() will assert() that you don't set both. */ #define PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT (1 << 5) =20 @@ -81,7 +81,7 @@ typedef struct ptimer_state ptimer_state; typedef void (*ptimer_cb)(void *opaque); =20 /** - * ptimer_init - Allocate and return a new ptimer + * ptimer_init_with_bh - Allocate and return a new ptimer * @bh: QEMU bottom half which is run on timer expiry * @policy: PTIMER_POLICY_* bits specifying behaviour * @@ -89,13 +89,13 @@ typedef void (*ptimer_cb)(void *opaque); * The ptimer takes ownership of @bh and will delete it * when the ptimer is eventually freed. */ -ptimer_state *ptimer_init(QEMUBH *bh, uint8_t policy_mask); +ptimer_state *ptimer_init_with_bh(QEMUBH *bh, uint8_t policy_mask); =20 /** * ptimer_free - Free a ptimer * @s: timer to free * - * Free a ptimer created using ptimer_init() (including + * Free a ptimer created using ptimer_init_with_bh() (including * deleting the bottom half which it is using). */ void ptimer_free(ptimer_state *s); @@ -178,7 +178,8 @@ void ptimer_set_count(ptimer_state *s, uint64_t count); * @oneshot: non-zero if this timer should only count down once * * Start a ptimer counting down; when it reaches zero the bottom half - * passed to ptimer_init() will be invoked. If the @oneshot argument is ze= ro, + * passed to ptimer_init_with_bh() will be invoked. + * If the @oneshot argument is zero, * the counter value will then be reloaded from the limit and it will * start counting down again. If @oneshot is non-zero, then the counter * will disable itself when it reaches zero. diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c index 246cbb13363..b3624d5e280 100644 --- a/hw/arm/musicpal.c +++ b/hw/arm/musicpal.c @@ -849,7 +849,7 @@ static void mv88w8618_timer_init(SysBusDevice *dev, mv8= 8w8618_timer_state *s, s->freq =3D freq; =20 bh =3D qemu_bh_new(mv88w8618_timer_tick, s); - s->ptimer =3D ptimer_init(bh, PTIMER_POLICY_DEFAULT); + s->ptimer =3D ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); } =20 static uint64_t mv88w8618_pit_read(void *opaque, hwaddr offset, diff --git a/hw/core/ptimer.c b/hw/core/ptimer.c index d58e2dfdb08..f0d3ce11398 100644 --- a/hw/core/ptimer.c +++ b/hw/core/ptimer.c @@ -358,7 +358,7 @@ const VMStateDescription vmstate_ptimer =3D { } }; =20 -ptimer_state *ptimer_init(QEMUBH *bh, uint8_t policy_mask) +ptimer_state *ptimer_init_with_bh(QEMUBH *bh, uint8_t policy_mask) { ptimer_state *s; =20 diff --git a/hw/dma/xilinx_axidma.c b/hw/dma/xilinx_axidma.c index a254275b64e..e035d1f7504 100644 --- a/hw/dma/xilinx_axidma.c +++ b/hw/dma/xilinx_axidma.c @@ -552,7 +552,7 @@ static void xilinx_axidma_realize(DeviceState *dev, Err= or **errp) =20 st->nr =3D i; st->bh =3D qemu_bh_new(timer_hit, st); - st->ptimer =3D ptimer_init(st->bh, PTIMER_POLICY_DEFAULT); + st->ptimer =3D ptimer_init_with_bh(st->bh, PTIMER_POLICY_DEFAULT); ptimer_set_freq(st->ptimer, s->freqhz); } return; diff --git a/hw/m68k/mcf5206.c b/hw/m68k/mcf5206.c index a9c2c95b0d1..a49096367cb 100644 --- a/hw/m68k/mcf5206.c +++ b/hw/m68k/mcf5206.c @@ -141,7 +141,7 @@ static m5206_timer_state *m5206_timer_init(qemu_irq irq) =20 s =3D g_new0(m5206_timer_state, 1); bh =3D qemu_bh_new(m5206_timer_trigger, s); - s->timer =3D ptimer_init(bh, PTIMER_POLICY_DEFAULT); + s->timer =3D ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); s->irq =3D irq; m5206_timer_reset(s); return s; diff --git a/hw/m68k/mcf5208.c b/hw/m68k/mcf5208.c index 012710d057d..45c28b75a17 100644 --- a/hw/m68k/mcf5208.c +++ b/hw/m68k/mcf5208.c @@ -192,7 +192,7 @@ static void mcf5208_sys_init(MemoryRegion *address_spac= e, qemu_irq *pic) for (i =3D 0; i < 2; i++) { s =3D g_new0(m5208_timer_state, 1); bh =3D qemu_bh_new(m5208_timer_trigger, s); - s->timer =3D ptimer_init(bh, PTIMER_POLICY_DEFAULT); + s->timer =3D ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); memory_region_init_io(&s->iomem, NULL, &m5208_timer_ops, s, "m5208-timer", 0x00004000); memory_region_add_subregion(address_space, 0xfc080000 + 0x4000 * i, diff --git a/hw/net/fsl_etsec/etsec.c b/hw/net/fsl_etsec/etsec.c index 8451c17fb8f..d9b3e8c691e 100644 --- a/hw/net/fsl_etsec/etsec.c +++ b/hw/net/fsl_etsec/etsec.c @@ -393,7 +393,7 @@ static void etsec_realize(DeviceState *dev, Error **err= p) =20 =20 etsec->bh =3D qemu_bh_new(etsec_timer_hit, etsec); - etsec->ptimer =3D ptimer_init(etsec->bh, PTIMER_POLICY_DEFAULT); + etsec->ptimer =3D ptimer_init_with_bh(etsec->bh, PTIMER_POLICY_DEFAULT= ); ptimer_set_freq(etsec->ptimer, 100); } =20 diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c index 8bba2a80568..0ea51433dca 100644 --- a/hw/net/lan9118.c +++ b/hw/net/lan9118.c @@ -1350,7 +1350,7 @@ static void lan9118_realize(DeviceState *dev, Error *= *errp) s->txp =3D &s->tx_packet; =20 bh =3D qemu_bh_new(lan9118_tick, s); - s->timer =3D ptimer_init(bh, PTIMER_POLICY_DEFAULT); + s->timer =3D ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); ptimer_set_freq(s->timer, 10000); ptimer_set_limit(s->timer, 0xffff, 1); } diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index ca5a9050591..28d055e42f3 100644 --- a/hw/timer/allwinner-a10-pit.c +++ b/hw/timer/allwinner-a10-pit.c @@ -271,7 +271,7 @@ static void a10_pit_init(Object *obj) tc->container =3D s; tc->index =3D i; bh[i] =3D qemu_bh_new(a10_pit_timer_cb, tc); - s->timer[i] =3D ptimer_init(bh[i], PTIMER_POLICY_DEFAULT); + s->timer[i] =3D ptimer_init_with_bh(bh[i], PTIMER_POLICY_DEFAULT); } } =20 diff --git a/hw/timer/altera_timer.c b/hw/timer/altera_timer.c index 936b31311d2..ee32e0ec1ff 100644 --- a/hw/timer/altera_timer.c +++ b/hw/timer/altera_timer.c @@ -184,7 +184,7 @@ static void altera_timer_realize(DeviceState *dev, Erro= r **errp) } =20 t->bh =3D qemu_bh_new(timer_hit, t); - t->ptimer =3D ptimer_init(t->bh, PTIMER_POLICY_DEFAULT); + t->ptimer =3D ptimer_init_with_bh(t->bh, PTIMER_POLICY_DEFAULT); ptimer_set_freq(t->ptimer, t->freq_hz); =20 memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t, diff --git a/hw/timer/arm_mptimer.c b/hw/timer/arm_mptimer.c index 9f63abef10e..2a54a011431 100644 --- a/hw/timer/arm_mptimer.c +++ b/hw/timer/arm_mptimer.c @@ -228,7 +228,7 @@ static void arm_mptimer_reset(DeviceState *dev) } } =20 -static void arm_mptimer_init(Object *obj) +static void arm_mptimer_init_with_bh(Object *obj) { ARMMPTimerState *s =3D ARM_MPTIMER(obj); =20 @@ -261,7 +261,7 @@ static void arm_mptimer_realize(DeviceState *dev, Error= **errp) for (i =3D 0; i < s->num_cpu; i++) { TimerBlock *tb =3D &s->timerblock[i]; QEMUBH *bh =3D qemu_bh_new(timerblock_tick, tb); - tb->timer =3D ptimer_init(bh, PTIMER_POLICY); + tb->timer =3D ptimer_init_with_bh(bh, PTIMER_POLICY); sysbus_init_irq(sbd, &tb->irq); memory_region_init_io(&tb->iomem, OBJECT(s), &timerblock_ops, tb, "arm_mptimer_timerblock", 0x20); @@ -311,7 +311,7 @@ static const TypeInfo arm_mptimer_info =3D { .name =3D TYPE_ARM_MPTIMER, .parent =3D TYPE_SYS_BUS_DEVICE, .instance_size =3D sizeof(ARMMPTimerState), - .instance_init =3D arm_mptimer_init, + .instance_init =3D arm_mptimer_init_with_bh, .class_init =3D arm_mptimer_class_init, }; =20 diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c index 283ae1e74a9..848fbcb0e25 100644 --- a/hw/timer/arm_timer.c +++ b/hw/timer/arm_timer.c @@ -177,7 +177,7 @@ static arm_timer_state *arm_timer_init(uint32_t freq) s->control =3D TIMER_CTRL_IE; =20 bh =3D qemu_bh_new(arm_timer_tick, s); - s->timer =3D ptimer_init(bh, PTIMER_POLICY_DEFAULT); + s->timer =3D ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); vmstate_register(NULL, -1, &vmstate_arm_timer, s); return s; } diff --git a/hw/timer/cmsdk-apb-dualtimer.c b/hw/timer/cmsdk-apb-dualtimer.c index 5e2352dd326..44d23c80364 100644 --- a/hw/timer/cmsdk-apb-dualtimer.c +++ b/hw/timer/cmsdk-apb-dualtimer.c @@ -453,7 +453,7 @@ static void cmsdk_apb_dualtimer_realize(DeviceState *de= v, Error **errp) QEMUBH *bh =3D qemu_bh_new(cmsdk_dualtimermod_tick, m); =20 m->parent =3D s; - m->timer =3D ptimer_init(bh, + m->timer =3D ptimer_init_with_bh(bh, PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD | PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT | PTIMER_POLICY_NO_IMMEDIATE_RELOAD | diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c index c83e26566a9..c9ce9770cef 100644 --- a/hw/timer/cmsdk-apb-timer.c +++ b/hw/timer/cmsdk-apb-timer.c @@ -218,7 +218,7 @@ static void cmsdk_apb_timer_realize(DeviceState *dev, E= rror **errp) } =20 bh =3D qemu_bh_new(cmsdk_apb_timer_tick, s); - s->timer =3D ptimer_init(bh, + s->timer =3D ptimer_init_with_bh(bh, PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD | PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT | PTIMER_POLICY_NO_IMMEDIATE_RELOAD | diff --git a/hw/timer/digic-timer.c b/hw/timer/digic-timer.c index 021c4ef714f..b111e1fe643 100644 --- a/hw/timer/digic-timer.c +++ b/hw/timer/digic-timer.c @@ -129,7 +129,7 @@ static void digic_timer_init(Object *obj) { DigicTimerState *s =3D DIGIC_TIMER(obj); =20 - s->ptimer =3D ptimer_init(NULL, PTIMER_POLICY_DEFAULT); + s->ptimer =3D ptimer_init_with_bh(NULL, PTIMER_POLICY_DEFAULT); =20 /* * FIXME: there is no documentation on Digic timer diff --git a/hw/timer/etraxfs_timer.c b/hw/timer/etraxfs_timer.c index d62025b8797..ab27fe1895b 100644 --- a/hw/timer/etraxfs_timer.c +++ b/hw/timer/etraxfs_timer.c @@ -328,9 +328,9 @@ static void etraxfs_timer_realize(DeviceState *dev, Err= or **errp) t->bh_t0 =3D qemu_bh_new(timer0_hit, t); t->bh_t1 =3D qemu_bh_new(timer1_hit, t); t->bh_wd =3D qemu_bh_new(watchdog_hit, t); - t->ptimer_t0 =3D ptimer_init(t->bh_t0, PTIMER_POLICY_DEFAULT); - t->ptimer_t1 =3D ptimer_init(t->bh_t1, PTIMER_POLICY_DEFAULT); - t->ptimer_wd =3D ptimer_init(t->bh_wd, PTIMER_POLICY_DEFAULT); + t->ptimer_t0 =3D ptimer_init_with_bh(t->bh_t0, PTIMER_POLICY_DEFAULT); + t->ptimer_t1 =3D ptimer_init_with_bh(t->bh_t1, PTIMER_POLICY_DEFAULT); + t->ptimer_wd =3D ptimer_init_with_bh(t->bh_wd, PTIMER_POLICY_DEFAULT); =20 sysbus_init_irq(sbd, &t->irq); sysbus_init_irq(sbd, &t->nmi); diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c index 77b9af05f41..9f2e8dd0a42 100644 --- a/hw/timer/exynos4210_mct.c +++ b/hw/timer/exynos4210_mct.c @@ -1429,7 +1429,7 @@ static void exynos4210_mct_init(Object *obj) =20 /* Global timer */ bh[0] =3D qemu_bh_new(exynos4210_gfrc_event, s); - s->g_timer.ptimer_frc =3D ptimer_init(bh[0], PTIMER_POLICY_DEFAULT); + s->g_timer.ptimer_frc =3D ptimer_init_with_bh(bh[0], PTIMER_POLICY_DEF= AULT); memset(&s->g_timer.reg, 0, sizeof(struct gregs)); =20 /* Local timers */ @@ -1437,8 +1437,9 @@ static void exynos4210_mct_init(Object *obj) bh[0] =3D qemu_bh_new(exynos4210_ltick_event, &s->l_timer[i]); bh[1] =3D qemu_bh_new(exynos4210_lfrc_event, &s->l_timer[i]); s->l_timer[i].tick_timer.ptimer_tick =3D - ptimer_init(bh[0], PTIMER_POLICY_DEFAUL= T); - s->l_timer[i].ptimer_frc =3D ptimer_init(bh[1], PTIMER_POLICY_DEFA= ULT); + ptimer_init_with_bh(bh[0], PTIMER_POLICY_DEFAULT); + s->l_timer[i].ptimer_frc =3D + ptimer_init_with_bh(bh[1], PTIMER_POLICY_DEFAULT); s->l_timer[i].id =3D i; } =20 diff --git a/hw/timer/exynos4210_pwm.c b/hw/timer/exynos4210_pwm.c index b7fad2ad449..aa5dca68ef7 100644 --- a/hw/timer/exynos4210_pwm.c +++ b/hw/timer/exynos4210_pwm.c @@ -393,7 +393,7 @@ static void exynos4210_pwm_init(Object *obj) for (i =3D 0; i < EXYNOS4210_PWM_TIMERS_NUM; i++) { bh =3D qemu_bh_new(exynos4210_pwm_tick, &s->timer[i]); sysbus_init_irq(dev, &s->timer[i].irq); - s->timer[i].ptimer =3D ptimer_init(bh, PTIMER_POLICY_DEFAULT); + s->timer[i].ptimer =3D ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAU= LT); s->timer[i].id =3D i; s->timer[i].parent =3D s; } diff --git a/hw/timer/exynos4210_rtc.c b/hw/timer/exynos4210_rtc.c index ea689042297..d5d7c91fb15 100644 --- a/hw/timer/exynos4210_rtc.c +++ b/hw/timer/exynos4210_rtc.c @@ -558,12 +558,12 @@ static void exynos4210_rtc_init(Object *obj) QEMUBH *bh; =20 bh =3D qemu_bh_new(exynos4210_rtc_tick, s); - s->ptimer =3D ptimer_init(bh, PTIMER_POLICY_DEFAULT); + s->ptimer =3D ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); ptimer_set_freq(s->ptimer, RTC_BASE_FREQ); exynos4210_rtc_update_freq(s, 0); =20 bh =3D qemu_bh_new(exynos4210_rtc_1Hz_tick, s); - s->ptimer_1Hz =3D ptimer_init(bh, PTIMER_POLICY_DEFAULT); + s->ptimer_1Hz =3D ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); ptimer_set_freq(s->ptimer_1Hz, RTC_BASE_FREQ); =20 sysbus_init_irq(dev, &s->alm_irq); diff --git a/hw/timer/grlib_gptimer.c b/hw/timer/grlib_gptimer.c index 32dbf870d4b..bb09268ea14 100644 --- a/hw/timer/grlib_gptimer.c +++ b/hw/timer/grlib_gptimer.c @@ -366,7 +366,7 @@ static void grlib_gptimer_realize(DeviceState *dev, Err= or **errp) =20 timer->unit =3D unit; timer->bh =3D qemu_bh_new(grlib_gptimer_hit, timer); - timer->ptimer =3D ptimer_init(timer->bh, PTIMER_POLICY_DEFAULT); + timer->ptimer =3D ptimer_init_with_bh(timer->bh, PTIMER_POLICY_DEF= AULT); timer->id =3D i; =20 /* One IRQ line for each timer */ diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c index f54e059910b..39810ac8b03 100644 --- a/hw/timer/imx_epit.c +++ b/hw/timer/imx_epit.c @@ -317,10 +317,10 @@ static void imx_epit_realize(DeviceState *dev, Error = **errp) 0x00001000); sysbus_init_mmio(sbd, &s->iomem); =20 - s->timer_reload =3D ptimer_init(NULL, PTIMER_POLICY_DEFAULT); + s->timer_reload =3D ptimer_init_with_bh(NULL, PTIMER_POLICY_DEFAULT); =20 bh =3D qemu_bh_new(imx_epit_cmp, s); - s->timer_cmp =3D ptimer_init(bh, PTIMER_POLICY_DEFAULT); + s->timer_cmp =3D ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); } =20 static void imx_epit_class_init(ObjectClass *klass, void *data) diff --git a/hw/timer/imx_gpt.c b/hw/timer/imx_gpt.c index 49a441f4517..c535d191292 100644 --- a/hw/timer/imx_gpt.c +++ b/hw/timer/imx_gpt.c @@ -492,7 +492,7 @@ static void imx_gpt_realize(DeviceState *dev, Error **e= rrp) sysbus_init_mmio(sbd, &s->iomem); =20 bh =3D qemu_bh_new(imx_gpt_timeout, s); - s->timer =3D ptimer_init(bh, PTIMER_POLICY_DEFAULT); + s->timer =3D ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); } =20 static void imx_gpt_class_init(ObjectClass *klass, void *data) diff --git a/hw/timer/lm32_timer.c b/hw/timer/lm32_timer.c index ac3edaff4f8..f79f818d22c 100644 --- a/hw/timer/lm32_timer.c +++ b/hw/timer/lm32_timer.c @@ -187,7 +187,7 @@ static void lm32_timer_init(Object *obj) sysbus_init_irq(dev, &s->irq); =20 s->bh =3D qemu_bh_new(timer_hit, s); - s->ptimer =3D ptimer_init(s->bh, PTIMER_POLICY_DEFAULT); + s->ptimer =3D ptimer_init_with_bh(s->bh, PTIMER_POLICY_DEFAULT); =20 memory_region_init_io(&s->iomem, obj, &timer_ops, s, "timer", R_MAX * 4); diff --git a/hw/timer/milkymist-sysctl.c b/hw/timer/milkymist-sysctl.c index 958350767ae..aeba889bba4 100644 --- a/hw/timer/milkymist-sysctl.c +++ b/hw/timer/milkymist-sysctl.c @@ -285,8 +285,8 @@ static void milkymist_sysctl_init(Object *obj) =20 s->bh0 =3D qemu_bh_new(timer0_hit, s); s->bh1 =3D qemu_bh_new(timer1_hit, s); - s->ptimer0 =3D ptimer_init(s->bh0, PTIMER_POLICY_DEFAULT); - s->ptimer1 =3D ptimer_init(s->bh1, PTIMER_POLICY_DEFAULT); + s->ptimer0 =3D ptimer_init_with_bh(s->bh0, PTIMER_POLICY_DEFAULT); + s->ptimer1 =3D ptimer_init_with_bh(s->bh1, PTIMER_POLICY_DEFAULT); =20 memory_region_init_io(&s->regs_region, obj, &sysctl_mmio_ops, s, "milkymist-sysctl", R_MAX * 4); diff --git a/hw/timer/mss-timer.c b/hw/timer/mss-timer.c index 45f1cf42f9e..a34c2402b00 100644 --- a/hw/timer/mss-timer.c +++ b/hw/timer/mss-timer.c @@ -229,7 +229,7 @@ static void mss_timer_init(Object *obj) struct Msf2Timer *st =3D &t->timers[i]; =20 st->bh =3D qemu_bh_new(timer_hit, st); - st->ptimer =3D ptimer_init(st->bh, PTIMER_POLICY_DEFAULT); + st->ptimer =3D ptimer_init_with_bh(st->bh, PTIMER_POLICY_DEFAULT); ptimer_set_freq(st->ptimer, t->freq_hz); sysbus_init_irq(SYS_BUS_DEVICE(obj), &st->irq); } diff --git a/hw/timer/puv3_ost.c b/hw/timer/puv3_ost.c index 6fe370049b5..0898da5ce97 100644 --- a/hw/timer/puv3_ost.c +++ b/hw/timer/puv3_ost.c @@ -129,7 +129,7 @@ static void puv3_ost_realize(DeviceState *dev, Error **= errp) sysbus_init_irq(sbd, &s->irq); =20 s->bh =3D qemu_bh_new(puv3_ost_tick, s); - s->ptimer =3D ptimer_init(s->bh, PTIMER_POLICY_DEFAULT); + s->ptimer =3D ptimer_init_with_bh(s->bh, PTIMER_POLICY_DEFAULT); ptimer_set_freq(s->ptimer, 50 * 1000 * 1000); =20 memory_region_init_io(&s->iomem, OBJECT(s), &puv3_ost_ops, s, "puv3_os= t", diff --git a/hw/timer/sh_timer.c b/hw/timer/sh_timer.c index adcc0c138e7..48a81b4dc79 100644 --- a/hw/timer/sh_timer.c +++ b/hw/timer/sh_timer.c @@ -204,7 +204,7 @@ static void *sh_timer_init(uint32_t freq, int feat, qem= u_irq irq) s->irq =3D irq; =20 bh =3D qemu_bh_new(sh_timer_tick, s); - s->timer =3D ptimer_init(bh, PTIMER_POLICY_DEFAULT); + s->timer =3D ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); =20 sh_timer_write(s, OFFSET_TCOR >> 2, s->tcor); sh_timer_write(s, OFFSET_TCNT >> 2, s->tcnt); diff --git a/hw/timer/slavio_timer.c b/hw/timer/slavio_timer.c index 38fd32b62a0..692d213897d 100644 --- a/hw/timer/slavio_timer.c +++ b/hw/timer/slavio_timer.c @@ -393,7 +393,7 @@ static void slavio_timer_init(Object *obj) tc->timer_index =3D i; =20 bh =3D qemu_bh_new(slavio_timer_irq, tc); - s->cputimer[i].timer =3D ptimer_init(bh, PTIMER_POLICY_DEFAULT); + s->cputimer[i].timer =3D ptimer_init_with_bh(bh, PTIMER_POLICY_DEF= AULT); ptimer_set_period(s->cputimer[i].timer, TIMER_PERIOD); =20 size =3D i =3D=3D 0 ? SYS_TIMER_SIZE : CPU_TIMER_SIZE; diff --git a/hw/timer/xilinx_timer.c b/hw/timer/xilinx_timer.c index 355518232cd..92dbff304d9 100644 --- a/hw/timer/xilinx_timer.c +++ b/hw/timer/xilinx_timer.c @@ -221,7 +221,7 @@ static void xilinx_timer_realize(DeviceState *dev, Erro= r **errp) xt->parent =3D t; xt->nr =3D i; xt->bh =3D qemu_bh_new(timer_hit, xt); - xt->ptimer =3D ptimer_init(xt->bh, PTIMER_POLICY_DEFAULT); + xt->ptimer =3D ptimer_init_with_bh(xt->bh, PTIMER_POLICY_DEFAULT); ptimer_set_freq(xt->ptimer, t->freq_hz); } =20 diff --git a/hw/watchdog/cmsdk-apb-watchdog.c b/hw/watchdog/cmsdk-apb-watch= dog.c index 6bf43f943fb..e42c3ebd29d 100644 --- a/hw/watchdog/cmsdk-apb-watchdog.c +++ b/hw/watchdog/cmsdk-apb-watchdog.c @@ -329,7 +329,7 @@ static void cmsdk_apb_watchdog_realize(DeviceState *dev= , Error **errp) } =20 bh =3D qemu_bh_new(cmsdk_apb_watchdog_tick, s); - s->timer =3D ptimer_init(bh, + s->timer =3D ptimer_init_with_bh(bh, PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD | PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT | PTIMER_POLICY_NO_IMMEDIATE_RELOAD | diff --git a/tests/ptimer-test.c b/tests/ptimer-test.c index 5b20e91599e..a3c82d1d147 100644 --- a/tests/ptimer-test.c +++ b/tests/ptimer-test.c @@ -68,7 +68,7 @@ static void check_set_count(gconstpointer arg) { const uint8_t *policy =3D arg; QEMUBH *bh =3D qemu_bh_new(ptimer_trigger, NULL); - ptimer_state *ptimer =3D ptimer_init(bh, *policy); + ptimer_state *ptimer =3D ptimer_init_with_bh(bh, *policy); =20 triggered =3D false; =20 @@ -82,7 +82,7 @@ static void check_set_limit(gconstpointer arg) { const uint8_t *policy =3D arg; QEMUBH *bh =3D qemu_bh_new(ptimer_trigger, NULL); - ptimer_state *ptimer =3D ptimer_init(bh, *policy); + ptimer_state *ptimer =3D ptimer_init_with_bh(bh, *policy); =20 triggered =3D false; =20 @@ -102,7 +102,7 @@ static void check_oneshot(gconstpointer arg) { const uint8_t *policy =3D arg; QEMUBH *bh =3D qemu_bh_new(ptimer_trigger, NULL); - ptimer_state *ptimer =3D ptimer_init(bh, *policy); + ptimer_state *ptimer =3D ptimer_init_with_bh(bh, *policy); bool no_round_down =3D (*policy & PTIMER_POLICY_NO_COUNTER_ROUND_DOWN); =20 triggered =3D false; @@ -205,7 +205,7 @@ static void check_periodic(gconstpointer arg) { const uint8_t *policy =3D arg; QEMUBH *bh =3D qemu_bh_new(ptimer_trigger, NULL); - ptimer_state *ptimer =3D ptimer_init(bh, *policy); + ptimer_state *ptimer =3D ptimer_init_with_bh(bh, *policy); bool wrap_policy =3D (*policy & PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD); bool no_immediate_trigger =3D (*policy & PTIMER_POLICY_NO_IMMEDIATE_TR= IGGER); bool no_immediate_reload =3D (*policy & PTIMER_POLICY_NO_IMMEDIATE_REL= OAD); @@ -373,7 +373,7 @@ static void check_on_the_fly_mode_change(gconstpointer = arg) { const uint8_t *policy =3D arg; QEMUBH *bh =3D qemu_bh_new(ptimer_trigger, NULL); - ptimer_state *ptimer =3D ptimer_init(bh, *policy); + ptimer_state *ptimer =3D ptimer_init_with_bh(bh, *policy); bool wrap_policy =3D (*policy & PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD); bool no_round_down =3D (*policy & PTIMER_POLICY_NO_COUNTER_ROUND_DOWN); =20 @@ -420,7 +420,7 @@ static void check_on_the_fly_period_change(gconstpointe= r arg) { const uint8_t *policy =3D arg; QEMUBH *bh =3D qemu_bh_new(ptimer_trigger, NULL); - ptimer_state *ptimer =3D ptimer_init(bh, *policy); + ptimer_state *ptimer =3D ptimer_init_with_bh(bh, *policy); bool no_round_down =3D (*policy & PTIMER_POLICY_NO_COUNTER_ROUND_DOWN); =20 triggered =3D false; @@ -453,7 +453,7 @@ static void check_on_the_fly_freq_change(gconstpointer = arg) { const uint8_t *policy =3D arg; QEMUBH *bh =3D qemu_bh_new(ptimer_trigger, NULL); - ptimer_state *ptimer =3D ptimer_init(bh, *policy); + ptimer_state *ptimer =3D ptimer_init_with_bh(bh, *policy); bool no_round_down =3D (*policy & PTIMER_POLICY_NO_COUNTER_ROUND_DOWN); =20 triggered =3D false; @@ -486,7 +486,7 @@ static void check_run_with_period_0(gconstpointer arg) { const uint8_t *policy =3D arg; QEMUBH *bh =3D qemu_bh_new(ptimer_trigger, NULL); - ptimer_state *ptimer =3D ptimer_init(bh, *policy); + ptimer_state *ptimer =3D ptimer_init_with_bh(bh, *policy); =20 triggered =3D false; =20 @@ -504,7 +504,7 @@ static void check_run_with_delta_0(gconstpointer arg) { const uint8_t *policy =3D arg; QEMUBH *bh =3D qemu_bh_new(ptimer_trigger, NULL); - ptimer_state *ptimer =3D ptimer_init(bh, *policy); + ptimer_state *ptimer =3D ptimer_init_with_bh(bh, *policy); bool wrap_policy =3D (*policy & PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD); bool no_immediate_trigger =3D (*policy & PTIMER_POLICY_NO_IMMEDIATE_TR= IGGER); bool no_immediate_reload =3D (*policy & PTIMER_POLICY_NO_IMMEDIATE_REL= OAD); @@ -610,7 +610,7 @@ static void check_periodic_with_load_0(gconstpointer ar= g) { const uint8_t *policy =3D arg; QEMUBH *bh =3D qemu_bh_new(ptimer_trigger, NULL); - ptimer_state *ptimer =3D ptimer_init(bh, *policy); + ptimer_state *ptimer =3D ptimer_init_with_bh(bh, *policy); bool continuous_trigger =3D (*policy & PTIMER_POLICY_CONTINUOUS_TRIGGE= R); bool no_immediate_trigger =3D (*policy & PTIMER_POLICY_NO_IMMEDIATE_TR= IGGER); bool trig_only_on_dec =3D (*policy & PTIMER_POLICY_TRIGGER_ONLY_ON_DEC= REMENT); @@ -670,7 +670,7 @@ static void check_oneshot_with_load_0(gconstpointer arg) { const uint8_t *policy =3D arg; QEMUBH *bh =3D qemu_bh_new(ptimer_trigger, NULL); - ptimer_state *ptimer =3D ptimer_init(bh, *policy); + ptimer_state *ptimer =3D ptimer_init_with_bh(bh, *policy); bool no_immediate_trigger =3D (*policy & PTIMER_POLICY_NO_IMMEDIATE_TR= IGGER); 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id z9sm19135541wrl.35.2019.10.08.10.17.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Oct 2019 10:17:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3TNOdz92e/qBT6KrqIxG70SsX0V9K71FFrgsUzEswP0=; b=RqDnjTInbiI1VNGzi7gMr2x6o6AMcFW6+sZ5sQ2BRTqI5CA89bPcuspRR71MuV7xs+ gL9bI+vim46pmuWe1UTEIvkz/A3CuX6REOXMacQCBaITIRfGhwEYLegIrDK3xexnROi6 pWUhGnRRgG9WDfGIXLHAUeMXvq+RpWD0Bm6G8MKZ95I1KWMhZQnJx900A/QmfDwEmEF5 uaEPbYgw5CRkOXlpy1AI7v9/FAsujlw8PAN+QiTk4UEgoFmj+7kZQyCZaxVajo+BajGE Sfu1gSlwsppwBeZIFYIoY2onxt8COVVOOsUw15UVccvs1QEDU0uu9lOohlYqSWVTPOq7 ylIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3TNOdz92e/qBT6KrqIxG70SsX0V9K71FFrgsUzEswP0=; b=j/KB6iegRg8uWn5m37FdgKOxqTCC3bnLOzkoIELPllnQ1yK/o9qNk/VXi1YIB8F4kC vkcC0yZut2Ec7XA+UMAuByShlH/mdjADCE/ZWnK+D9f5RDf+d40yqTVggPIFG/A0O2bT 5BKdJiB6ErfTQLiPzqFWNj1jlc3374Ge/tKgsW/qcmne8n068T627hlzB+hIOHtF0sH2 jGZeczpjN/MHgTaZo9IetwgpYMkFhSGiUbDt5b9kzFW3v/L76T4BycpTQaU1idAYt/gv NC7kD9/qIwcZex2hx2hGHN+Pnrvldiz/A1MGG5R0c0s87rjzCuJJP4leQmnGwZrWEUwF 7rsA== X-Gm-Message-State: APjAAAUR32ZChN+CfOFDOn/sPiJzCabX2qEfGfjmj9k7gsF6+d1+ytjj TCfUOZEznxGOZJ98qwz5qsj0pw== X-Google-Smtp-Source: APXvYqyZeI91ektFtwepSPY3yaLlUMB73Yaf+7xQEsJXuCnJ27XUgldojTVD8E8H474buk7k/hzuJA== X-Received: by 2002:adf:e610:: with SMTP id p16mr16688388wrm.313.1570555066280; Tue, 08 Oct 2019 10:17:46 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 02/21] ptimer: Provide new transaction-based API Date: Tue, 8 Oct 2019 18:17:21 +0100 Message-Id: <20191008171740.9679-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191008171740.9679-1-peter.maydell@linaro.org> References: <20191008171740.9679-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42d X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Paolo Bonzini Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Provide the new transaction-based API. If a ptimer is created using ptimer_init() rather than ptimer_init_with_bh(), then instead of providing a QEMUBH, it provides a pointer to the callback function directly, and has opted into the transaction API. All calls to functions which modify ptimer state: - ptimer_set_period() - ptimer_set_freq() - ptimer_set_limit() - ptimer_set_count() - ptimer_run() - ptimer_stop() must be between matched calls to ptimer_transaction_begin() and ptimer_transaction_commit(). When ptimer_transaction_commit() is called it will evaluate the state of the timer after all the changes in the transaction, and call the callback if necessary. In the old API the individual update functions generally would call ptimer_trigger() immediately, which would schedule the QEMUBH. In the new API the update functions will instead defer the "set s->next_event and call ptimer_reload()" work to ptimer_transaction_commit(). Because ptimer_trigger() can now immediately call into the device code which may then call other ptimer functions that update ptimer_state fields, we must be more careful in ptimer_reload() not to cache fields from ptimer_state across the ptimer_trigger() call. (This was harmless with the QEMUBH mechanism as the BH would not be invoked until much later.) We use assertions to check that: * the functions modifying ptimer state are not called outside a transaction block * ptimer_transaction_begin() and _commit() calls are paired * the transaction API is not used with a QEMUBH ptimer There is some slight repetition of code: * most of the set functions have similar looking "if s->bh call ptimer_reload, otherwise set s->need_reload" code * ptimer_init() and ptimer_init_with_bh() have similar code We deliberately don't try to avoid this repetition, because it will all be deleted when the QEMUBH version of the API is removed. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- Changes since v1: * ptimer_transaction_begin() now sets need_reload to false * fixed assert condition in ptimer_transaction_begin() * ptimer_transaction_commit() now has a loop to call ptimer_reload() again if the callback function updated the ptimer state such that it needs to trigger again * fixed callback_opaque arg name mismatch in doc comment * don't cache delta, period, etc across ptimer_trigger() call RTH: I know you gave a reviewed-by-with-caveats to v1 of this patch but I feel like there turned out to be enough things needing fixing that I'd rather you looked at v2 afresh. --- include/hw/ptimer.h | 72 +++++++++++++++++++++ hw/core/ptimer.c | 152 +++++++++++++++++++++++++++++++++++++++----- 2 files changed, 209 insertions(+), 15 deletions(-) diff --git a/include/hw/ptimer.h b/include/hw/ptimer.h index 2fb9ba1915e..4c321f65dcb 100644 --- a/include/hw/ptimer.h +++ b/include/hw/ptimer.h @@ -91,6 +91,38 @@ typedef void (*ptimer_cb)(void *opaque); */ ptimer_state *ptimer_init_with_bh(QEMUBH *bh, uint8_t policy_mask); =20 +/** + * ptimer_init - Allocate and return a new ptimer + * @callback: function to call on ptimer expiry + * @callback_opaque: opaque pointer passed to @callback + * @policy: PTIMER_POLICY_* bits specifying behaviour + * + * The ptimer returned must be freed using ptimer_free(). + * + * If a ptimer is created using this API then will use the + * transaction-based API for modifying ptimer state: all calls + * to functions which modify ptimer state: + * - ptimer_set_period() + * - ptimer_set_freq() + * - ptimer_set_limit() + * - ptimer_set_count() + * - ptimer_run() + * - ptimer_stop() + * must be between matched calls to ptimer_transaction_begin() + * and ptimer_transaction_commit(). When ptimer_transaction_commit() + * is called it will evaluate the state of the timer after all the + * changes in the transaction, and call the callback if necessary. + * + * The callback function is always called from within a transaction + * begin/commit block, so the callback should not call the + * ptimer_transaction_begin() function itself. If the callback changes + * the ptimer state such that another ptimer expiry is triggered, then + * the callback will be called a second time after the first call returns. + */ +ptimer_state *ptimer_init(ptimer_cb callback, + void *callback_opaque, + uint8_t policy_mask); + /** * ptimer_free - Free a ptimer * @s: timer to free @@ -100,6 +132,28 @@ ptimer_state *ptimer_init_with_bh(QEMUBH *bh, uint8_t = policy_mask); */ void ptimer_free(ptimer_state *s); =20 +/** + * ptimer_transaction_begin() - Start a ptimer modification transaction + * + * This function must be called before making any calls to functions + * which modify the ptimer's state (see the ptimer_init() documentation + * for a list of these), and must always have a matched call to + * ptimer_transaction_commit(). + * It is an error to call this function for a BH-based ptimer; + * attempting to do this will trigger an assert. + */ +void ptimer_transaction_begin(ptimer_state *s); + +/** + * ptimer_transaction_commit() - Commit a ptimer modification transaction + * + * This function must be called after calls to functions which modify + * the ptimer's state, and completes the update of the ptimer. If the + * ptimer state now means that we should trigger the timer expiry + * callback, it will be called directly. + */ +void ptimer_transaction_commit(ptimer_state *s); + /** * ptimer_set_period - Set counter increment interval in nanoseconds * @s: ptimer to configure @@ -108,6 +162,9 @@ void ptimer_free(ptimer_state *s); * Note that if your counter behaviour is specified as having a * particular frequency rather than a period then ptimer_set_freq() * may be more appropriate. + * + * This function will assert if it is called outside a + * ptimer_transaction_begin/commit block, unless this is a bottom-half pti= mer. */ void ptimer_set_period(ptimer_state *s, int64_t period); =20 @@ -121,6 +178,9 @@ void ptimer_set_period(ptimer_state *s, int64_t period); * as setting the frequency then this function is more appropriate, * because it allows specifying an effective period which is * precise to fractions of a nanosecond, avoiding rounding errors. + * + * This function will assert if it is called outside a + * ptimer_transaction_begin/commit block, unless this is a bottom-half pti= mer. */ void ptimer_set_freq(ptimer_state *s, uint32_t freq); =20 @@ -148,6 +208,9 @@ uint64_t ptimer_get_limit(ptimer_state *s); * Set the limit value of the down-counter. The @reload flag can * be used to emulate the behaviour of timers which immediately * reload the counter when their reload register is written to. + * + * This function will assert if it is called outside a + * ptimer_transaction_begin/commit block, unless this is a bottom-half pti= mer. */ void ptimer_set_limit(ptimer_state *s, uint64_t limit, int reload); =20 @@ -169,6 +232,9 @@ uint64_t ptimer_get_count(ptimer_state *s); * Set the value of the down-counter. If the counter is currently * enabled this will arrange for a timer callback at the appropriate * point in the future. + * + * This function will assert if it is called outside a + * ptimer_transaction_begin/commit block, unless this is a bottom-half pti= mer. */ void ptimer_set_count(ptimer_state *s, uint64_t count); =20 @@ -183,6 +249,9 @@ void ptimer_set_count(ptimer_state *s, uint64_t count); * the counter value will then be reloaded from the limit and it will * start counting down again. If @oneshot is non-zero, then the counter * will disable itself when it reaches zero. + * + * This function will assert if it is called outside a + * ptimer_transaction_begin/commit block, unless this is a bottom-half pti= mer. */ void ptimer_run(ptimer_state *s, int oneshot); =20 @@ -195,6 +264,9 @@ void ptimer_run(ptimer_state *s, int oneshot); * * Note that this can cause it to "lose" time, even if it is immediately * restarted. + * + * This function will assert if it is called outside a + * ptimer_transaction_begin/commit block, unless this is a bottom-half pti= mer. */ void ptimer_stop(ptimer_state *s); =20 diff --git a/hw/core/ptimer.c b/hw/core/ptimer.c index f0d3ce11398..7239b8227cc 100644 --- a/hw/core/ptimer.c +++ b/hw/core/ptimer.c @@ -31,6 +31,16 @@ struct ptimer_state uint8_t policy_mask; QEMUBH *bh; QEMUTimer *timer; + ptimer_cb callback; + void *callback_opaque; + /* + * These track whether we're in a transaction block, and if we + * need to do a timer reload when the block finishes. They don't + * need to be migrated because migration can never happen in the + * middle of a transaction block. + */ + bool in_transaction; + bool need_reload; }; =20 /* Use a bottom-half routine to avoid reentrancy issues. */ @@ -39,13 +49,16 @@ static void ptimer_trigger(ptimer_state *s) if (s->bh) { replay_bh_schedule_event(s->bh); } + if (s->callback) { + s->callback(s->callback_opaque); + } } =20 static void ptimer_reload(ptimer_state *s, int delta_adjust) { - uint32_t period_frac =3D s->period_frac; - uint64_t period =3D s->period; - uint64_t delta =3D s->delta; + uint32_t period_frac; + uint64_t period; + uint64_t delta; bool suppress_trigger =3D false; =20 /* @@ -58,11 +71,20 @@ static void ptimer_reload(ptimer_state *s, int delta_ad= just) (s->policy_mask & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT)) { suppress_trigger =3D true; } - if (delta =3D=3D 0 && !(s->policy_mask & PTIMER_POLICY_NO_IMMEDIATE_TR= IGGER) + if (s->delta =3D=3D 0 && !(s->policy_mask & PTIMER_POLICY_NO_IMMEDIATE= _TRIGGER) && !suppress_trigger) { ptimer_trigger(s); } =20 + /* + * Note that ptimer_trigger() might call the device callback function, + * which can then modify timer state, so we must not cache any fields + * from ptimer_state until after we have called it. + */ + delta =3D s->delta; + period =3D s->period; + period_frac =3D s->period_frac; + if (delta =3D=3D 0 && !(s->policy_mask & PTIMER_POLICY_NO_IMMEDIATE_RE= LOAD)) { delta =3D s->delta =3D s->limit; } @@ -136,6 +158,15 @@ static void ptimer_tick(void *opaque) ptimer_state *s =3D (ptimer_state *)opaque; bool trigger =3D true; =20 + /* + * We perform all the tick actions within a begin/commit block + * because the callback function that ptimer_trigger() calls + * might make calls into the ptimer APIs that provoke another + * trigger, and we want that to cause the callback function + * to be called iteratively, not recursively. + */ + ptimer_transaction_begin(s); + if (s->enabled =3D=3D 2) { s->delta =3D 0; s->enabled =3D 0; @@ -164,6 +195,8 @@ static void ptimer_tick(void *opaque) if (trigger) { ptimer_trigger(s); } + + ptimer_transaction_commit(s); } =20 uint64_t ptimer_get_count(ptimer_state *s) @@ -263,10 +296,15 @@ uint64_t ptimer_get_count(ptimer_state *s) =20 void ptimer_set_count(ptimer_state *s, uint64_t count) { + assert(s->in_transaction || !s->callback); s->delta =3D count; if (s->enabled) { - s->next_event =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); - ptimer_reload(s, 0); + if (!s->callback) { + s->next_event =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + ptimer_reload(s, 0); + } else { + s->need_reload =3D true; + } } } =20 @@ -274,6 +312,8 @@ void ptimer_run(ptimer_state *s, int oneshot) { bool was_disabled =3D !s->enabled; =20 + assert(s->in_transaction || !s->callback); + if (was_disabled && s->period =3D=3D 0) { if (!qtest_enabled()) { fprintf(stderr, "Timer with period zero, disabling\n"); @@ -282,8 +322,12 @@ void ptimer_run(ptimer_state *s, int oneshot) } s->enabled =3D oneshot ? 2 : 1; if (was_disabled) { - s->next_event =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); - ptimer_reload(s, 0); + if (!s->callback) { + s->next_event =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + ptimer_reload(s, 0); + } else { + s->need_reload =3D true; + } } } =20 @@ -291,35 +335,50 @@ void ptimer_run(ptimer_state *s, int oneshot) is immediately restarted. */ void ptimer_stop(ptimer_state *s) { + assert(s->in_transaction || !s->callback); + if (!s->enabled) return; =20 s->delta =3D ptimer_get_count(s); timer_del(s->timer); s->enabled =3D 0; + if (s->callback) { + s->need_reload =3D false; + } } =20 /* Set counter increment interval in nanoseconds. */ void ptimer_set_period(ptimer_state *s, int64_t period) { + assert(s->in_transaction || !s->callback); s->delta =3D ptimer_get_count(s); s->period =3D period; s->period_frac =3D 0; if (s->enabled) { - s->next_event =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); - ptimer_reload(s, 0); + if (!s->callback) { + s->next_event =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + ptimer_reload(s, 0); + } else { + s->need_reload =3D true; + } } } =20 /* Set counter frequency in Hz. */ void ptimer_set_freq(ptimer_state *s, uint32_t freq) { + assert(s->in_transaction || !s->callback); s->delta =3D ptimer_get_count(s); s->period =3D 1000000000ll / freq; s->period_frac =3D (1000000000ll << 32) / freq; if (s->enabled) { - s->next_event =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); - ptimer_reload(s, 0); + if (!s->callback) { + s->next_event =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + ptimer_reload(s, 0); + } else { + s->need_reload =3D true; + } } } =20 @@ -327,12 +386,17 @@ void ptimer_set_freq(ptimer_state *s, uint32_t freq) count =3D limit. */ void ptimer_set_limit(ptimer_state *s, uint64_t limit, int reload) { + assert(s->in_transaction || !s->callback); s->limit =3D limit; if (reload) s->delta =3D limit; if (s->enabled && reload) { - s->next_event =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); - ptimer_reload(s, 0); + if (!s->callback) { + s->next_event =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + ptimer_reload(s, 0); + } else { + s->need_reload =3D true; + } } } =20 @@ -341,6 +405,32 @@ uint64_t ptimer_get_limit(ptimer_state *s) return s->limit; } =20 +void ptimer_transaction_begin(ptimer_state *s) +{ + assert(!s->in_transaction || !s->callback); + s->in_transaction =3D true; + s->need_reload =3D false; +} + +void ptimer_transaction_commit(ptimer_state *s) +{ + assert(s->in_transaction); + /* + * We must loop here because ptimer_reload() can call the callback + * function, which might then update ptimer state in a way that + * means we need to do another reload and possibly another callback. + * A disabled timer never needs reloading (and if we don't check + * this then we loop forever if ptimer_reload() disables the timer). + */ + while (s->need_reload && s->enabled) { + s->need_reload =3D false; + s->next_event =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + ptimer_reload(s, 0); + } + /* Now we've finished reload we can leave the transaction block. */ + s->in_transaction =3D false; +} + const VMStateDescription vmstate_ptimer =3D { .name =3D "ptimer", .version_id =3D 1, @@ -377,9 +467,41 @@ ptimer_state *ptimer_init_with_bh(QEMUBH *bh, uint8_t = policy_mask) return s; } =20 +ptimer_state *ptimer_init(ptimer_cb callback, void *callback_opaque, + uint8_t policy_mask) +{ + ptimer_state *s; + + /* + * The callback function is mandatory; so we use it to distinguish + * old-style QEMUBH ptimers from new transaction API ptimers. + * (ptimer_init_with_bh() allows a NULL bh pointer and at least + * one device (digic-timer) passes NULL, so it's not the case + * that either s->bh !=3D NULL or s->callback !=3D NULL.) + */ + assert(callback); + + s =3D g_new0(ptimer_state, 1); + s->timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, ptimer_tick, s); + s->policy_mask =3D policy_mask; + s->callback =3D callback; + s->callback_opaque =3D callback_opaque; + + /* + * These two policies are incompatible -- trigger-on-decrement implies + * a timer trigger when the count becomes 0, but no-immediate-trigger + * implies a trigger when the count stops being 0. + */ + assert(!((policy_mask & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT) && + (policy_mask & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER))); + return s; +} + void ptimer_free(ptimer_state *s) { - qemu_bh_delete(s->bh); + if (s->bh) { + qemu_bh_delete(s->bh); + } timer_free(s->timer); g_free(s); } --=20 2.20.1 From nobody Thu Apr 25 18:08:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1570555250; cv=none; d=zoho.com; s=zohoarc; b=iEENUT3OsZq+xmtqwmC4FGWc5eQm4cLmnqjYYei+UJuQwGpNyFcE1maMVjS5kMlkwcPU/pkFWC7kLstX618DehyhlWsTg/3uuaNDu5902PiEFxxLgTxsEbal3jZ2RDrCVJSNmhGPJSs7IZ4ZELMg8mex5fSZoUuZESKjo3BxFqA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1570555250; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id z9sm19135541wrl.35.2019.10.08.10.17.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Oct 2019 10:17:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qwANpzWfIEeRGUJ6saOUlObSLOjFsXhXk8QCpbryjDk=; b=ljUjknKZZ8tliKRFUJSOiiUKxRiENcfs9yEe5dTrY+Qy8yWxmKi4NPhtyPrUQxXsb/ X8AzHEQAr1jt8RVLPluxhq/dkf5EmZ5T9mDfXZHlHiGhKZBaEiHc40gvrj5lFP4yAky2 QYmKqI436vidElkEaAUx0LvbE9JHXchESkFGFd0sj76ux9CSDlL0Z9xcu8YnGr4rlpHy dvq0Ci61d+W/37RMtua++UfCc8LW4qWh9yh2pJh0zQ0rgyckrG4dhayIHzebBbGKXL2h rQ3qsQtFGRbZbSkG9eALvWrKC4RMTDo/VovDUJ+JBzr1NpBZqthVp+jnNsprDBbgrm4X aBCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qwANpzWfIEeRGUJ6saOUlObSLOjFsXhXk8QCpbryjDk=; b=EsxaXxQ200y/PFZzdBhjwGJ8JQb1+YUjnzGffs1hZBODa9bPGGB95edOokTZNC5uxw 4Iy50G77na2JSA2kF1wq+A7C1v+FG4SAskiCXUkWsTdNCgieZgHyLXV1m/HMTsmF5t1D pqAVx+NBP8u1v1Ry1xG+c0/thevZ5CaVZ3wpbIgscKhnD//b0vwTI1fbtanjTCcJildW iol8Xci43Tq3VEEf7u9Nq0oYfAOM0JI/OHoDFNgvXSoHAWvcR8WptPC7+mOit1TGMFmy Mrh1rYbSj0+mqq835sWQV2TVsGqSQrXUmBajqgNL001iybZ3wNQhwU1NeadRBoQiHHs6 JGAA== X-Gm-Message-State: APjAAAWEzF+LE7VVHL6kZ5182rK7QnJvVgALhlNjT3ruk8sGoWziyJwN ncuqau7IHSuN8p6fX0PKaQc5UQ== X-Google-Smtp-Source: APXvYqxdUjoHtx/6QQnsxhyaNR/9J07lU1RcDHCH26bq667rT1Sfz1Qi+3C2FNgG6evucGyQCGLyrA== X-Received: by 2002:a7b:c4d4:: with SMTP id g20mr4252433wmk.123.1570555068010; Tue, 08 Oct 2019 10:17:48 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 03/21] tests/ptimer-test: Switch to transaction-based ptimer API Date: Tue, 8 Oct 2019 18:17:22 +0100 Message-Id: <20191008171740.9679-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191008171740.9679-1-peter.maydell@linaro.org> References: <20191008171740.9679-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Paolo Bonzini Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Convert the ptimer test cases to the transaction-based ptimer API, by changing to ptimer_init(), dropping the now-unused QEMUBH variables, and surrounding each set of changes to the ptimer state in ptimer_transaction_begin/commit calls. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- tests/ptimer-test.c | 106 +++++++++++++++++++++++++++++++++++--------- 1 file changed, 84 insertions(+), 22 deletions(-) diff --git a/tests/ptimer-test.c b/tests/ptimer-test.c index a3c82d1d147..e16c30ce573 100644 --- a/tests/ptimer-test.c +++ b/tests/ptimer-test.c @@ -67,12 +67,13 @@ static void qemu_clock_step(uint64_t ns) static void check_set_count(gconstpointer arg) { const uint8_t *policy =3D arg; - QEMUBH *bh =3D qemu_bh_new(ptimer_trigger, NULL); - ptimer_state *ptimer =3D ptimer_init_with_bh(bh, *policy); + ptimer_state *ptimer =3D ptimer_init(ptimer_trigger, NULL, *policy); =20 triggered =3D false; =20 + ptimer_transaction_begin(ptimer); ptimer_set_count(ptimer, 1000); + ptimer_transaction_commit(ptimer); g_assert_cmpuint(ptimer_get_count(ptimer), =3D=3D, 1000); g_assert_false(triggered); ptimer_free(ptimer); @@ -81,17 +82,20 @@ static void check_set_count(gconstpointer arg) static void check_set_limit(gconstpointer arg) { const uint8_t *policy =3D arg; - QEMUBH *bh =3D qemu_bh_new(ptimer_trigger, NULL); - ptimer_state *ptimer =3D ptimer_init_with_bh(bh, *policy); + ptimer_state *ptimer =3D ptimer_init(ptimer_trigger, NULL, *policy); =20 triggered =3D false; =20 + ptimer_transaction_begin(ptimer); ptimer_set_limit(ptimer, 1000, 0); + ptimer_transaction_commit(ptimer); g_assert_cmpuint(ptimer_get_count(ptimer), =3D=3D, 0); g_assert_cmpuint(ptimer_get_limit(ptimer), =3D=3D, 1000); g_assert_false(triggered); =20 + ptimer_transaction_begin(ptimer); ptimer_set_limit(ptimer, 2000, 1); + ptimer_transaction_commit(ptimer); g_assert_cmpuint(ptimer_get_count(ptimer), =3D=3D, 2000); g_assert_cmpuint(ptimer_get_limit(ptimer), =3D=3D, 2000); g_assert_false(triggered); @@ -101,22 +105,25 @@ static void check_set_limit(gconstpointer arg) static void check_oneshot(gconstpointer arg) { const uint8_t *policy =3D arg; - QEMUBH *bh =3D qemu_bh_new(ptimer_trigger, NULL); - ptimer_state *ptimer =3D ptimer_init_with_bh(bh, *policy); + ptimer_state *ptimer =3D ptimer_init(ptimer_trigger, NULL, *policy); bool no_round_down =3D (*policy & PTIMER_POLICY_NO_COUNTER_ROUND_DOWN); =20 triggered =3D false; =20 + ptimer_transaction_begin(ptimer); ptimer_set_period(ptimer, 2000000); ptimer_set_count(ptimer, 10); ptimer_run(ptimer, 1); + ptimer_transaction_commit(ptimer); =20 qemu_clock_step(2000000 * 2 + 1); =20 g_assert_cmpuint(ptimer_get_count(ptimer), =3D=3D, no_round_down ? 8 := 7); g_assert_false(triggered); =20 + ptimer_transaction_begin(ptimer); ptimer_stop(ptimer); + ptimer_transaction_commit(ptimer); =20 g_assert_cmpuint(ptimer_get_count(ptimer), =3D=3D, no_round_down ? 8 := 7); g_assert_false(triggered); @@ -126,7 +133,9 @@ static void check_oneshot(gconstpointer arg) g_assert_cmpuint(ptimer_get_count(ptimer), =3D=3D, no_round_down ? 8 := 7); g_assert_false(triggered); =20 + ptimer_transaction_begin(ptimer); ptimer_run(ptimer, 1); + ptimer_transaction_commit(ptimer); =20 qemu_clock_step(2000000 * 7 + 1); =20 @@ -157,28 +166,36 @@ static void check_oneshot(gconstpointer arg) g_assert_cmpuint(ptimer_get_count(ptimer), =3D=3D, 0); g_assert_false(triggered); =20 + ptimer_transaction_begin(ptimer); ptimer_set_count(ptimer, 10); + ptimer_transaction_commit(ptimer); =20 qemu_clock_step(20000000 + 1); =20 g_assert_cmpuint(ptimer_get_count(ptimer), =3D=3D, 10); g_assert_false(triggered); =20 + ptimer_transaction_begin(ptimer); ptimer_set_limit(ptimer, 9, 1); + ptimer_transaction_commit(ptimer); =20 qemu_clock_step(20000000 + 1); =20 g_assert_cmpuint(ptimer_get_count(ptimer), =3D=3D, 9); g_assert_false(triggered); =20 + ptimer_transaction_begin(ptimer); ptimer_run(ptimer, 1); + ptimer_transaction_commit(ptimer); =20 qemu_clock_step(2000000 + 1); =20 g_assert_cmpuint(ptimer_get_count(ptimer), =3D=3D, no_round_down ? 8 := 7); g_assert_false(triggered); =20 + ptimer_transaction_begin(ptimer); ptimer_set_count(ptimer, 20); + ptimer_transaction_commit(ptimer); =20 qemu_clock_step(2000000 * 19 + 1); =20 @@ -190,7 +207,9 @@ static void check_oneshot(gconstpointer arg) g_assert_cmpuint(ptimer_get_count(ptimer), =3D=3D, 0); g_assert_true(triggered); =20 + ptimer_transaction_begin(ptimer); ptimer_stop(ptimer); + ptimer_transaction_commit(ptimer); =20 triggered =3D false; =20 @@ -204,8 +223,7 @@ static void check_oneshot(gconstpointer arg) static void check_periodic(gconstpointer arg) { const uint8_t *policy =3D arg; - QEMUBH *bh =3D qemu_bh_new(ptimer_trigger, NULL); - ptimer_state *ptimer =3D ptimer_init_with_bh(bh, *policy); + ptimer_state *ptimer =3D ptimer_init(ptimer_trigger, NULL, *policy); bool wrap_policy =3D (*policy & PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD); bool no_immediate_trigger =3D (*policy & PTIMER_POLICY_NO_IMMEDIATE_TR= IGGER); bool no_immediate_reload =3D (*policy & PTIMER_POLICY_NO_IMMEDIATE_REL= OAD); @@ -214,9 +232,11 @@ static void check_periodic(gconstpointer arg) =20 triggered =3D false; =20 + ptimer_transaction_begin(ptimer); ptimer_set_period(ptimer, 2000000); ptimer_set_limit(ptimer, 10, 1); ptimer_run(ptimer, 0); + ptimer_transaction_commit(ptimer); =20 g_assert_cmpuint(ptimer_get_count(ptimer), =3D=3D, 10); g_assert_false(triggered); @@ -245,7 +265,9 @@ static void check_periodic(gconstpointer arg) (no_round_down ? 9 : 8) + (wrap_policy ? 1 : 0)); g_assert_false(triggered); =20 + ptimer_transaction_begin(ptimer); ptimer_set_count(ptimer, 20); + ptimer_transaction_commit(ptimer); =20 g_assert_cmpuint(ptimer_get_count(ptimer), =3D=3D, 20); g_assert_false(triggered); @@ -268,7 +290,9 @@ static void check_periodic(gconstpointer arg) =20 triggered =3D false; =20 + ptimer_transaction_begin(ptimer); ptimer_set_count(ptimer, 3); + ptimer_transaction_commit(ptimer); =20 g_assert_cmpuint(ptimer_get_count(ptimer), =3D=3D, 3); g_assert_false(triggered); @@ -284,7 +308,9 @@ static void check_periodic(gconstpointer arg) (no_round_down ? 9 : 8) + (wrap_policy ? 1 : 0)); g_assert_true(triggered); =20 + ptimer_transaction_begin(ptimer); ptimer_stop(ptimer); + ptimer_transaction_commit(ptimer); triggered =3D false; =20 qemu_clock_step(2000000); @@ -293,8 +319,10 @@ static void check_periodic(gconstpointer arg) (no_round_down ? 9 : 8) + (wrap_policy ? 1 : 0)); g_assert_false(triggered); =20 + ptimer_transaction_begin(ptimer); ptimer_set_count(ptimer, 3); ptimer_run(ptimer, 0); + ptimer_transaction_commit(ptimer); =20 qemu_clock_step(2000000 * 3 + 1); =20 @@ -310,7 +338,9 @@ static void check_periodic(gconstpointer arg) (no_round_down ? 9 : 8) + (wrap_policy ? 1 : 0)); g_assert_false(triggered); =20 + ptimer_transaction_begin(ptimer); ptimer_set_count(ptimer, 0); + ptimer_transaction_commit(ptimer); g_assert_cmpuint(ptimer_get_count(ptimer), =3D=3D, no_immediate_reload ? 0 : 10); =20 @@ -348,7 +378,9 @@ static void check_periodic(gconstpointer arg) (no_round_down ? 8 : 7) + (wrap_policy ? 1 : 0)); g_assert_true(triggered); =20 + ptimer_transaction_begin(ptimer); ptimer_stop(ptimer); + ptimer_transaction_commit(ptimer); =20 triggered =3D false; =20 @@ -358,8 +390,13 @@ static void check_periodic(gconstpointer arg) (no_round_down ? 8 : 7) + (wrap_policy ? 1 : 0)); g_assert_false(triggered); =20 + ptimer_transaction_begin(ptimer); ptimer_run(ptimer, 0); + ptimer_transaction_commit(ptimer); + + ptimer_transaction_begin(ptimer); ptimer_set_period(ptimer, 0); + ptimer_transaction_commit(ptimer); =20 qemu_clock_step(2000000 + 1); =20 @@ -372,23 +409,26 @@ static void check_periodic(gconstpointer arg) static void check_on_the_fly_mode_change(gconstpointer arg) { const uint8_t *policy =3D arg; - QEMUBH *bh =3D qemu_bh_new(ptimer_trigger, NULL); - ptimer_state *ptimer =3D ptimer_init_with_bh(bh, *policy); + ptimer_state *ptimer =3D ptimer_init(ptimer_trigger, NULL, *policy); bool wrap_policy =3D (*policy & PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD); bool no_round_down =3D (*policy & PTIMER_POLICY_NO_COUNTER_ROUND_DOWN); =20 triggered =3D false; =20 + ptimer_transaction_begin(ptimer); ptimer_set_period(ptimer, 2000000); ptimer_set_limit(ptimer, 10, 1); ptimer_run(ptimer, 1); + ptimer_transaction_commit(ptimer); =20 qemu_clock_step(2000000 * 9 + 1); =20 g_assert_cmpuint(ptimer_get_count(ptimer), =3D=3D, no_round_down ? 1 := 0); g_assert_false(triggered); =20 + ptimer_transaction_begin(ptimer); ptimer_run(ptimer, 0); + ptimer_transaction_commit(ptimer); =20 g_assert_cmpuint(ptimer_get_count(ptimer), =3D=3D, no_round_down ? 1 := 0); g_assert_false(triggered); @@ -403,7 +443,9 @@ static void check_on_the_fly_mode_change(gconstpointer = arg) =20 qemu_clock_step(2000000 * 9); =20 + ptimer_transaction_begin(ptimer); ptimer_run(ptimer, 1); + ptimer_transaction_commit(ptimer); =20 g_assert_cmpuint(ptimer_get_count(ptimer), =3D=3D, (no_round_down ? 1 : 0) + (wrap_policy ? 1 : 0)); @@ -419,22 +461,25 @@ static void check_on_the_fly_mode_change(gconstpointe= r arg) static void check_on_the_fly_period_change(gconstpointer arg) { const uint8_t *policy =3D arg; - QEMUBH *bh =3D qemu_bh_new(ptimer_trigger, NULL); - ptimer_state *ptimer =3D ptimer_init_with_bh(bh, *policy); + ptimer_state *ptimer =3D ptimer_init(ptimer_trigger, NULL, *policy); bool no_round_down =3D (*policy & PTIMER_POLICY_NO_COUNTER_ROUND_DOWN); =20 triggered =3D false; =20 + ptimer_transaction_begin(ptimer); ptimer_set_period(ptimer, 2000000); ptimer_set_limit(ptimer, 8, 1); ptimer_run(ptimer, 1); + ptimer_transaction_commit(ptimer); =20 qemu_clock_step(2000000 * 4 + 1); =20 g_assert_cmpuint(ptimer_get_count(ptimer), =3D=3D, no_round_down ? 4 := 3); g_assert_false(triggered); =20 + ptimer_transaction_begin(ptimer); ptimer_set_period(ptimer, 4000000); + ptimer_transaction_commit(ptimer); g_assert_cmpuint(ptimer_get_count(ptimer), =3D=3D, no_round_down ? 4 := 3); =20 qemu_clock_step(4000000 * 2 + 1); @@ -452,22 +497,25 @@ static void check_on_the_fly_period_change(gconstpoin= ter arg) static void check_on_the_fly_freq_change(gconstpointer arg) { const uint8_t *policy =3D arg; - QEMUBH *bh =3D qemu_bh_new(ptimer_trigger, NULL); - ptimer_state *ptimer =3D ptimer_init_with_bh(bh, *policy); + ptimer_state *ptimer =3D ptimer_init(ptimer_trigger, NULL, *policy); bool no_round_down =3D (*policy & PTIMER_POLICY_NO_COUNTER_ROUND_DOWN); =20 triggered =3D false; =20 + ptimer_transaction_begin(ptimer); ptimer_set_freq(ptimer, 500); ptimer_set_limit(ptimer, 8, 1); ptimer_run(ptimer, 1); + ptimer_transaction_commit(ptimer); =20 qemu_clock_step(2000000 * 4 + 1); =20 g_assert_cmpuint(ptimer_get_count(ptimer), =3D=3D, no_round_down ? 4 := 3); g_assert_false(triggered); =20 + ptimer_transaction_begin(ptimer); ptimer_set_freq(ptimer, 250); + ptimer_transaction_commit(ptimer); g_assert_cmpuint(ptimer_get_count(ptimer), =3D=3D, no_round_down ? 4 := 3); =20 qemu_clock_step(2000000 * 4 + 1); @@ -485,13 +533,14 @@ static void check_on_the_fly_freq_change(gconstpointe= r arg) static void check_run_with_period_0(gconstpointer arg) { const uint8_t *policy =3D arg; - QEMUBH *bh =3D qemu_bh_new(ptimer_trigger, NULL); - ptimer_state *ptimer =3D ptimer_init_with_bh(bh, *policy); + ptimer_state *ptimer =3D ptimer_init(ptimer_trigger, NULL, *policy); =20 triggered =3D false; =20 + ptimer_transaction_begin(ptimer); ptimer_set_count(ptimer, 99); ptimer_run(ptimer, 1); + ptimer_transaction_commit(ptimer); =20 qemu_clock_step(10 * NANOSECONDS_PER_SECOND); =20 @@ -503,8 +552,7 @@ static void check_run_with_period_0(gconstpointer arg) static void check_run_with_delta_0(gconstpointer arg) { const uint8_t *policy =3D arg; - QEMUBH *bh =3D qemu_bh_new(ptimer_trigger, NULL); - ptimer_state *ptimer =3D ptimer_init_with_bh(bh, *policy); + ptimer_state *ptimer =3D ptimer_init(ptimer_trigger, NULL, *policy); bool wrap_policy =3D (*policy & PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD); bool no_immediate_trigger =3D (*policy & PTIMER_POLICY_NO_IMMEDIATE_TR= IGGER); bool no_immediate_reload =3D (*policy & PTIMER_POLICY_NO_IMMEDIATE_REL= OAD); @@ -513,9 +561,11 @@ static void check_run_with_delta_0(gconstpointer arg) =20 triggered =3D false; =20 + ptimer_transaction_begin(ptimer); ptimer_set_period(ptimer, 2000000); ptimer_set_limit(ptimer, 99, 0); ptimer_run(ptimer, 1); + ptimer_transaction_commit(ptimer); g_assert_cmpuint(ptimer_get_count(ptimer), =3D=3D, no_immediate_reload ? 0 : 99); =20 @@ -541,8 +591,10 @@ static void check_run_with_delta_0(gconstpointer arg) g_assert_false(triggered); } =20 + ptimer_transaction_begin(ptimer); ptimer_set_count(ptimer, 99); ptimer_run(ptimer, 1); + ptimer_transaction_commit(ptimer); } =20 qemu_clock_step(2000000 + 1); @@ -562,8 +614,10 @@ static void check_run_with_delta_0(gconstpointer arg) =20 triggered =3D false; =20 + ptimer_transaction_begin(ptimer); ptimer_set_count(ptimer, 0); ptimer_run(ptimer, 0); + ptimer_transaction_commit(ptimer); g_assert_cmpuint(ptimer_get_count(ptimer), =3D=3D, no_immediate_reload ? 0 : 99); =20 @@ -602,23 +656,26 @@ static void check_run_with_delta_0(gconstpointer arg) wrap_policy ? 0 : (no_round_down ? 99 : 98)); g_assert_true(triggered); =20 + ptimer_transaction_begin(ptimer); ptimer_stop(ptimer); + ptimer_transaction_commit(ptimer); ptimer_free(ptimer); } =20 static void check_periodic_with_load_0(gconstpointer arg) { const uint8_t *policy =3D arg; - QEMUBH *bh =3D qemu_bh_new(ptimer_trigger, NULL); - ptimer_state *ptimer =3D ptimer_init_with_bh(bh, *policy); + ptimer_state *ptimer =3D ptimer_init(ptimer_trigger, NULL, *policy); bool continuous_trigger =3D (*policy & PTIMER_POLICY_CONTINUOUS_TRIGGE= R); bool no_immediate_trigger =3D (*policy & PTIMER_POLICY_NO_IMMEDIATE_TR= IGGER); bool trig_only_on_dec =3D (*policy & PTIMER_POLICY_TRIGGER_ONLY_ON_DEC= REMENT); =20 triggered =3D false; =20 + ptimer_transaction_begin(ptimer); ptimer_set_period(ptimer, 2000000); ptimer_run(ptimer, 0); + ptimer_transaction_commit(ptimer); =20 g_assert_cmpuint(ptimer_get_count(ptimer), =3D=3D, 0); =20 @@ -642,8 +699,10 @@ static void check_periodic_with_load_0(gconstpointer a= rg) =20 triggered =3D false; =20 + ptimer_transaction_begin(ptimer); ptimer_set_count(ptimer, 10); ptimer_run(ptimer, 0); + ptimer_transaction_commit(ptimer); =20 qemu_clock_step(2000000 * 10 + 1); =20 @@ -662,22 +721,25 @@ static void check_periodic_with_load_0(gconstpointer = arg) g_assert_false(triggered); } =20 + ptimer_transaction_begin(ptimer); ptimer_stop(ptimer); + ptimer_transaction_commit(ptimer); ptimer_free(ptimer); } =20 static void check_oneshot_with_load_0(gconstpointer arg) { const uint8_t *policy =3D arg; - QEMUBH *bh =3D qemu_bh_new(ptimer_trigger, NULL); - ptimer_state *ptimer =3D ptimer_init_with_bh(bh, *policy); + ptimer_state *ptimer =3D ptimer_init(ptimer_trigger, NULL, *policy); bool no_immediate_trigger =3D (*policy & PTIMER_POLICY_NO_IMMEDIATE_TR= IGGER); bool trig_only_on_dec =3D (*policy & PTIMER_POLICY_TRIGGER_ONLY_ON_DEC= REMENT); =20 triggered =3D false; =20 + ptimer_transaction_begin(ptimer); ptimer_set_period(ptimer, 2000000); ptimer_run(ptimer, 1); + ptimer_transaction_commit(ptimer); =20 g_assert_cmpuint(ptimer_get_count(ptimer), =3D=3D, 0); =20 --=20 2.20.1 From nobody Thu Apr 25 18:08:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id z9sm19135541wrl.35.2019.10.08.10.17.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Oct 2019 10:17:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vp4+p4FLQruJ614qug2AywQIur5rU9O0ZC+bqOyPTzg=; b=PtVYUBhIWbWgg8zezYNZa6Tzzuev48iYDvlHzBz+NQDGavmE+fwArjtw6U167K/WEw exlh9g3JiFiDY9LU4mhivPo0bD8m1Z9Seqw7ZkZha+L12vQJk2xMHc00lORxM8gV+mHX BkfXxKLd//QpFiJmfWBc0Yx4inQSXPvsjKBt9YG7UQRjuC5ZUJq00ScLjMqd76FmbsUp SJHrX8CfJfKdYcod9fpYo0fMwj8/hkOGXE3C2lpF3Hrw4V33BWXbX50Uc4wRCXOkMK/K CwS5aIPMNeZshkxZj5gb5tIe9bkyCERM9Ewi0o07STsznRkBzrt5ioF/UzdLIcVKbOam tzGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vp4+p4FLQruJ614qug2AywQIur5rU9O0ZC+bqOyPTzg=; b=J2VRDrPs6xpzXIfyWPGrBo3mI9UeuqxhYiSoS+0fVAh5k9QATZaHasOPU3trkegIgF IPSSEhLIy/imopHQDnHQA1kDvgJgmDonmprX5MLyH5jwNrPK1wdVlN97eLXhF08te+LH De/KCiCjIvqF21ovGnQOd4uh7f0sE7UtThyPXMD+j1H76Hrkwi7bkMszE3TFlApeW8Oe peUvp55Z+Se+F7228MrR1rzXO6xZFFOAO2e/2YZT1AUMQzaxm9E3/Xk1YrmsKXjqJG1j vMg08Wz1b2WZY7R02vVQKBv1uCPbLo173dB+kvrMzbgO4G5kcQjY8WqyYLlRnyXCG73Z zrBA== X-Gm-Message-State: APjAAAWjzMKGhhi1EfwcZgY+b1+rHGc4VyX4su3f0i3J40EZrfPCIGyJ WoXJ9lRXqD/eCn2MDgHxAlxQPw== X-Google-Smtp-Source: APXvYqx/s53I5iXHlJAyVkB1Vtz/ZIT0P32aFNtEYH5QI3eNMYC94hiktNb/JUS9TBROZWKR7SmbVA== X-Received: by 2002:a1c:540c:: with SMTP id i12mr4958787wmb.90.1570555069072; Tue, 08 Oct 2019 10:17:49 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 04/21] hw/timer/arm_timer.c: Switch to transaction-based ptimer API Date: Tue, 8 Oct 2019 18:17:23 +0100 Message-Id: <20191008171740.9679-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191008171740.9679-1-peter.maydell@linaro.org> References: <20191008171740.9679-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Paolo Bonzini Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Switch the arm_timer.c code away from bottom-half based ptimers to the new transaction-based ptimer API. This just requires adding begin/commit calls around the various arms of arm_timer_write() that modify the ptimer state, and using the new ptimer_init() function to create the timer. Fixes: https://bugs.launchpad.net/qemu/+bug/1777777 Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/timer/arm_timer.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c index 848fbcb0e25..255def3deec 100644 --- a/hw/timer/arm_timer.c +++ b/hw/timer/arm_timer.c @@ -14,7 +14,6 @@ #include "hw/irq.h" #include "hw/ptimer.h" #include "hw/qdev-properties.h" -#include "qemu/main-loop.h" #include "qemu/module.h" #include "qemu/log.h" #include "trace.h" @@ -79,7 +78,10 @@ static uint32_t arm_timer_read(void *opaque, hwaddr offs= et) } } =20 -/* Reset the timer limit after settings have changed. */ +/* + * Reset the timer limit after settings have changed. + * May only be called from inside a ptimer transaction block. + */ static void arm_timer_recalibrate(arm_timer_state *s, int reload) { uint32_t limit; @@ -106,13 +108,16 @@ static void arm_timer_write(void *opaque, hwaddr offs= et, switch (offset >> 2) { case 0: /* TimerLoad */ s->limit =3D value; + ptimer_transaction_begin(s->timer); arm_timer_recalibrate(s, 1); + ptimer_transaction_commit(s->timer); break; case 1: /* TimerValue */ /* ??? Linux seems to want to write to this readonly register. Ignore it. */ break; case 2: /* TimerControl */ + ptimer_transaction_begin(s->timer); if (s->control & TIMER_CTRL_ENABLE) { /* Pause the timer if it is running. This may cause some inaccuracy dure to rounding, but avoids a whole lot of other @@ -132,13 +137,16 @@ static void arm_timer_write(void *opaque, hwaddr offs= et, /* Restart the timer if still enabled. */ ptimer_run(s->timer, (s->control & TIMER_CTRL_ONESHOT) !=3D 0); } + ptimer_transaction_commit(s->timer); break; case 3: /* TimerIntClr */ s->int_level =3D 0; break; case 6: /* TimerBGLoad */ s->limit =3D value; + ptimer_transaction_begin(s->timer); arm_timer_recalibrate(s, 0); + ptimer_transaction_commit(s->timer); break; default: qemu_log_mask(LOG_GUEST_ERROR, @@ -170,14 +178,12 @@ static const VMStateDescription vmstate_arm_timer =3D= { static arm_timer_state *arm_timer_init(uint32_t freq) { arm_timer_state *s; - QEMUBH *bh; =20 s =3D (arm_timer_state *)g_malloc0(sizeof(arm_timer_state)); s->freq =3D freq; s->control =3D TIMER_CTRL_IE; =20 - bh =3D qemu_bh_new(arm_timer_tick, s); - s->timer =3D ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); + s->timer =3D ptimer_init(arm_timer_tick, s, PTIMER_POLICY_DEFAULT); vmstate_register(NULL, -1, &vmstate_arm_timer, s); return s; } --=20 2.20.1 From nobody Thu Apr 25 18:08:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1570555228; cv=none; d=zoho.com; s=zohoarc; b=kQOlXEUv0kNXp7MH4efxnWw45clf9uo1dSpsyJvCggs/HJ6XYmhLtgyqSkEkaCxOtLWjbBCQl8e93OO0TEUctmChPBhOJLxqdGGOd7uAH7h7FiwlnaWt78y5KSOYPicCXD8/N+xJNRtixG4zsZE3gmfnAKqzdQiKBc2BMvMy5Ks= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1570555228; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=naa7xg2s4V4Ih3fFkoGzCGOvDaxJr7Ss6St8GXFDrdg=; b=VyR1UZ1EryjJgEWKtqCRXI7Dlo0Fmg7XuQzPyPylImFja7LydSsl0MMKWy+Ut97NaGtVC2dgH8wHrMvcr2gZ4n96whC07oA0KaS8Trxjwbbl64WSd6diURpiL1KEXOFjZM95e/0XBSOQanN1hEUL5l8Wq15/2Le0DT/1pJfplAY= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1570555228690337.003708284858; Tue, 8 Oct 2019 10:20:28 -0700 (PDT) Received: from localhost ([::1]:58974 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iHt9u-0000Dd-MC for importer@patchew.org; Tue, 08 Oct 2019 13:20:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48768) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iHt7R-0006cM-8B for qemu-devel@nongnu.org; Tue, 08 Oct 2019 13:17:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iHt7P-0002EB-OE for qemu-devel@nongnu.org; Tue, 08 Oct 2019 13:17:53 -0400 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:38953) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iHt7P-0002DR-CR for qemu-devel@nongnu.org; Tue, 08 Oct 2019 13:17:51 -0400 Received: by mail-wm1-x342.google.com with SMTP id v17so3928256wml.4 for ; Tue, 08 Oct 2019 10:17:51 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id z9sm19135541wrl.35.2019.10.08.10.17.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Oct 2019 10:17:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=naa7xg2s4V4Ih3fFkoGzCGOvDaxJr7Ss6St8GXFDrdg=; b=Fybt316FzjeS3HF9a6qrViSMmsZaV7kgC+Ee2l59Zh4st3gK8fyskTJqzmxDnjfi9a bPt0U7taa+Rlc3QixUjfB5WdUmUSP+rTgsgdp75LsXvZVl2+rKUQwvO2ORbuKgeN6Oa0 FsinJEwk9YmXf6rPSgpjDJYD6d5/QdD6JWFt+arGUcLkBQBtEIL3+UFVbJDcGUbkgov5 lHRODwz5kUJ1gDE1zwzlAMo5RE3+zjvVHqkn3eAXhHs4GNpIkab3epgaILUJJZHeIZah YaOAHYdxxjLF1aa5KtiqPk+bf2SXbGzA2pSZTCsWW4zHnJnAkFfVsDKR2Ndk+lmdlhmq OBMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=naa7xg2s4V4Ih3fFkoGzCGOvDaxJr7Ss6St8GXFDrdg=; b=pbHCGJMzMLS+FlKTCA5AXZ7TN2H4D1Of6E3RAboLhdfRtkqi3EchL8/N/N55cQ9P6G /fVmNfyqk/RUXF3OkaqgpxccI3jUmCJCvXv2rrySLVw+7ghH5r7q8Gd4gOKNYEjfFuXT b5BWlpZzT6qEfk+te+chtobJmbUXrIkHCqFyfwIib3GBLops1OCEOQYe441lMpulZAiR 1+880x9bfVUemCds3LE//NIYzcoKdV4qodHollCUfEs1LJPhCWjyXtGZ7pSc1Tkl40WG 6dJoZ7BtLG9vKipMTJ9jXF3iKi938/xtvbT3DfsVFAqDHssqZzSpP4A+O+2O+J49K/Sz LyXg== X-Gm-Message-State: APjAAAW6pJZPuvq9vlsYTkp3LcMtMD5ajpqVUHQHwpV3LETcg8qIskuF MA6rMhnpbJpXG4jyyc817Mks9g== X-Google-Smtp-Source: APXvYqxoykkcq0rqepQ6/Dmopbc1EYZU6JfJU4M2jEIy2g9wRQ1+G8FrLEd+SR+mMqx5bIX8bVR7DA== X-Received: by 2002:a05:600c:2489:: with SMTP id 9mr4591426wms.131.1570555070234; Tue, 08 Oct 2019 10:17:50 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 05/21] hw/arm/musicpal.c: Switch to transaction-based ptimer API Date: Tue, 8 Oct 2019 18:17:24 +0100 Message-Id: <20191008171740.9679-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191008171740.9679-1-peter.maydell@linaro.org> References: <20191008171740.9679-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Paolo Bonzini Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Switch the musicpal code away from bottom-half based ptimers to the new transaction-based ptimer API. This just requires adding begin/commit calls around the various places that modify the ptimer state, and using the new ptimer_init() function to create the timer. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/arm/musicpal.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c index b3624d5e280..f68a399a984 100644 --- a/hw/arm/musicpal.c +++ b/hw/arm/musicpal.c @@ -843,13 +843,10 @@ static void mv88w8618_timer_tick(void *opaque) static void mv88w8618_timer_init(SysBusDevice *dev, mv88w8618_timer_state = *s, uint32_t freq) { - QEMUBH *bh; - sysbus_init_irq(dev, &s->irq); s->freq =3D freq; =20 - bh =3D qemu_bh_new(mv88w8618_timer_tick, s); - s->ptimer =3D ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); + s->ptimer =3D ptimer_init(mv88w8618_timer_tick, s, PTIMER_POLICY_DEFAU= LT); } =20 static uint64_t mv88w8618_pit_read(void *opaque, hwaddr offset, @@ -879,16 +876,19 @@ static void mv88w8618_pit_write(void *opaque, hwaddr = offset, case MP_PIT_TIMER1_LENGTH ... MP_PIT_TIMER4_LENGTH: t =3D &s->timer[offset >> 2]; t->limit =3D value; + ptimer_transaction_begin(t->ptimer); if (t->limit > 0) { ptimer_set_limit(t->ptimer, t->limit, 1); } else { ptimer_stop(t->ptimer); } + ptimer_transaction_commit(t->ptimer); break; =20 case MP_PIT_CONTROL: for (i =3D 0; i < 4; i++) { t =3D &s->timer[i]; + ptimer_transaction_begin(t->ptimer); if (value & 0xf && t->limit > 0) { ptimer_set_limit(t->ptimer, t->limit, 0); ptimer_set_freq(t->ptimer, t->freq); @@ -896,6 +896,7 @@ static void mv88w8618_pit_write(void *opaque, hwaddr of= fset, } else { ptimer_stop(t->ptimer); } + ptimer_transaction_commit(t->ptimer); value >>=3D 4; } break; @@ -914,8 +915,11 @@ static void mv88w8618_pit_reset(DeviceState *d) int i; =20 for (i =3D 0; i < 4; i++) { - ptimer_stop(s->timer[i].ptimer); - s->timer[i].limit =3D 0; + mv88w8618_timer_state *t =3D &s->timer[i]; + ptimer_transaction_begin(t->ptimer); + ptimer_stop(t->ptimer); + ptimer_transaction_commit(t->ptimer); + t->limit =3D 0; } } =20 --=20 2.20.1 From nobody Thu Apr 25 18:08:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1570555524; cv=none; d=zoho.com; s=zohoarc; b=awZJH14jdrdgzueAy5lC9ExUQGyJorQx/K4NRyHQQRB53ylIp2PZ+XfeuefHPfeFuWaWUrA9ijR3H/EtmzHIUPyp4xYGyDpyBEDZJDYXyVwKDJ7OuMRGq81wmk+HXjBLmfMsbVcHo6IjS4ABMzg7AmbzkeROpy7NC6AXnqkRel4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1570555524; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=jKb9Rbp8gXPT0bACEbKBu5D4v0cg+tsMxucN4ICfYFw=; b=F7XAk1MkREk+yAguXPa+CT2Cvjv6aX36r1QoRQ1l7w90bXwaIdIS/nCI1E6+kJ4Fua4kR+g+STsr9NiFnTtCbUjhpvdyvGh3T7KwNDe+KWGlmkFXPdXSAE9P20iV3bpmpGzRUjUt28BEVM8uSQykSzBc6q6PI2ofBAdkpWx6Tb4= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1570555524303766.1198392930435; Tue, 8 Oct 2019 10:25:24 -0700 (PDT) Received: from localhost ([::1]:59062 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iHtEg-0004dC-C7 for importer@patchew.org; Tue, 08 Oct 2019 13:25:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48820) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iHt7T-0006fP-Hs for qemu-devel@nongnu.org; Tue, 08 Oct 2019 13:17:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iHt7R-0002Fc-5x for qemu-devel@nongnu.org; Tue, 08 Oct 2019 13:17:54 -0400 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:43025) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iHt7Q-0002ER-Qs for qemu-devel@nongnu.org; Tue, 08 Oct 2019 13:17:53 -0400 Received: by mail-wr1-x444.google.com with SMTP id j18so19527935wrq.10 for ; Tue, 08 Oct 2019 10:17:52 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id z9sm19135541wrl.35.2019.10.08.10.17.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Oct 2019 10:17:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jKb9Rbp8gXPT0bACEbKBu5D4v0cg+tsMxucN4ICfYFw=; b=TCDKiM1WzJoK/uWnKEXcIpAJL+L1HRBXg6r2xaCO9DHH1ZI6jwgu7N4cSrLpUM9WjL QGayGO5T+uEYCBDBmnanaHTbtwUMUvj0zI3XCwk5LL2RCD8SIUmUxwX6LB6hF6suj7dN VeN0yyoruDnREAEJPQrhDm9I2QJMm1T7cCn8ooQ5WrJdo+tsGp2iSXUkbX2E/sLd0bQZ HAtXImvtEDj/aeNQAplB3HXugKhnnU3mQh3Vu+maHsBXuya0scq/c8wISi3O+bHy7L6S 6uxQWppua6ROF7pgf/v8fRhoC7jvdCRMlU4RlJ5NesSUJq0NFcqkWPOpOXl2cWKfl7kY DtVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jKb9Rbp8gXPT0bACEbKBu5D4v0cg+tsMxucN4ICfYFw=; b=leL5P9NVR4BdieSqDHNRb7cwo5L13iYw8I2bD3f11os5pKvQAY8F6bYGpuYAMWqrz8 3rc6Y7rMSn24aAfLKNSe5QzVjWTDVErPvn1huWIvqRwJRoPSAIhOoR8QhZmLGP9F/DxE uSxvemOUx8oCplJgNbQlpqezgEXsdKMG6bVoZM90kpLNHuP5ICBM0abWpaZUME4XAK5m iebfAlKWoGZd9A8H6fqPMw0n4WhynjP99NTCiHXnIZ33TQppNJEpXC1z3QlhbzNsGiM0 rhOyre+5dQxgBNJZhM2WcoL5ZF7/qfI5gTOX2R9MAZieYoJCILbPaV7fasB7D+oLq9Q3 psmQ== X-Gm-Message-State: APjAAAVKmfGkLTwYSsPk1F3iXAzP8M3AfsY2YeHLqFrXQv64sD/9tnX4 sk6o+M8Ed5HeU2JTp/n8PgS/Mw5jvNj2Cw== X-Google-Smtp-Source: APXvYqxE3Ei06SIYcvafrTXFVmwNL+phMsbf/asXBt06uk8D4Tb3RreH/lfYr7YMc6SwcG1SWtB3ag== X-Received: by 2002:a5d:49cb:: with SMTP id t11mr25862841wrs.366.1570555071679; Tue, 08 Oct 2019 10:17:51 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 06/21] hw/timer/allwinner-a10-pit.c: Switch to transaction-based ptimer API Date: Tue, 8 Oct 2019 18:17:25 +0100 Message-Id: <20191008171740.9679-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191008171740.9679-1-peter.maydell@linaro.org> References: <20191008171740.9679-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Paolo Bonzini Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Switch the allwinner-a10-pit code away from bottom-half based ptimers to the new transaction-based ptimer API. This just requires adding begin/commit calls around the various places that modify the ptimer state, and using the new ptimer_init() function to create the timer. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/timer/allwinner-a10-pit.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index 28d055e42f3..aae880f5b35 100644 --- a/hw/timer/allwinner-a10-pit.c +++ b/hw/timer/allwinner-a10-pit.c @@ -22,7 +22,6 @@ #include "hw/timer/allwinner-a10-pit.h" #include "migration/vmstate.h" #include "qemu/log.h" -#include "qemu/main-loop.h" #include "qemu/module.h" =20 static void a10_pit_update_irq(AwA10PITState *s) @@ -80,6 +79,7 @@ static uint64_t a10_pit_read(void *opaque, hwaddr offset,= unsigned size) return 0; } =20 +/* Must be called inside a ptimer transaction block for s->timer[index] */ static void a10_pit_set_freq(AwA10PITState *s, int index) { uint32_t prescaler, source, source_freq; @@ -118,6 +118,7 @@ static void a10_pit_write(void *opaque, hwaddr offset, = uint64_t value, switch (offset & 0x0f) { case AW_A10_PIT_TIMER_CONTROL: s->control[index] =3D value; + ptimer_transaction_begin(s->timer[index]); a10_pit_set_freq(s, index); if (s->control[index] & AW_A10_PIT_TIMER_RELOAD) { ptimer_set_count(s->timer[index], s->interval[index]); @@ -131,10 +132,13 @@ static void a10_pit_write(void *opaque, hwaddr offset= , uint64_t value, } else { ptimer_stop(s->timer[index]); } + ptimer_transaction_commit(s->timer[index]); break; case AW_A10_PIT_TIMER_INTERVAL: s->interval[index] =3D value; + ptimer_transaction_begin(s->timer[index]); ptimer_set_limit(s->timer[index], s->interval[index], 1); + ptimer_transaction_commit(s->timer[index]); break; case AW_A10_PIT_TIMER_COUNT: s->count[index] =3D value; @@ -225,8 +229,10 @@ static void a10_pit_reset(DeviceState *dev) s->control[i] =3D AW_A10_PIT_DEFAULT_CLOCK; s->interval[i] =3D 0; s->count[i] =3D 0; + ptimer_transaction_begin(s->timer[i]); ptimer_stop(s->timer[i]); a10_pit_set_freq(s, i); + ptimer_transaction_commit(s->timer[i]); } s->watch_dog_mode =3D 0; s->watch_dog_control =3D 0; @@ -255,7 +261,6 @@ static void a10_pit_init(Object *obj) { AwA10PITState *s =3D AW_A10_PIT(obj); SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); - QEMUBH * bh[AW_A10_PIT_TIMER_NR]; uint8_t i; =20 for (i =3D 0; i < AW_A10_PIT_TIMER_NR; i++) { @@ -270,8 +275,7 @@ static void a10_pit_init(Object *obj) =20 tc->container =3D s; tc->index =3D i; - bh[i] =3D qemu_bh_new(a10_pit_timer_cb, tc); - s->timer[i] =3D ptimer_init_with_bh(bh[i], PTIMER_POLICY_DEFAULT); + s->timer[i] =3D ptimer_init(a10_pit_timer_cb, tc, PTIMER_POLICY_DE= FAULT); } } =20 --=20 2.20.1 From nobody Thu Apr 25 18:08:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id z9sm19135541wrl.35.2019.10.08.10.17.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Oct 2019 10:17:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YIQRxGhBJ1X9p2Nl8IBpa05pvQdkYgoMHZ4M5gIxc50=; b=aaFIl2VC5JOv/pFyQjeRHvAwjPepmBx6g920gmzsD4G63E3y8uXibOnKGJDy7hLMie 5dmFkMcnc8DmT/biSoi6QzvwugyESvongUEiXp6VWDrYBjwQag1kXeRIl//MkZspe8KH MkBQQvfTKIkge6MLFnx8M6f2SWAkL1jT+EiX+PDhw8dmXD7zdjSFVU5u88iif+PIMrYZ BnWPbVTgMQI/xYPn0Zt7/rBNtfaLsyBE7PQtHm63sUJlHq/sgoDQHUMiwSlmhsMuLNpC fNnye94oYEpv6x0U9dM3kR7ZT5vbJjTzucamxpuiFZplPQJUVPcIwIU7peoMm682Q2cg o4uQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YIQRxGhBJ1X9p2Nl8IBpa05pvQdkYgoMHZ4M5gIxc50=; b=YuEUBdc6iE3H9Ao8rCjhH9F11Z1bOJCUCS5UW4kLMgm6Ce/UOJRZePVfI5j2MkqtNr RzltF33I8ZQPg6H7ZMw3I4gZLlfZyoD/Bj0CDjEXC8XuGbCwm/t8IxBHsxO8B2hzwEwl UiMkxdj9mz28LPeCKzzxw3NCu2TfBTd8LTTBYZtyUA88P9qzlryCiv/BZMiEXIEuNL/N TR91zXZrlND3OKfMgBdCzZFEZDCYD/BxKCYKRYuatfSc7m8kyVY6MI77X6Q4pMxRp36I LOrMMekbT0Od8WQq6Z2a5ZpnZbtJVKhQ43KwXjfo+hHPHF+Uu8Sr+NICBgums4Q6j0Mw SPbQ== X-Gm-Message-State: APjAAAVekSUt24iXflcwPyxDeuo6ZGT/uC1S5lpqQYs94/9ZYeZNq+AK E8Gkt4g/njpfpBz2tp+yGrwFNw== X-Google-Smtp-Source: APXvYqyVPyEKTdIvhPk5znw+fXSUqe50esP7v+o6Nso1E8n2EU7C238giq2IVw89fKpTUz+z8aLt9A== X-Received: by 2002:a5d:4090:: with SMTP id o16mr10300156wrp.172.1570555072858; Tue, 08 Oct 2019 10:17:52 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 07/21] hw/timer/arm_mptimer.c: Switch to transaction-based ptimer API Date: Tue, 8 Oct 2019 18:17:26 +0100 Message-Id: <20191008171740.9679-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191008171740.9679-1-peter.maydell@linaro.org> References: <20191008171740.9679-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Paolo Bonzini Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Switch the arm_mptimer.c code away from bottom-half based ptimers to the new transaction-based ptimer API. This just requires adding begin/commit calls around the various places that modify the ptimer state, and using the new ptimer_init() function to create the timer. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/timer/arm_mptimer.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/hw/timer/arm_mptimer.c b/hw/timer/arm_mptimer.c index 2a54a011431..fdf97d1800f 100644 --- a/hw/timer/arm_mptimer.c +++ b/hw/timer/arm_mptimer.c @@ -27,7 +27,6 @@ #include "hw/timer/arm_mptimer.h" #include "migration/vmstate.h" #include "qapi/error.h" -#include "qemu/main-loop.h" #include "qemu/module.h" #include "hw/core/cpu.h" =20 @@ -65,6 +64,7 @@ static inline uint32_t timerblock_scale(uint32_t control) return (((control >> 8) & 0xff) + 1) * 10; } =20 +/* Must be called within a ptimer transaction block */ static inline void timerblock_set_count(struct ptimer_state *timer, uint32_t control, uint64_t *count) { @@ -77,6 +77,7 @@ static inline void timerblock_set_count(struct ptimer_sta= te *timer, ptimer_set_count(timer, *count); } =20 +/* Must be called within a ptimer transaction block */ static inline void timerblock_run(struct ptimer_state *timer, uint32_t control, uint32_t load) { @@ -124,6 +125,7 @@ static void timerblock_write(void *opaque, hwaddr addr, uint32_t control =3D tb->control; switch (addr) { case 0: /* Load */ + ptimer_transaction_begin(tb->timer); /* Setting load to 0 stops the timer without doing the tick if * prescaler =3D 0. */ @@ -132,8 +134,10 @@ static void timerblock_write(void *opaque, hwaddr addr, } ptimer_set_limit(tb->timer, value, 1); timerblock_run(tb->timer, control, value); + ptimer_transaction_commit(tb->timer); break; case 4: /* Counter. */ + ptimer_transaction_begin(tb->timer); /* Setting counter to 0 stops the one-shot timer, or periodic with * load =3D 0, without doing the tick if prescaler =3D 0. */ @@ -143,8 +147,10 @@ static void timerblock_write(void *opaque, hwaddr addr, } timerblock_set_count(tb->timer, control, &value); timerblock_run(tb->timer, control, value); + ptimer_transaction_commit(tb->timer); break; case 8: /* Control. */ + ptimer_transaction_begin(tb->timer); if ((control & 3) !=3D (value & 3)) { ptimer_stop(tb->timer); } @@ -160,6 +166,7 @@ static void timerblock_write(void *opaque, hwaddr addr, timerblock_run(tb->timer, value, count); } tb->control =3D value; + ptimer_transaction_commit(tb->timer); break; case 12: /* Interrupt status. */ tb->status &=3D ~value; @@ -212,9 +219,11 @@ static void timerblock_reset(TimerBlock *tb) tb->control =3D 0; tb->status =3D 0; if (tb->timer) { + ptimer_transaction_begin(tb->timer); ptimer_stop(tb->timer); ptimer_set_limit(tb->timer, 0, 1); ptimer_set_period(tb->timer, timerblock_scale(0)); + ptimer_transaction_commit(tb->timer); } } =20 @@ -260,8 +269,7 @@ static void arm_mptimer_realize(DeviceState *dev, Error= **errp) */ for (i =3D 0; i < s->num_cpu; i++) { TimerBlock *tb =3D &s->timerblock[i]; - QEMUBH *bh =3D qemu_bh_new(timerblock_tick, tb); - tb->timer =3D ptimer_init_with_bh(bh, PTIMER_POLICY); + tb->timer =3D ptimer_init(timerblock_tick, tb, PTIMER_POLICY); sysbus_init_irq(sbd, &tb->irq); memory_region_init_io(&tb->iomem, OBJECT(s), &timerblock_ops, tb, "arm_mptimer_timerblock", 0x20); --=20 2.20.1 From nobody Thu Apr 25 18:08:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id z9sm19135541wrl.35.2019.10.08.10.17.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Oct 2019 10:17:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FS9XddmY4om6siRP8IpkPnxKBpobej+L3T9CfHmPAng=; b=qRFXGLXbvtyoSUzGEn+fj6yeidVCtQyNh/Q0vOwOOQVAT2XICV9O2mSbRv4HJZlmId me7/ylz6GbK326jqcbanI7chJnHWEjEGkDy4N6atU4IX5ywsOBjeamJ7Zz3ZxVA65lId tIblyRerbfmQMDTLGc06cXH2wSMgas4dUyTLrGDLnDdnE21Up/yavN7OQozCSVxVgElv SvXVCTYbtIkf4JPb+4dTPppoPYokScoPvqshavXeYk8MlEcGE8yhCUK38iUoSDe0dl9b GsO5kTN3NCTEDGgjEWlsRmfEwK4jyVZtlpJeriz25TP48YgwMQqe2rS3bBtrknyzFEo/ A4mA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FS9XddmY4om6siRP8IpkPnxKBpobej+L3T9CfHmPAng=; b=VUyeRZK2eTO9l5jJosNpt4sPRT8fWmNyrB3d5PqAQGNSCE73sgHKF/LD/bPA13XPvI X4ICJc3ZlXPhbuFfhHhmLhzBKXQ3frgDXLeuVoRpZbSd3HjXzuIf0Hnyeh2BlYIwtkCa k1qy/elvh/8+z/BhIRDVVXgI/w5PbMW9KJ5E4shB9UJF0hmRfANNlGTep1kpaG3DNS8T MVr8FC/vdDqd0VKQ7A9043aPqWhBvjU6AOuMiY55viIKiIRS4LhJIUaQHkQK4p/4do++ 5WcVBFVXINl5LdKLnfgGYQbKWu1e8M2JodK1O8nZx05NMD2oty7QIBQjlkJXTg/08ra7 3rEw== X-Gm-Message-State: APjAAAXdnw9Zf+Zwl/mgHA+wQqdjVhgGu1jAhZ17LTAi/gs645LumMkr LLRT0lpsMT+bQfYCzupN9xzDUg== X-Google-Smtp-Source: APXvYqwUzrBD+ZjtDnAb5Md/JBrYWCRoCeiZEXLpg6S3zvt629siptaW1fXinWJ+fPOYAqYZqLJ68A== X-Received: by 2002:a1c:6a03:: with SMTP id f3mr4514443wmc.167.1570555074057; Tue, 08 Oct 2019 10:17:54 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 08/21] hw/timer/cmsdk-apb-dualtimer.c: Switch to transaction-based ptimer API Date: Tue, 8 Oct 2019 18:17:27 +0100 Message-Id: <20191008171740.9679-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191008171740.9679-1-peter.maydell@linaro.org> References: <20191008171740.9679-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Paolo Bonzini Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Switch the cmsdk-apb-dualtimer code away from bottom-half based ptimers to the new transaction-based ptimer API. This just requires adding begin/commit calls around the various places that modify the ptimer state, and using the new ptimer_init() function to create the timer. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/timer/cmsdk-apb-dualtimer.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/hw/timer/cmsdk-apb-dualtimer.c b/hw/timer/cmsdk-apb-dualtimer.c index 44d23c80364..e28ba9c90a8 100644 --- a/hw/timer/cmsdk-apb-dualtimer.c +++ b/hw/timer/cmsdk-apb-dualtimer.c @@ -20,7 +20,6 @@ #include "qemu/log.h" #include "trace.h" #include "qapi/error.h" -#include "qemu/main-loop.h" #include "qemu/module.h" #include "hw/sysbus.h" #include "hw/irq.h" @@ -112,6 +111,8 @@ static void cmsdk_dualtimermod_write_control(CMSDKAPBDu= alTimerModule *m, /* Handle a write to the CONTROL register */ uint32_t changed; =20 + ptimer_transaction_begin(m->timer); + newctrl &=3D R_CONTROL_VALID_MASK; =20 changed =3D m->control ^ newctrl; @@ -213,6 +214,8 @@ static void cmsdk_dualtimermod_write_control(CMSDKAPBDu= alTimerModule *m, } =20 m->control =3D newctrl; + + ptimer_transaction_commit(m->timer); } =20 static uint64_t cmsdk_apb_dualtimer_read(void *opaque, hwaddr offset, @@ -330,6 +333,7 @@ static void cmsdk_apb_dualtimer_write(void *opaque, hwa= ddr offset, if (!(m->control & R_CONTROL_SIZE_MASK)) { value &=3D 0xffff; } + ptimer_transaction_begin(m->timer); if (!(m->control & R_CONTROL_MODE_MASK)) { /* * In free-running mode this won't set the limit but will @@ -346,6 +350,7 @@ static void cmsdk_apb_dualtimer_write(void *opaque, hwa= ddr offset, ptimer_run(m->timer, 1); } } + ptimer_transaction_commit(m->timer); break; case A_TIMER1BGLOAD: /* Set the limit, but not the current count */ @@ -357,7 +362,9 @@ static void cmsdk_apb_dualtimer_write(void *opaque, hwa= ddr offset, if (!(m->control & R_CONTROL_SIZE_MASK)) { value &=3D 0xffff; } + ptimer_transaction_begin(m->timer); ptimer_set_limit(m->timer, value, 0); + ptimer_transaction_commit(m->timer); break; case A_TIMER1CONTROL: cmsdk_dualtimermod_write_control(m, value); @@ -398,6 +405,7 @@ static void cmsdk_dualtimermod_reset(CMSDKAPBDualTimerM= odule *m) m->intstatus =3D 0; m->load =3D 0; m->value =3D 0xffffffff; + ptimer_transaction_begin(m->timer); ptimer_stop(m->timer); /* * We start in free-running mode, with VALUE at 0xffffffff, and @@ -406,6 +414,7 @@ static void cmsdk_dualtimermod_reset(CMSDKAPBDualTimerM= odule *m) */ ptimer_set_limit(m->timer, 0xffff, 1); ptimer_set_freq(m->timer, m->parent->pclk_frq); + ptimer_transaction_commit(m->timer); } =20 static void cmsdk_apb_dualtimer_reset(DeviceState *dev) @@ -450,10 +459,9 @@ static void cmsdk_apb_dualtimer_realize(DeviceState *d= ev, Error **errp) =20 for (i =3D 0; i < ARRAY_SIZE(s->timermod); i++) { CMSDKAPBDualTimerModule *m =3D &s->timermod[i]; - QEMUBH *bh =3D qemu_bh_new(cmsdk_dualtimermod_tick, m); =20 m->parent =3D s; - m->timer =3D ptimer_init_with_bh(bh, + m->timer =3D ptimer_init(cmsdk_dualtimermod_tick, m, PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD | PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT | PTIMER_POLICY_NO_IMMEDIATE_RELOAD | --=20 2.20.1 From nobody Thu Apr 25 18:08:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id z9sm19135541wrl.35.2019.10.08.10.17.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Oct 2019 10:17:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vTblCPBR00kWBDdHJQrBVtK3r4jiWKjQ3PNlDp1BYo0=; b=R7eTfrLJsXKYaoZP/Ro3jCeyCKMIJz02XWUM7n8bl4bP6tExa0XVBl6wGgan+T7hyW nCBvggFHbDwbBpWcI19VC7G2ZnKv/M9d+FnJYD6cMunO3UMXLkmw7O3zldCR4dLoZU4q PbPmlCQKJ4G7OwIv/BtUWdSdEqwMxXaeI2Z2C65I6R+sabQVLmXJb/P2NGRWfCJK6vzt xOKtDDE/d0rEEDm1mNa9+NMfLODpDahoD0EP9DBsEJ2gSFXRyIutjSs4TdGbLjt9Fs+q 1M+LIZnXrnF9co7ehxMmRVaef9pdJlAPJklbJCQKX3MYCvpuuYgmRS721brE94haTEwm h6qA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vTblCPBR00kWBDdHJQrBVtK3r4jiWKjQ3PNlDp1BYo0=; b=Zi2KMBUBB5BJOeWamkDpIxtzRtByyNVapDKlQ/Z/Q340w7413mlCT7xeTGGHCnNcr+ qscU4a3OzExqeN56JMJGTpAOqCQP9E7cg0gf8BX+W6D0ANFZjEb7NPxYz3kN57V3aewN W+9oItMDzk6/JhD8AqpCk7PlUq9U2CfGhCgsPKJyPdkEZlq7/ihPf4U9xJ4nj6VMamsW D8il1YjaILuYgRneVX60+rpn0bMOs8La3bHzPp+GviP4cEsenUBoJ3SPeCwQRrdj9HZ0 VI9LX60p0P2agyekznLM1lUQn2tQe5jV+jpjpKPkQbvXxikW1vbIUgsYZKHD92QUHbXo WnSQ== X-Gm-Message-State: APjAAAXvWHXsOpLNsOFLerz9daBQFql+oRRBAgsuciWtULg2+dh3Tfxv iuIalbo+6LPByu9+PxtpF7CWwRFAeGbR0g== X-Google-Smtp-Source: APXvYqzKMDEpEVwehuoUPK1bnre3enMh5zFqI+CnNhxSu/cvvChPqARLTgOM4DudF/17xhGUtiHfYw== X-Received: by 2002:a5d:5381:: with SMTP id d1mr11391673wrv.396.1570555075246; Tue, 08 Oct 2019 10:17:55 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 09/21] hw/timer/cmsdk-apb-timer.c: Switch to transaction-based ptimer API Date: Tue, 8 Oct 2019 18:17:28 +0100 Message-Id: <20191008171740.9679-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191008171740.9679-1-peter.maydell@linaro.org> References: <20191008171740.9679-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Paolo Bonzini Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Switch the cmsdk-apb-timer code away from bottom-half based ptimers to the new transaction-based ptimer API. This just requires adding begin/commit calls around the various places that modify the ptimer state, and using the new ptimer_init() function to create the timer. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/timer/cmsdk-apb-timer.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c index c9ce9770cef..40728e85e20 100644 --- a/hw/timer/cmsdk-apb-timer.c +++ b/hw/timer/cmsdk-apb-timer.c @@ -29,7 +29,6 @@ =20 #include "qemu/osdep.h" #include "qemu/log.h" -#include "qemu/main-loop.h" #include "qemu/module.h" #include "qapi/error.h" #include "trace.h" @@ -121,14 +120,17 @@ static void cmsdk_apb_timer_write(void *opaque, hwadd= r offset, uint64_t value, "CMSDK APB timer: EXTIN input not supported\n"); } s->ctrl =3D value & 0xf; + ptimer_transaction_begin(s->timer); if (s->ctrl & R_CTRL_EN_MASK) { ptimer_run(s->timer, ptimer_get_limit(s->timer) =3D=3D 0); } else { ptimer_stop(s->timer); } + ptimer_transaction_commit(s->timer); break; case A_RELOAD: /* Writing to reload also sets the current timer value */ + ptimer_transaction_begin(s->timer); if (!value) { ptimer_stop(s->timer); } @@ -140,8 +142,10 @@ static void cmsdk_apb_timer_write(void *opaque, hwaddr= offset, uint64_t value, */ ptimer_run(s->timer, 0); } + ptimer_transaction_commit(s->timer); break; case A_VALUE: + ptimer_transaction_begin(s->timer); if (!value && !ptimer_get_limit(s->timer)) { ptimer_stop(s->timer); } @@ -149,6 +153,7 @@ static void cmsdk_apb_timer_write(void *opaque, hwaddr = offset, uint64_t value, if (value && (s->ctrl & R_CTRL_EN_MASK)) { ptimer_run(s->timer, ptimer_get_limit(s->timer) =3D=3D 0); } + ptimer_transaction_commit(s->timer); break; case A_INTSTATUS: /* Just one bit, which is W1C. */ @@ -191,9 +196,11 @@ static void cmsdk_apb_timer_reset(DeviceState *dev) trace_cmsdk_apb_timer_reset(); s->ctrl =3D 0; s->intstatus =3D 0; + ptimer_transaction_begin(s->timer); ptimer_stop(s->timer); /* Set the limit and the count */ ptimer_set_limit(s->timer, 0, 1); + ptimer_transaction_commit(s->timer); } =20 static void cmsdk_apb_timer_init(Object *obj) @@ -210,21 +217,21 @@ static void cmsdk_apb_timer_init(Object *obj) static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp) { CMSDKAPBTIMER *s =3D CMSDK_APB_TIMER(dev); - QEMUBH *bh; =20 if (s->pclk_frq =3D=3D 0) { error_setg(errp, "CMSDK APB timer: pclk-frq property must be set"); return; } =20 - bh =3D qemu_bh_new(cmsdk_apb_timer_tick, s); - s->timer =3D ptimer_init_with_bh(bh, + s->timer =3D ptimer_init(cmsdk_apb_timer_tick, s, PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD | PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT | PTIMER_POLICY_NO_IMMEDIATE_RELOAD | PTIMER_POLICY_NO_COUNTER_ROUND_DOWN); =20 + ptimer_transaction_begin(s->timer); ptimer_set_freq(s->timer, s->pclk_frq); + ptimer_transaction_commit(s->timer); } =20 static const VMStateDescription cmsdk_apb_timer_vmstate =3D { --=20 2.20.1 From nobody Thu Apr 25 18:08:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id z9sm19135541wrl.35.2019.10.08.10.17.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Oct 2019 10:17:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WdDJaaZ/rRs7yx03rtQr/OXY2zE5aVv2WsD7FCB9XiQ=; b=Bzpfq2BzeT6i8Poc+l2rSXhqmOGm8dTTj76XumrT9oGnPLL1M+zL++D9E3KgpycklD HU8f218i7bjlUbeuBlBq8ykAvW0UdgMbe+K00Q1f1yU3mc6xQDdinP9897UyPqVRj5J6 SZDOuz6xnlIB3H4mC6ZblzRfvY0CrzFoMA2ykkgFFyjwbnrVObElxdhoP801JFxFIAb1 CIkv4xoKuCVlAjjYdTcqIVB3/jyr7bvFBK/XENEW4U4o0LtHz7itbyEcJRJ6sx33ZyFH J6WfAHyh11e24CbXxsiux1+myW+UURUcGYN08mvq9bSLFCe8SeuqWpeWII8VoYKYxgil uX3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WdDJaaZ/rRs7yx03rtQr/OXY2zE5aVv2WsD7FCB9XiQ=; b=iBTVfU07T+9AgvvLOSxgInZn9diSnwVzE21MdCTCCbX2oLglsx6ajYmhVn7mAF13xo y2gkkErbsmmcj3iZDtgYo0OWOHdc7JYAIJ7MTcMx0Q7D6DBVPqwVgP1wpsjRNkc1inFG CIuD7TQ6IdkTrZ+3QXN4oK3UvditNhUX6DbUT/kOVfBrn2ehZETrFGK2zdw+1aK8tEBJ 54jBBUPBh/Cta7tA4C9iI7oJLKBjVt+EWxXHoDA929j49plNkAPAI8ZWBRixGLEZfGov 9U02ZeAkovjdYUMXQGA1dc5ILqCZHOnS2dPVP9ecBxyc+oaEmAyuwzIMMGI4Yb/JehU8 f0tQ== X-Gm-Message-State: APjAAAXpH3LKaI8bfM9PwaxesUqEvBPTUgPUOkE5MKxMVrym/pxIf/Ct YZm2f7RsEyPvdEiiEfwngOFntQ== X-Google-Smtp-Source: APXvYqzjXXcioyxMpM30PY+4g79HHKyWdeYWISJTF8s0k6k0HqhthLD0PDGSZGVwjBtC9tvceoV5PA== X-Received: by 2002:adf:c58b:: with SMTP id m11mr26761343wrg.252.1570555076363; Tue, 08 Oct 2019 10:17:56 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 10/21] hw/timer/digic-timer.c: Switch to transaction-based ptimer API Date: Tue, 8 Oct 2019 18:17:29 +0100 Message-Id: <20191008171740.9679-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191008171740.9679-1-peter.maydell@linaro.org> References: <20191008171740.9679-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Paolo Bonzini Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Switch the digic-timer.c code away from bottom-half based ptimers to the new transaction-based ptimer API. This just requires adding begin/commit calls around the various places that modify the ptimer state, and using the new ptimer_init() function to create the timer. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/timer/digic-timer.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/hw/timer/digic-timer.c b/hw/timer/digic-timer.c index b111e1fe643..32612228daf 100644 --- a/hw/timer/digic-timer.c +++ b/hw/timer/digic-timer.c @@ -29,7 +29,6 @@ #include "qemu/osdep.h" #include "hw/sysbus.h" #include "hw/ptimer.h" -#include "qemu/main-loop.h" #include "qemu/module.h" #include "qemu/log.h" =20 @@ -52,7 +51,9 @@ static void digic_timer_reset(DeviceState *dev) { DigicTimerState *s =3D DIGIC_TIMER(dev); =20 + ptimer_transaction_begin(s->ptimer); ptimer_stop(s->ptimer); + ptimer_transaction_commit(s->ptimer); s->control =3D 0; s->relvalue =3D 0; } @@ -93,16 +94,20 @@ static void digic_timer_write(void *opaque, hwaddr offs= et, break; } =20 + ptimer_transaction_begin(s->ptimer); if (value & DIGIC_TIMER_CONTROL_EN) { ptimer_run(s->ptimer, 0); } =20 s->control =3D (uint32_t)value; + ptimer_transaction_commit(s->ptimer); break; =20 case DIGIC_TIMER_RELVALUE: s->relvalue =3D extract32(value, 0, 16); + ptimer_transaction_begin(s->ptimer); ptimer_set_limit(s->ptimer, s->relvalue, 1); + ptimer_transaction_commit(s->ptimer); break; =20 case DIGIC_TIMER_VALUE: @@ -125,17 +130,24 @@ static const MemoryRegionOps digic_timer_ops =3D { .endianness =3D DEVICE_NATIVE_ENDIAN, }; =20 +static void digic_timer_tick(void *opaque) +{ + /* Nothing to do on timer rollover */ +} + static void digic_timer_init(Object *obj) { DigicTimerState *s =3D DIGIC_TIMER(obj); =20 - s->ptimer =3D ptimer_init_with_bh(NULL, PTIMER_POLICY_DEFAULT); + s->ptimer =3D ptimer_init(digic_timer_tick, NULL, PTIMER_POLICY_DEFAUL= T); =20 /* * FIXME: there is no documentation on Digic timer * frequency setup so let it always run at 1 MHz */ + ptimer_transaction_begin(s->ptimer); ptimer_set_freq(s->ptimer, 1 * 1000 * 1000); + ptimer_transaction_commit(s->ptimer); =20 memory_region_init_io(&s->iomem, OBJECT(s), &digic_timer_ops, s, TYPE_DIGIC_TIMER, 0x100); --=20 2.20.1 From nobody Thu Apr 25 18:08:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1570556024; cv=none; d=zoho.com; s=zohoarc; b=NYTyO6lRF1DB9RnG1s5R/Z6pSE7oTBP8LJfXhok3Tzbm2rOQ/pNZL1wdkLoTQnMsV3entea9D9J6O4RHeLZ/4at8C+vQICUHapruJ1JzrvqKWXzzgMRIsxREFyx16lc++yMPW8CqQbVXh34y0Mz3Bex9OcYyJ+O5mzPPW6Lw2jM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1570556024; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=YiY1S+jBU4K+H4DP3GSn5UtNtVLHfTSyLgESh8MXV28=; b=RA6DvzOy4XeKpp3a4m8ramF8O+dwaqWWs4Z9yno0jvybGO5AUngbBZUdzymiek+DQzzu0WENAgv50MllKSUJ38kqvdh1PYeRO11ebHyjTcysW1kk2k1q8dexyVcf6/g+JlfREsJ/JEkk73AtWe3DJbJk0zF+opIPJVq3N8WQ7BU= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1570556024248924.0219713572085; Tue, 8 Oct 2019 10:33:44 -0700 (PDT) Received: from localhost ([::1]:59226 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iHtMk-00044z-H7 for importer@patchew.org; Tue, 08 Oct 2019 13:33:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48966) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iHt7a-0006kf-Vv for qemu-devel@nongnu.org; Tue, 08 Oct 2019 13:18:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iHt7Y-0002LX-T1 for qemu-devel@nongnu.org; Tue, 08 Oct 2019 13:18:02 -0400 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:51540) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iHt7W-0002K6-S0 for qemu-devel@nongnu.org; Tue, 08 Oct 2019 13:18:00 -0400 Received: by mail-wm1-x343.google.com with SMTP id 7so4037925wme.1 for ; Tue, 08 Oct 2019 10:17:58 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id z9sm19135541wrl.35.2019.10.08.10.17.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Oct 2019 10:17:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YiY1S+jBU4K+H4DP3GSn5UtNtVLHfTSyLgESh8MXV28=; b=ecS4Wcp0UbmnZiXwvPcoYVZvYu4tk3W01yIyxKhpa6eLqanQCDTtpF/7kR1Y7FnWIg bDxmKAh1R6X7g2VjwR2clVFZFll+7F9KSEoNm4Q9waF79Q7XLfvaCL5H1lhsrzdXKI7t IVi7puAYdpqz+9KxD/tm4knhRmw8r+ARa+xEhUTz0oAB6nNqDQJlTCos3oIm+QbSrLjF cRdH62Uf8skDs3NLZjmEpvsmcswfbqPQiT4exo84qE3Mp/hijJEl+ntJ3s9LQeJ1UICa UtUpkJfaS6/yLFgTz7Eap7WXro7Ehe1LZPCrwqa7bEachhCuCdFO7YnmceH6MnUYQ6Gf hypQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YiY1S+jBU4K+H4DP3GSn5UtNtVLHfTSyLgESh8MXV28=; b=SmYP76xe9AOfji1CnFnCSoRcm5342t4mIGmjflR6AF5dKRlrnWVkfz+yX+ZytJo1cV y61L9IUSwSKGCOvOwCoFzhTCftsX8kJKvIlueEUlXkuHTOVPJQ7Z9vxyznP4zxOWvOD3 9wBrNCNMrd94yKdW/5lYuz5291jV3B2orZU05p3NyMBiH4xQaTexrYKsJ/EuvRp1UN/j 7sr2TxqTfyg72ddo+s10hFA8M7WI+rNzNpBNPayGc/jUj5BzIlMYgV+iCROaw4w7TsTe 19gbMdwkApUMbFlIm4U47duKj4EgTLiSHfrj2bgQVQ6yDGpkJ5aqPd41sYCO0m31j4co vxcQ== X-Gm-Message-State: APjAAAUe1Cht2DMZh1HVqmbxeeM4AZ2MBwT3GgBONssTs0+dglLgNjR7 2E3X+GhkbPAN5DJxAJe7dNXd1A== X-Google-Smtp-Source: APXvYqwNvPtBKi8yl8ZFKOHOcrB2o4U/2n7DMv3aQWbbiaE0VcH+gfEnlRs/3rkwVXOp3gJDU+Dqpw== X-Received: by 2002:a7b:c3cf:: with SMTP id t15mr4494880wmj.85.1570555077751; Tue, 08 Oct 2019 10:17:57 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 11/21] hw/timer/exynos4210_mct.c: Switch GFRC to transaction-based ptimer API Date: Tue, 8 Oct 2019 18:17:30 +0100 Message-Id: <20191008171740.9679-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191008171740.9679-1-peter.maydell@linaro.org> References: <20191008171740.9679-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Paolo Bonzini Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" We want to switch the exynos MCT code away from bottom-half based ptimers to the new transaction-based ptimer API. The MCT is complicated and uses multiple different ptimers, so it's clearer to switch it a piece at a time. Here we change over only the GFRC. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/timer/exynos4210_mct.c | 48 ++++++++++++++++++++++++++++++++++++--- 1 file changed, 45 insertions(+), 3 deletions(-) diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c index 9f2e8dd0a42..fcf91c75cc5 100644 --- a/hw/timer/exynos4210_mct.c +++ b/hw/timer/exynos4210_mct.c @@ -364,6 +364,7 @@ static void exynos4210_mct_update_freq(Exynos4210MCTSta= te *s); =20 /* * Set counter of FRC global timer. + * Must be called within exynos4210_gfrc_tx_begin/commit block. */ static void exynos4210_gfrc_set_count(Exynos4210MCTGT *s, uint64_t count) { @@ -385,6 +386,7 @@ static uint64_t exynos4210_gfrc_get_count(Exynos4210MCT= GT *s) =20 /* * Stop global FRC timer + * Must be called within exynos4210_gfrc_tx_begin/commit block. */ static void exynos4210_gfrc_stop(Exynos4210MCTGT *s) { @@ -395,6 +397,7 @@ static void exynos4210_gfrc_stop(Exynos4210MCTGT *s) =20 /* * Start global FRC timer + * Must be called within exynos4210_gfrc_tx_begin/commit block. */ static void exynos4210_gfrc_start(Exynos4210MCTGT *s) { @@ -403,6 +406,21 @@ static void exynos4210_gfrc_start(Exynos4210MCTGT *s) ptimer_run(s->ptimer_frc, 1); } =20 +/* + * Start ptimer transaction for global FRC timer; this is just for + * consistency with the way we wrap operations like stop and run. + */ +static void exynos4210_gfrc_tx_begin(Exynos4210MCTGT *s) +{ + ptimer_transaction_begin(s->ptimer_frc); +} + +/* Commit ptimer transaction for global FRC timer. */ +static void exynos4210_gfrc_tx_commit(Exynos4210MCTGT *s) +{ + ptimer_transaction_commit(s->ptimer_frc); +} + /* * Find next nearest Comparator. If current Comparator value equals to oth= er * Comparator value, skip them both @@ -492,6 +510,7 @@ static uint64_t exynos4210_gcomp_get_distance(Exynos421= 0MCTState *s, int32_t id) =20 /* * Restart global FRC timer + * Must be called within exynos4210_gfrc_tx_begin/commit block. */ static void exynos4210_gfrc_restart(Exynos4210MCTState *s) { @@ -933,6 +952,19 @@ static void exynos4210_ltick_event(void *opaque) exynos4210_ltick_int_start(&s->tick_timer); } =20 +static void tx_ptimer_set_freq(ptimer_state *s, uint32_t freq) +{ + /* + * callers of exynos4210_mct_update_freq() never do anything + * else that needs to be in the same ptimer transaction, so + * to avoid a lot of repetition we have a convenience function + * for begin/set_freq/commit. + */ + ptimer_transaction_begin(s); + ptimer_set_freq(s, freq); + ptimer_transaction_commit(s); +} + /* update timer frequency */ static void exynos4210_mct_update_freq(Exynos4210MCTState *s) { @@ -945,7 +977,7 @@ static void exynos4210_mct_update_freq(Exynos4210MCTSta= te *s) DPRINTF("freq=3D%dHz\n", s->freq); =20 /* global timer */ - ptimer_set_freq(s->g_timer.ptimer_frc, s->freq); + tx_ptimer_set_freq(s->g_timer.ptimer_frc, s->freq); =20 /* local timer */ ptimer_set_freq(s->l_timer[0].tick_timer.ptimer_tick, s->freq); @@ -965,7 +997,9 @@ static void exynos4210_mct_reset(DeviceState *d) =20 /* global timer */ memset(&s->g_timer.reg, 0, sizeof(s->g_timer.reg)); + exynos4210_gfrc_tx_begin(&s->g_timer); exynos4210_gfrc_stop(&s->g_timer); + exynos4210_gfrc_tx_commit(&s->g_timer); =20 /* local timer */ memset(s->l_timer[0].reg.cnt, 0, sizeof(s->l_timer[0].reg.cnt)); @@ -1144,7 +1178,9 @@ static void exynos4210_mct_write(void *opaque, hwaddr= offset, } =20 s->g_timer.reg.cnt =3D new_frc; + exynos4210_gfrc_tx_begin(&s->g_timer); exynos4210_gfrc_restart(s); + exynos4210_gfrc_tx_commit(&s->g_timer); break; =20 case G_CNT_WSTAT: @@ -1168,7 +1204,9 @@ static void exynos4210_mct_write(void *opaque, hwaddr= offset, s->g_timer.reg.wstat |=3D G_WSTAT_COMP_L(index); } =20 + exynos4210_gfrc_tx_begin(&s->g_timer); exynos4210_gfrc_restart(s); + exynos4210_gfrc_tx_commit(&s->g_timer); break; =20 case G_TCON: @@ -1178,6 +1216,8 @@ static void exynos4210_mct_write(void *opaque, hwaddr= offset, =20 DPRINTF("global timer write to reg.g_tcon %llx\n", value); =20 + exynos4210_gfrc_tx_begin(&s->g_timer); + /* Start FRC if transition from disabled to enabled */ if ((value & G_TCON_TIMER_ENABLE) > (old_val & G_TCON_TIMER_ENABLE)) { @@ -1195,6 +1235,8 @@ static void exynos4210_mct_write(void *opaque, hwaddr= offset, exynos4210_gfrc_restart(s); } } + + exynos4210_gfrc_tx_commit(&s->g_timer); break; =20 case G_INT_CSTAT: @@ -1428,8 +1470,8 @@ static void exynos4210_mct_init(Object *obj) QEMUBH *bh[2]; =20 /* Global timer */ - bh[0] =3D qemu_bh_new(exynos4210_gfrc_event, s); - s->g_timer.ptimer_frc =3D ptimer_init_with_bh(bh[0], PTIMER_POLICY_DEF= AULT); + s->g_timer.ptimer_frc =3D ptimer_init(exynos4210_gfrc_event, s, + PTIMER_POLICY_DEFAULT); memset(&s->g_timer.reg, 0, sizeof(struct gregs)); =20 /* Local timers */ --=20 2.20.1 From nobody Thu Apr 25 18:08:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id z9sm19135541wrl.35.2019.10.08.10.17.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Oct 2019 10:17:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AQvT9vDwvMSeUbPbD+uEtZfbrPLTNxo2MaS4CXHbEVw=; b=ohhpWqFFQHiMPwr97FA20nrcPzPIFqpzJQCRvfq+vE/j6/3P2V2Uo3p6Boe6Hx1XqF 2D7B4fwzZEuaoAF5c4DQl+ZUrPmDVBVHEQlYMXvj9am4n3vDfMRCbmDrBXdm/YLflYR4 xudVSZ3HCJIl/DubdNsUMZGEpab3rRrxqHH30RUzQ5STZgNnD/m0oQd52sicnkpBk7fn rt/NDlxwRBiKa+1jTsy8vEqjIBqzi5Rb6Gpa8zLXcz15RVrzd0x0lud5J4aEXv5mPTEQ oUEIis7FsepQWO/cpdU0Fb+9jaSKY27oXX7GDOHPQO44syRoS4kcetQp7FL4B89kcm6G mmxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AQvT9vDwvMSeUbPbD+uEtZfbrPLTNxo2MaS4CXHbEVw=; b=uasN2YjLlhNueLBK99RcS6QHfP+5lduTMMlFDiZJ+x00mvrs+NtbWmdiLw1/0q7ij0 6LTRv7OrXBiOkmDwQKdZlu8itiqnxFByXuVrm9aqCtXcKCBBajjohi4b02w3SE6i98/J VjRzbN9HCuOk80i/r1KSl8iPjdjYD/hqKa7cji/lAOiCTUk4IYqlXjPg6uKMs6+EyhMX 9iwIjh3mYo/O0rKlTNT6ZzLVUI+WfBOYQSyXjy1G8nt22uvNnO2RvyPW08q0TyoL0nVq N4wA+QGYAlE9fiO4K1mhtN9S03VzJ3tM7dWAuJq2BywNiVw3vRXj3SVX/u2ekLbIcsgF o/fg== X-Gm-Message-State: APjAAAXMgtMoUhGzIPs8YAXuiBV+AYqzL4KoCM5QNu9ry1k0oVibFtXI VFi7/l7pBX0WthjVBUfPF44Low== X-Google-Smtp-Source: APXvYqwLnQqxUnwXDUy7VLBYztYblW/2977UIocdAMkjdLY97bBYDKTYBDyRa52JEvwcfbc/yqzoJg== X-Received: by 2002:a5d:574f:: with SMTP id q15mr16258203wrw.362.1570555079030; Tue, 08 Oct 2019 10:17:59 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 12/21] hw/timer/exynos4210_mct.c: Switch LFRC to transaction-based ptimer API Date: Tue, 8 Oct 2019 18:17:31 +0100 Message-Id: <20191008171740.9679-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191008171740.9679-1-peter.maydell@linaro.org> References: <20191008171740.9679-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Paolo Bonzini Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Switch the exynos MCT LFRC timers over to the ptimer transaction API. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/timer/exynos4210_mct.c | 27 +++++++++++++++++++++++---- 1 file changed, 23 insertions(+), 4 deletions(-) diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c index fcf91c75cc5..82803ef9a02 100644 --- a/hw/timer/exynos4210_mct.c +++ b/hw/timer/exynos4210_mct.c @@ -608,6 +608,7 @@ static uint64_t exynos4210_lfrc_get_count(Exynos4210MCT= LT *s) =20 /* * Set counter of FRC local timer. + * Must be called from within exynos4210_lfrc_tx_begin/commit block. */ static void exynos4210_lfrc_update_count(Exynos4210MCTLT *s) { @@ -620,6 +621,7 @@ static void exynos4210_lfrc_update_count(Exynos4210MCTL= T *s) =20 /* * Start local FRC timer + * Must be called from within exynos4210_lfrc_tx_begin/commit block. */ static void exynos4210_lfrc_start(Exynos4210MCTLT *s) { @@ -628,12 +630,25 @@ static void exynos4210_lfrc_start(Exynos4210MCTLT *s) =20 /* * Stop local FRC timer + * Must be called from within exynos4210_lfrc_tx_begin/commit block. */ static void exynos4210_lfrc_stop(Exynos4210MCTLT *s) { ptimer_stop(s->ptimer_frc); } =20 +/* Start ptimer transaction for local FRC timer */ +static void exynos4210_lfrc_tx_begin(Exynos4210MCTLT *s) +{ + ptimer_transaction_begin(s->ptimer_frc); +} + +/* Commit ptimer transaction for local FRC timer */ +static void exynos4210_lfrc_tx_commit(Exynos4210MCTLT *s) +{ + ptimer_transaction_commit(s->ptimer_frc); +} + /* * Local timer free running counter tick handler */ @@ -981,9 +996,9 @@ static void exynos4210_mct_update_freq(Exynos4210MCTSta= te *s) =20 /* local timer */ ptimer_set_freq(s->l_timer[0].tick_timer.ptimer_tick, s->freq); - ptimer_set_freq(s->l_timer[0].ptimer_frc, s->freq); + tx_ptimer_set_freq(s->l_timer[0].ptimer_frc, s->freq); ptimer_set_freq(s->l_timer[1].tick_timer.ptimer_tick, s->freq); - ptimer_set_freq(s->l_timer[1].ptimer_frc, s->freq); + tx_ptimer_set_freq(s->l_timer[1].ptimer_frc, s->freq); } } =20 @@ -1012,7 +1027,9 @@ static void exynos4210_mct_reset(DeviceState *d) s->l_timer[i].tick_timer.count =3D 0; s->l_timer[i].tick_timer.distance =3D 0; s->l_timer[i].tick_timer.progress =3D 0; + exynos4210_lfrc_tx_begin(&s->l_timer[i]); ptimer_stop(s->l_timer[i].ptimer_frc); + exynos4210_lfrc_tx_commit(&s->l_timer[i]); =20 exynos4210_ltick_timer_init(&s->l_timer[i].tick_timer); } @@ -1316,6 +1333,7 @@ static void exynos4210_mct_write(void *opaque, hwaddr= offset, } =20 /* Start or Stop local FRC if TCON changed */ + exynos4210_lfrc_tx_begin(&s->l_timer[lt_i]); if ((value & L_TCON_FRC_START) > (s->l_timer[lt_i].reg.tcon & L_TCON_FRC_START)) { DPRINTF("local timer[%d] start frc\n", lt_i); @@ -1326,6 +1344,7 @@ static void exynos4210_mct_write(void *opaque, hwaddr= offset, DPRINTF("local timer[%d] stop frc\n", lt_i); exynos4210_lfrc_stop(&s->l_timer[lt_i]); } + exynos4210_lfrc_tx_commit(&s->l_timer[lt_i]); break; =20 case L0_TCNTB: case L1_TCNTB: @@ -1477,11 +1496,11 @@ static void exynos4210_mct_init(Object *obj) /* Local timers */ for (i =3D 0; i < 2; i++) { bh[0] =3D qemu_bh_new(exynos4210_ltick_event, &s->l_timer[i]); - bh[1] =3D qemu_bh_new(exynos4210_lfrc_event, &s->l_timer[i]); s->l_timer[i].tick_timer.ptimer_tick =3D ptimer_init_with_bh(bh[0], PTIMER_POLICY_DEFAULT); s->l_timer[i].ptimer_frc =3D - ptimer_init_with_bh(bh[1], PTIMER_POLICY_DEFAULT); + ptimer_init(exynos4210_lfrc_event, &s->l_timer[i], + PTIMER_POLICY_DEFAULT); s->l_timer[i].id =3D i; } =20 --=20 2.20.1 From nobody Thu Apr 25 18:08:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1570556388; cv=none; d=zoho.com; s=zohoarc; b=EsEKFMs+QDq+XGGoeFYBwHAg9gHivhp8991xlAU+iqL2TH5DUVPCYYj0gFT2lAsrc/bvOrW311/HQRdp8p1rKXE0UsV5eheGN/AAJgMftcEDfxHhC4SAwMESt9Tk/MY9Nu1D1aOc3qx8oCKdYuzDm6n3qmFzHVdik5hrCGIev9Q= ARC-Message-Signature: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id z9sm19135541wrl.35.2019.10.08.10.17.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Oct 2019 10:17:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QW+A6xlbgK0FgzrwM5hDJiZEldqNh8wWGg0ioEj7aAU=; b=BM+7Tp44LjG8NgGZHfvDmDNNWka0Np95L+GTWDj3/fnwbDtoWXWUGRwFBsOwjPH1T9 Q3tt5+/1dRV6Eqf4doZ45IEThOFblKzSSJmv1+bcp85+G0YsGPBVoRxlvvlf2b+KQ7n2 NNBRzg/CFyjHXWnSnfBlAZlM2owFuwq+dcP/7O34mrcVZuShhIWzhYhpGCRJibZbkfXP /QijTH3DZVZ6kftZNG4iNYSkAjnBzRJzVK8tUhG9goXCmzh+a1lB1elxo/m/3Oziti5D Rva7ccFW1IU3oZvfTJGE3oyFuk5Vaj5iNdgOO0R2c2PdSKY09u4aGzrdZDGwy+PAjveb 0Ypw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QW+A6xlbgK0FgzrwM5hDJiZEldqNh8wWGg0ioEj7aAU=; b=PqChwatWNTV42tV5FspTfvbLdrdDkm1my9gnXomZkqk4CiKKLtHjMDXT3Uvdo9UIt2 Y8ozyTHQI8GgXY1dx1Lui6JKAuu85c9BwyDRvWJHyeA4aOCA2cCAhbw/5D7cATFmEtCp Tp1QggPPkTV22u7JeDJw3ivKvdGfNwLU73ibDt+NCzxIOtoqWv2fao5uY62TUEgvpOLo 3ZmSBNDntEovINswHpAI16n86hVoTqCmvXvUE6hobDsfc3jI9Pl9rpw26KItPVUMYvlL lVJ+cNFyKTHqryV7WztD7PdNKO/AC2NWGr4xEVhozVmcqOF5t8hvUjGTbmCkL1t9tmwS 3N1w== X-Gm-Message-State: APjAAAW2+nsNGx3hlwZd8LfgyQXMS/njkAHSzpUjx7nlAb1JKW8hitug u+DIGjr4vzbaZcPld1twm2Vh9g== X-Google-Smtp-Source: APXvYqyesHJeTP3cqY0cgNPJMiB/XCDPtQ8NpEGaFv2BKOK/P8ZBlHx7t8+Xs6WdVRuNtZhIv7UaqQ== X-Received: by 2002:a05:6000:186:: with SMTP id p6mr25899400wrx.136.1570555080350; Tue, 08 Oct 2019 10:18:00 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 13/21] hw/timer/exynos4210_mct.c: Switch ltick to transaction-based ptimer API Date: Tue, 8 Oct 2019 18:17:32 +0100 Message-Id: <20191008171740.9679-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191008171740.9679-1-peter.maydell@linaro.org> References: <20191008171740.9679-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Paolo Bonzini Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Switch the ltick ptimer over to the ptimer transaction API. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/timer/exynos4210_mct.c | 31 +++++++++++++++++++++++++------ 1 file changed, 25 insertions(+), 6 deletions(-) diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c index 82803ef9a02..72257584145 100644 --- a/hw/timer/exynos4210_mct.c +++ b/hw/timer/exynos4210_mct.c @@ -58,7 +58,6 @@ #include "hw/sysbus.h" #include "migration/vmstate.h" #include "qemu/timer.h" -#include "qemu/main-loop.h" #include "qemu/module.h" #include "hw/ptimer.h" =20 @@ -735,6 +734,7 @@ static uint32_t exynos4210_ltick_int_get_cnto(struct ti= ck_timer *s) =20 /* * Start local tick cnt timer. + * Must be called within exynos4210_ltick_tx_begin/commit block. */ static void exynos4210_ltick_cnt_start(struct tick_timer *s) { @@ -750,6 +750,7 @@ static void exynos4210_ltick_cnt_start(struct tick_time= r *s) =20 /* * Stop local tick cnt timer. + * Must be called within exynos4210_ltick_tx_begin/commit block. */ static void exynos4210_ltick_cnt_stop(struct tick_timer *s) { @@ -767,6 +768,18 @@ static void exynos4210_ltick_cnt_stop(struct tick_time= r *s) } } =20 +/* Start ptimer transaction for local tick timer */ +static void exynos4210_ltick_tx_begin(struct tick_timer *s) +{ + ptimer_transaction_begin(s->ptimer_tick); +} + +/* Commit ptimer transaction for local tick timer */ +static void exynos4210_ltick_tx_commit(struct tick_timer *s) +{ + ptimer_transaction_commit(s->ptimer_tick); +} + /* * Get counter for CNT timer */ @@ -812,6 +825,7 @@ static uint32_t exynos4210_ltick_cnt_get_cnto(struct ti= ck_timer *s) =20 /* * Set new values of counters for CNT and INT timers + * Must be called within exynos4210_ltick_tx_begin/commit block. */ static void exynos4210_ltick_set_cntb(struct tick_timer *s, uint32_t new_c= nt, uint32_t new_int) @@ -885,7 +899,9 @@ static void exynos4210_ltick_recalc_count(struct tick_t= imer *s) static void exynos4210_ltick_timer_init(struct tick_timer *s) { exynos4210_ltick_int_stop(s); + exynos4210_ltick_tx_begin(s); exynos4210_ltick_cnt_stop(s); + exynos4210_ltick_tx_commit(s); =20 s->count =3D 0; s->distance =3D 0; @@ -995,9 +1011,9 @@ static void exynos4210_mct_update_freq(Exynos4210MCTSt= ate *s) tx_ptimer_set_freq(s->g_timer.ptimer_frc, s->freq); =20 /* local timer */ - ptimer_set_freq(s->l_timer[0].tick_timer.ptimer_tick, s->freq); + tx_ptimer_set_freq(s->l_timer[0].tick_timer.ptimer_tick, s->freq); tx_ptimer_set_freq(s->l_timer[0].ptimer_frc, s->freq); - ptimer_set_freq(s->l_timer[1].tick_timer.ptimer_tick, s->freq); + tx_ptimer_set_freq(s->l_timer[1].tick_timer.ptimer_tick, s->freq); tx_ptimer_set_freq(s->l_timer[1].ptimer_frc, s->freq); } } @@ -1304,6 +1320,7 @@ static void exynos4210_mct_write(void *opaque, hwaddr= offset, s->l_timer[lt_i].reg.wstat |=3D L_WSTAT_TCON_WRITE; s->l_timer[lt_i].reg.tcon =3D value; =20 + exynos4210_ltick_tx_begin(&s->l_timer[lt_i].tick_timer); /* Stop local CNT */ if ((value & L_TCON_TICK_START) < (old_val & L_TCON_TICK_START)) { @@ -1331,6 +1348,7 @@ static void exynos4210_mct_write(void *opaque, hwaddr= offset, DPRINTF("local timer[%d] start int\n", lt_i); exynos4210_ltick_int_start(&s->l_timer[lt_i].tick_timer); } + exynos4210_ltick_tx_commit(&s->l_timer[lt_i].tick_timer); =20 /* Start or Stop local FRC if TCON changed */ exynos4210_lfrc_tx_begin(&s->l_timer[lt_i]); @@ -1356,8 +1374,10 @@ static void exynos4210_mct_write(void *opaque, hwadd= r offset, * Due to this we should reload timer to nearest moment when CNT is * expired and then in event handler update tcntb to new TCNTB val= ue. */ + exynos4210_ltick_tx_begin(&s->l_timer[lt_i].tick_timer); exynos4210_ltick_set_cntb(&s->l_timer[lt_i].tick_timer, value, s->l_timer[lt_i].tick_timer.icntb); + exynos4210_ltick_tx_commit(&s->l_timer[lt_i].tick_timer); =20 s->l_timer[lt_i].reg.wstat |=3D L_WSTAT_TCNTB_WRITE; s->l_timer[lt_i].reg.cnt[L_REG_CNT_TCNTB] =3D value; @@ -1486,7 +1506,6 @@ static void exynos4210_mct_init(Object *obj) int i; Exynos4210MCTState *s =3D EXYNOS4210_MCT(obj); SysBusDevice *dev =3D SYS_BUS_DEVICE(obj); - QEMUBH *bh[2]; =20 /* Global timer */ s->g_timer.ptimer_frc =3D ptimer_init(exynos4210_gfrc_event, s, @@ -1495,9 +1514,9 @@ static void exynos4210_mct_init(Object *obj) =20 /* Local timers */ for (i =3D 0; i < 2; i++) { - bh[0] =3D qemu_bh_new(exynos4210_ltick_event, &s->l_timer[i]); s->l_timer[i].tick_timer.ptimer_tick =3D - ptimer_init_with_bh(bh[0], PTIMER_POLICY_DEFAULT); + ptimer_init(exynos4210_ltick_event, &s->l_timer[i], + PTIMER_POLICY_DEFAULT); s->l_timer[i].ptimer_frc =3D ptimer_init(exynos4210_lfrc_event, &s->l_timer[i], PTIMER_POLICY_DEFAULT); --=20 2.20.1 From nobody Thu Apr 25 18:08:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id z9sm19135541wrl.35.2019.10.08.10.18.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Oct 2019 10:18:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NFu/MEC+WzwyReIBeXZdHYVan9ju3LNnnVn/p9IiNqo=; b=JHDd5AMvkjN4JVcHK8nTdOzcH5T1Gp/15GkDzhs9qwqhzY2RqVATBDxbxX4qmhS9HL llIwRlCwSKpRPOBHnftVsX+/HZc+zIpJjvUAAtlMrK3iPa4quJGAypH4eNMnBalR4mSJ 0IwDinvB8Z2l41Ykhl9LEhxEwFPOlUkPiy5gSx1cPodxQkBkA3mgyyRQ5skozQorKkP/ kaPOeThKlAR1v10Xp4uhLZHpaQEWuLn+HldUFzTDjXIubXt36E5of6M1+ll6UtcHH7s5 l4NPx80BxtSFMd7caeKjEmysvmHAGAJBRcDQaHl4grcXi9LkatyCnQ/mOvh1kLalAHjK jY5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NFu/MEC+WzwyReIBeXZdHYVan9ju3LNnnVn/p9IiNqo=; b=rjY/8PvukTBVgHFP6XA4Ptx9Nktz2kt8inOBUYX4KJ28Fvf0EMXgaO1nOuR/INiUfB 4/5femXiiQh2eUoIobyqfyJpG3tsxtfmNeeH74vy5PK2MsUEk06sZKgpFvuXIT1NvaSR kXZTCZeVBTyaxV9O9jcNpnTQKmX5soEX1EgLPvRLbF/SbZIhCeqLr0tBhgspthnb6svK ve0LyvZoKfzLpEmBEQCDJUUCbJgVaXf+63zePudYZRWbJVsChbiVgOoStihG8VFdknYO mV8yJqUfmT8XAz2/IbtEw+GethhznBWzYQjHglS1zV7rQcW48L6dKSjuvnHJxJmeCdzl qZvw== X-Gm-Message-State: APjAAAXvKiNU1Kt5NPUp8R+Euw1MnTJ3/OfPTfMSuapngh2I6DFe7Te3 Uhu6wwXWJD8j3y6Q6aMDRg3J/g== X-Google-Smtp-Source: APXvYqxJ5mPExAh9HwyEol0+h02Hx30n4fw5eHQLKtLRFDeiBTKcJvGXcEKz372XeLj1kDe8YUMsKA== X-Received: by 2002:a1c:b745:: with SMTP id h66mr4505556wmf.70.1570555081534; Tue, 08 Oct 2019 10:18:01 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 14/21] hw/timer/exynos4210_pwm.c: Switch to transaction-based ptimer API Date: Tue, 8 Oct 2019 18:17:33 +0100 Message-Id: <20191008171740.9679-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191008171740.9679-1-peter.maydell@linaro.org> References: <20191008171740.9679-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Paolo Bonzini Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Switch the exynos4210_pwm code away from bottom-half based ptimers to the new transaction-based ptimer API. This just requires adding begin/commit calls around the various places that modify the ptimer state, and using the new ptimer_init() function to create the timer. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/timer/exynos4210_pwm.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/hw/timer/exynos4210_pwm.c b/hw/timer/exynos4210_pwm.c index aa5dca68ef7..59a8c08db0f 100644 --- a/hw/timer/exynos4210_pwm.c +++ b/hw/timer/exynos4210_pwm.c @@ -25,7 +25,6 @@ #include "hw/sysbus.h" #include "migration/vmstate.h" #include "qemu/timer.h" -#include "qemu/main-loop.h" #include "qemu/module.h" #include "hw/ptimer.h" =20 @@ -150,7 +149,9 @@ static const VMStateDescription vmstate_exynos4210_pwm_= state =3D { }; =20 /* - * PWM update frequency + * PWM update frequency. + * Must be called within a ptimer_transaction_begin/commit block + * for s->timer[id].ptimer. */ static void exynos4210_pwm_update_freq(Exynos4210PWMState *s, uint32_t id) { @@ -281,12 +282,15 @@ static void exynos4210_pwm_write(void *opaque, hwaddr= offset, =20 /* update timers frequencies */ for (i =3D 0; i < EXYNOS4210_PWM_TIMERS_NUM; i++) { + ptimer_transaction_begin(s->timer[i].ptimer); exynos4210_pwm_update_freq(s, s->timer[i].id); + ptimer_transaction_commit(s->timer[i].ptimer); } break; =20 case TCON: for (i =3D 0; i < EXYNOS4210_PWM_TIMERS_NUM; i++) { + ptimer_transaction_begin(s->timer[i].ptimer); if ((value & TCON_TIMER_MANUAL_UPD(i)) > (s->reg_tcon & TCON_TIMER_MANUAL_UPD(i))) { /* @@ -315,6 +319,7 @@ static void exynos4210_pwm_write(void *opaque, hwaddr o= ffset, ptimer_stop(s->timer[i].ptimer); DPRINTF("stop timer %d\n", i); } + ptimer_transaction_commit(s->timer[i].ptimer); } s->reg_tcon =3D value; break; @@ -369,8 +374,10 @@ static void exynos4210_pwm_reset(DeviceState *d) s->timer[i].reg_tcmpb =3D 0; s->timer[i].reg_tcntb =3D 0; =20 + ptimer_transaction_begin(s->timer[i].ptimer); exynos4210_pwm_update_freq(s, s->timer[i].id); ptimer_stop(s->timer[i].ptimer); + ptimer_transaction_commit(s->timer[i].ptimer); } } =20 @@ -388,12 +395,12 @@ static void exynos4210_pwm_init(Object *obj) Exynos4210PWMState *s =3D EXYNOS4210_PWM(obj); SysBusDevice *dev =3D SYS_BUS_DEVICE(obj); int i; - QEMUBH *bh; =20 for (i =3D 0; i < EXYNOS4210_PWM_TIMERS_NUM; i++) { - bh =3D qemu_bh_new(exynos4210_pwm_tick, &s->timer[i]); sysbus_init_irq(dev, &s->timer[i].irq); - s->timer[i].ptimer =3D ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAU= LT); + s->timer[i].ptimer =3D ptimer_init(exynos4210_pwm_tick, + &s->timer[i], + PTIMER_POLICY_DEFAULT); s->timer[i].id =3D i; s->timer[i].parent =3D s; } --=20 2.20.1 From nobody Thu Apr 25 18:08:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1570556331; cv=none; d=zoho.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id z9sm19135541wrl.35.2019.10.08.10.18.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Oct 2019 10:18:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PYOd0vFS/gYS2A8DyTJAHBtn1FfEmdBSCZ1qScpfiwA=; b=Sw+8Rwp+JVvkoGA81kds513BxAOtOGzaAYuqHSmvsuztgpfgmpNCOn0rsBjvQel+Ha QfDWKdx6SgqNzO2TRtPGXIdSAp3RmtGda+Q9zK5Nny6b6YzE2ELsQ2WZyVEh92yz6Qso whK8ZlzCIhKJX9I+mrynZ9/0eoMcm3zFcNq4hYmxXTbYCa5GMSVZlbj8hl7ZeLtQC+Nl WybL2bsTPMCrYVDoz8buGXfd1qgo3Aw8nJTDha5T7hJVlquEC/JyOpwGBOB1Kq4mMDZf q9Bhc7Ad9v85DCyZqjtokVwZZF2EQqcv0D91GLjkzcsT9BlGZb7gblDTSkVcxpznQKrj QVTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PYOd0vFS/gYS2A8DyTJAHBtn1FfEmdBSCZ1qScpfiwA=; b=BcYzr5XhxkYzTAlv/be9ozcUN1XcxzwzPXfCPiOT71pRSoMK/N5Hi5/SJfA7pnnnC/ 3BESZSc6VsoS4C4peIo3EI5UWu1rYUyZlaR9Yjr8hwDEdg4vRNAgxSYYdySis2aRtL4+ ByhQXy1vjDWv/DfvGwGNAyXksKmKwVFLpJBT51crp2+4MLwpF0fOcmicoOq5VXEsNyTa mK1Omn8cOCfwz8vPW7gjSN0Nz8yeL1XjvWHepmMsICykEH0gO/n/kJf/GGCsNtsRpkRN zvgirO6vac6zmEw1bXyNW+zE9QvttPxw4mhWfOOJyl4yCrxUivKnSGgFMJaXF8VVeKpQ RimQ== X-Gm-Message-State: APjAAAWnJEoKjKJzbfeJ0Itz1AjobWn7wYcri+WSK+/3tBrNhU43kIRb oeG4kerYe+Hq6qZPqbq9cIdLFg== X-Google-Smtp-Source: APXvYqwW/OSAYdKmjJ9sWUoSRGtcCnrSipKaUhWEPl66SaEj0TS/25mfQVgMDb9+TqB41naucRKldQ== X-Received: by 2002:a5d:4a84:: with SMTP id o4mr3844941wrq.165.1570555082655; Tue, 08 Oct 2019 10:18:02 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 15/21] hw/timer/exynos4210_rtc.c: Switch 1Hz ptimer to transaction-based API Date: Tue, 8 Oct 2019 18:17:34 +0100 Message-Id: <20191008171740.9679-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191008171740.9679-1-peter.maydell@linaro.org> References: <20191008171740.9679-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Paolo Bonzini Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Switch the exynos41210_rtc 1Hz ptimer over to the transaction-based API. (We will switch the other ptimer used by this device in a separate commit.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/timer/exynos4210_rtc.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/hw/timer/exynos4210_rtc.c b/hw/timer/exynos4210_rtc.c index d5d7c91fb15..b7ae99e9aa7 100644 --- a/hw/timer/exynos4210_rtc.c +++ b/hw/timer/exynos4210_rtc.c @@ -401,6 +401,7 @@ static void exynos4210_rtc_write(void *opaque, hwaddr o= ffset, } break; case RTCCON: + ptimer_transaction_begin(s->ptimer_1Hz); if (value & RTC_ENABLE) { exynos4210_rtc_update_freq(s, value); } @@ -430,6 +431,7 @@ static void exynos4210_rtc_write(void *opaque, hwaddr o= ffset, ptimer_stop(s->ptimer); } } + ptimer_transaction_commit(s->ptimer_1Hz); s->reg_rtccon =3D value; break; case TICCNT: @@ -539,7 +541,9 @@ static void exynos4210_rtc_reset(DeviceState *d) =20 exynos4210_rtc_update_freq(s, s->reg_rtccon); ptimer_stop(s->ptimer); + ptimer_transaction_begin(s->ptimer_1Hz); ptimer_stop(s->ptimer_1Hz); + ptimer_transaction_commit(s->ptimer_1Hz); } =20 static const MemoryRegionOps exynos4210_rtc_ops =3D { @@ -562,9 +566,11 @@ static void exynos4210_rtc_init(Object *obj) ptimer_set_freq(s->ptimer, RTC_BASE_FREQ); exynos4210_rtc_update_freq(s, 0); =20 - bh =3D qemu_bh_new(exynos4210_rtc_1Hz_tick, s); - s->ptimer_1Hz =3D ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); + s->ptimer_1Hz =3D ptimer_init(exynos4210_rtc_1Hz_tick, + s, PTIMER_POLICY_DEFAULT); + ptimer_transaction_begin(s->ptimer_1Hz); ptimer_set_freq(s->ptimer_1Hz, RTC_BASE_FREQ); + ptimer_transaction_commit(s->ptimer_1Hz); =20 sysbus_init_irq(dev, &s->alm_irq); sysbus_init_irq(dev, &s->tick_irq); --=20 2.20.1 From nobody Thu Apr 25 18:08:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1570556050; cv=none; d=zoho.com; s=zohoarc; b=Yk+U1eK6NyRngEkhPRSa0Na8i46KEgjnLjVNchlqV0XXPZurqG0ImEB7B/feJMlXSEUF7fJWPoSo9o5LkwPqDJ6vXpejo7NTUguvitwl98c4FJNYnCW6WjXbhr8OROUNSa8wE/f9l/9WM2kdeSFbb1wJ5mHIx0X/SRDy9JtWFm0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1570556050; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=YG0gX4qWdrO9GT0PeX8Gop+wch2VyWRSSaF9t3LJ9nc=; b=VsjA7OUICH7+ZRSqHZnHDks+Psz1M9d46Ga8M3GQLK7y4wiyIzhDf/j0xwMtkF3Ff7ztWIzOaPAntmB8uEl9cULfwdedsDdyZ9glURosEgqSqO39wVttRB4y9kkImLt8/0GhLk3xaj3A5ksZGDQLFqCwZiGgjZUkmhSlYbemU6w= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1570556050465751.9448261334794; Tue, 8 Oct 2019 10:34:10 -0700 (PDT) Received: from localhost ([::1]:59242 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iHtN9-0004SE-6b for importer@patchew.org; Tue, 08 Oct 2019 13:34:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49069) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iHt7e-0006ok-L8 for qemu-devel@nongnu.org; Tue, 08 Oct 2019 13:18:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iHt7d-0002Oy-6n for qemu-devel@nongnu.org; Tue, 08 Oct 2019 13:18:06 -0400 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:40682) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iHt7c-0002No-RL for qemu-devel@nongnu.org; Tue, 08 Oct 2019 13:18:05 -0400 Received: by mail-wm1-x343.google.com with SMTP id b24so3925226wmj.5 for ; Tue, 08 Oct 2019 10:18:04 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id z9sm19135541wrl.35.2019.10.08.10.18.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Oct 2019 10:18:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YG0gX4qWdrO9GT0PeX8Gop+wch2VyWRSSaF9t3LJ9nc=; b=TpCIrSAKnC+ubgTuHzcWi7xGznG+/JaMKEd1aE538WLALpO9OSGu+9B7sUshwK4tEU kkFLeaKq1pzihfNMPe41qXO/jk1Lq6L0mmna5gO3jGVQGXL2tpb2scJw5Omm7H/kZBpi exjT5XV4Qy+HFjV40S+zAhmRzRHJVjtLXezbTMkZ33PHOTtCTOlCkbsgJRwnTQrr+oQc uKXFk8NwTc5gnRnjEazCuLBOWQ2+PoEGix6fXuQIsWMfuY2cZ5OAZA3SEDYyFKHnNONt yWi8naR3uF90HtASyOVYNauz7uGwF5MY/NyZQi4SFMHLYTCZKcjMHon5/yOjTJa+Qea9 mUzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YG0gX4qWdrO9GT0PeX8Gop+wch2VyWRSSaF9t3LJ9nc=; b=ep/EA0JkF+P1TSHXmMtYW4U8tCja4VZxkgJzfl5QkX/VKNVMVBgYQQA2WVJMuN3fu2 aJKinTMCUWpWVRvrvXfX9YqJKLo2e8wo1rocPeskzLHfP5EC9JpxcMqwe06BafsK2xgH Sa1pf1J2zKDzcDadNZKvx329dC5SivGbPfIvtwgWvk9XWJlVNtETxXPWTFsCrqySGoaS VpkLkg7uqNQRGic2q/PpiLxiQGwUsuF6mil7WWy/pDffvkCK+TIs0GErp74ZNHdkYnmM OuMZzxrmunw0VD+9cDBIfJspsrohyr5J0vfJF1fPEnOyArlrN1xNDOl4aUht/f0+qBQF rqSw== X-Gm-Message-State: APjAAAXFQmCy/SvPdb+AHGKKU8hq2HvH0gs6gtJWZ7vbwDkGC6Iiwopc B6KDM1+9vFP/7SkNsOqbOT1kDQ== X-Google-Smtp-Source: APXvYqz1+amI1wGizxub69MRVAZm6lD05unmpVsu+Y0zqL+2RvdpLU+lKDO26bgTieaF5a0ZFfr7zA== X-Received: by 2002:a1c:2382:: with SMTP id j124mr5026948wmj.154.1570555083764; Tue, 08 Oct 2019 10:18:03 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 16/21] hw/timer/exynos4210_rtc.c: Switch main ptimer to transaction-based API Date: Tue, 8 Oct 2019 18:17:35 +0100 Message-Id: <20191008171740.9679-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191008171740.9679-1-peter.maydell@linaro.org> References: <20191008171740.9679-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Paolo Bonzini Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Switch the exynos41210_rtc main ptimer over to the transaction-based API, completing the transition for this device. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/timer/exynos4210_rtc.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/hw/timer/exynos4210_rtc.c b/hw/timer/exynos4210_rtc.c index b7ae99e9aa7..f85483a07f8 100644 --- a/hw/timer/exynos4210_rtc.c +++ b/hw/timer/exynos4210_rtc.c @@ -28,7 +28,6 @@ #include "qemu/osdep.h" #include "qemu-common.h" #include "qemu/log.h" -#include "qemu/main-loop.h" #include "qemu/module.h" #include "hw/sysbus.h" #include "migration/vmstate.h" @@ -195,6 +194,7 @@ static void check_alarm_raise(Exynos4210RTCState *s) * RTC update frequency * Parameters: * reg_value - current RTCCON register or his new value + * Must be called within a ptimer_transaction_begin/commit block for s->pt= imer. */ static void exynos4210_rtc_update_freq(Exynos4210RTCState *s, uint32_t reg_value) @@ -402,6 +402,7 @@ static void exynos4210_rtc_write(void *opaque, hwaddr o= ffset, break; case RTCCON: ptimer_transaction_begin(s->ptimer_1Hz); + ptimer_transaction_begin(s->ptimer); if (value & RTC_ENABLE) { exynos4210_rtc_update_freq(s, value); } @@ -432,6 +433,7 @@ static void exynos4210_rtc_write(void *opaque, hwaddr o= ffset, } } ptimer_transaction_commit(s->ptimer_1Hz); + ptimer_transaction_commit(s->ptimer); s->reg_rtccon =3D value; break; case TICCNT: @@ -539,8 +541,10 @@ static void exynos4210_rtc_reset(DeviceState *d) =20 s->reg_curticcnt =3D 0; =20 + ptimer_transaction_begin(s->ptimer); exynos4210_rtc_update_freq(s, s->reg_rtccon); ptimer_stop(s->ptimer); + ptimer_transaction_commit(s->ptimer); ptimer_transaction_begin(s->ptimer_1Hz); ptimer_stop(s->ptimer_1Hz); ptimer_transaction_commit(s->ptimer_1Hz); @@ -559,12 +563,12 @@ static void exynos4210_rtc_init(Object *obj) { Exynos4210RTCState *s =3D EXYNOS4210_RTC(obj); SysBusDevice *dev =3D SYS_BUS_DEVICE(obj); - QEMUBH *bh; =20 - bh =3D qemu_bh_new(exynos4210_rtc_tick, s); - s->ptimer =3D ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); + s->ptimer =3D ptimer_init(exynos4210_rtc_tick, s, PTIMER_POLICY_DEFAUL= T); + ptimer_transaction_begin(s->ptimer); ptimer_set_freq(s->ptimer, RTC_BASE_FREQ); exynos4210_rtc_update_freq(s, 0); + ptimer_transaction_commit(s->ptimer); =20 s->ptimer_1Hz =3D ptimer_init(exynos4210_rtc_1Hz_tick, s, PTIMER_POLICY_DEFAULT); --=20 2.20.1 From nobody Thu Apr 25 18:08:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1570556238; cv=none; d=zoho.com; s=zohoarc; b=Gh9UHjRb31y7aLF7idtoiTyPLX8MntMgtJ+9TCfc2VPbfvRpmqt0l9f5kBTY8O99MhLH2aUoXe9OsBj1ORUWPpTZRLeX/a8uRrMKrx1XqECp8Q5b24ROuCI7lveCHbZbE3w3ZrpG+vSi2lFfUV87IPPmvqw2dE+6tRlF4JwMENs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1570556238; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=IKaS8RTHBXtjU4umm9TxJgozBl5pnbt1z64JULe41fo=; b=oSa3gG/7VcvuNDg/K97uiBW2MxNo9EYqFX7aW0oIi4qKmh/SF5yT1w5xES6xADo9iO28MgjnPVHzLJ9YikTAQCJwq3LcQAsFcOI83JJsF6xUVs+sz+VL6FYJBSwL+C+JBQMZLa5g7LPFJtgqXiJusD+WGoI0x3sy7cKSabZ3J9E= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1570556238324969.2332991844103; Tue, 8 Oct 2019 10:37:18 -0700 (PDT) Received: from localhost ([::1]:59286 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iHtQ9-0006zN-0e for importer@patchew.org; Tue, 08 Oct 2019 13:37:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49111) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iHt7g-0006qG-47 for qemu-devel@nongnu.org; Tue, 08 Oct 2019 13:18:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iHt7e-0002PX-7e for qemu-devel@nongnu.org; Tue, 08 Oct 2019 13:18:07 -0400 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]:40683) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iHt7d-0002PA-VU for qemu-devel@nongnu.org; Tue, 08 Oct 2019 13:18:06 -0400 Received: by mail-wm1-x344.google.com with SMTP id b24so3925283wmj.5 for ; Tue, 08 Oct 2019 10:18:05 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id z9sm19135541wrl.35.2019.10.08.10.18.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Oct 2019 10:18:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IKaS8RTHBXtjU4umm9TxJgozBl5pnbt1z64JULe41fo=; b=Csx+4V13gC3qgDV0eLlT1+8TisjHqgVTeDPEunDMr3qWRh8glQcAJirAXo1X+x7f7z cpTFMeqhvWwonHa4xWTNFzNghuFVIgra+5m9MyEvIgJRmQF0AbpKHfPCinAao9F2X8lO G0f0u3bsukY0VwBRL6tFA74VHqgcwb5d8nMlmqsf7kA6PMgpZ8Ms5SCKARzAfz6gk2Nk MlpLKg7I9Klo5FXiJ60DR4NWMl7OUXwBlLv8avu5mjuWC1jH+EpkAy6r/8fEIX94jIAH m+TkvCbK8GrKQjoFu0ARnagwxZTigqZW6emqz5++4AYj9Y7aUbSe+HBFBb8jKxFyrsJn 4ZgQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IKaS8RTHBXtjU4umm9TxJgozBl5pnbt1z64JULe41fo=; b=JiOfzKeYIgXIeHlm9MvflVMbGcu3OPOIAvdYKSfJxTqU/KL6GOzDOA3oClIC+0UxNT gsLGjZhWPFFIbPQqANgyWGYR5KUYh1hnpwi8zXWjAsEFkAoOWh7Cw2O6e9WODt/RbzAm A8uG94zXDdC9rBfrq/URWLYnxeUoTreG5oGDf0VS4ZXShnnXIVENOG3zeEktj+3dAfWf rZvx5hyZVcW7ndk1/0hr9n+dMA5tan1lW6tfDojjdII3/YM+3NSkd/rZdGBFpQWEZXXO zfzYyet8CsEIR507ydjJiafl6UeKbtE0TehHMyikRk2ffY8xG7JeDUiCPJFGQXCmn53V m4AQ== X-Gm-Message-State: APjAAAW61pGPRkWN0VT7Jl2GvvMeq7TRqNXhu670EUzoK4JGchErxkQj 1wWdayQx0+szttNTEtwDZt8LDw== X-Google-Smtp-Source: APXvYqzDY0CNWKdQ+bPOoT5M6JXegvoHXdiDp+oLrTgLxO5mE1g5EuZxRcnbH6AMEN4rmIhIeilX6w== X-Received: by 2002:a7b:c753:: with SMTP id w19mr4976166wmk.25.1570555084986; Tue, 08 Oct 2019 10:18:04 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 17/21] hw/timer/imx_epit.c: Switch to transaction-based ptimer API Date: Tue, 8 Oct 2019 18:17:36 +0100 Message-Id: <20191008171740.9679-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191008171740.9679-1-peter.maydell@linaro.org> References: <20191008171740.9679-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Paolo Bonzini Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Switch the imx_epit.c code away from bottom-half based ptimers to the new transaction-based ptimer API. This just requires adding begin/commit calls around the various places that modify the ptimer state, and using the new ptimer_init() function to create the timer. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/timer/imx_epit.c | 32 +++++++++++++++++++++++++++----- 1 file changed, 27 insertions(+), 5 deletions(-) diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c index 39810ac8b03..baf6338e1a6 100644 --- a/hw/timer/imx_epit.c +++ b/hw/timer/imx_epit.c @@ -17,7 +17,6 @@ #include "migration/vmstate.h" #include "hw/irq.h" #include "hw/misc/imx_ccm.h" -#include "qemu/main-loop.h" #include "qemu/module.h" #include "qemu/log.h" =20 @@ -74,6 +73,10 @@ static void imx_epit_update_int(IMXEPITState *s) } } =20 +/* + * Must be called from within a ptimer_transaction_begin/commit block + * for both s->timer_cmp and s->timer_reload. + */ static void imx_epit_set_freq(IMXEPITState *s) { uint32_t clksrc; @@ -105,6 +108,8 @@ static void imx_epit_reset(DeviceState *dev) s->lr =3D EPIT_TIMER_MAX; s->cmp =3D 0; s->cnt =3D 0; + ptimer_transaction_begin(s->timer_cmp); + ptimer_transaction_begin(s->timer_reload); /* stop both timers */ ptimer_stop(s->timer_cmp); ptimer_stop(s->timer_reload); @@ -117,6 +122,8 @@ static void imx_epit_reset(DeviceState *dev) /* if the timer is still enabled, restart it */ ptimer_run(s->timer_reload, 0); } + ptimer_transaction_commit(s->timer_cmp); + ptimer_transaction_commit(s->timer_reload); } =20 static uint32_t imx_epit_update_count(IMXEPITState *s) @@ -164,6 +171,7 @@ static uint64_t imx_epit_read(void *opaque, hwaddr offs= et, unsigned size) return reg_value; } =20 +/* Must be called from ptimer_transaction_begin/commit block for s->timer_= cmp */ static void imx_epit_reload_compare_timer(IMXEPITState *s) { if ((s->cr & (CR_EN | CR_OCIEN)) =3D=3D (CR_EN | CR_OCIEN)) { @@ -191,6 +199,8 @@ static void imx_epit_write(void *opaque, hwaddr offset,= uint64_t value, =20 switch (offset >> 2) { case 0: /* CR */ + ptimer_transaction_begin(s->timer_cmp); + ptimer_transaction_begin(s->timer_reload); =20 oldcr =3D s->cr; s->cr =3D value & 0x03ffffff; @@ -231,6 +241,9 @@ static void imx_epit_write(void *opaque, hwaddr offset,= uint64_t value, } else { ptimer_stop(s->timer_cmp); } + + ptimer_transaction_commit(s->timer_cmp); + ptimer_transaction_commit(s->timer_reload); break; =20 case 1: /* SR - ACK*/ @@ -244,6 +257,8 @@ static void imx_epit_write(void *opaque, hwaddr offset,= uint64_t value, case 2: /* LR - set ticks */ s->lr =3D value; =20 + ptimer_transaction_begin(s->timer_cmp); + ptimer_transaction_begin(s->timer_reload); if (s->cr & CR_RLD) { /* Also set the limit if the LRD bit is set */ /* If IOVW bit is set then set the timer value */ @@ -255,12 +270,16 @@ static void imx_epit_write(void *opaque, hwaddr offse= t, uint64_t value, } =20 imx_epit_reload_compare_timer(s); + ptimer_transaction_commit(s->timer_cmp); + ptimer_transaction_commit(s->timer_reload); break; =20 case 3: /* CMP */ s->cmp =3D value; =20 + ptimer_transaction_begin(s->timer_cmp); imx_epit_reload_compare_timer(s); + ptimer_transaction_commit(s->timer_cmp); =20 break; =20 @@ -281,6 +300,11 @@ static void imx_epit_cmp(void *opaque) imx_epit_update_int(s); } =20 +static void imx_epit_reload(void *opaque) +{ + /* No action required on rollover of timer_reload */ +} + static const MemoryRegionOps imx_epit_ops =3D { .read =3D imx_epit_read, .write =3D imx_epit_write, @@ -308,7 +332,6 @@ static void imx_epit_realize(DeviceState *dev, Error **= errp) { IMXEPITState *s =3D IMX_EPIT(dev); SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); - QEMUBH *bh; =20 DPRINTF("\n"); =20 @@ -317,10 +340,9 @@ static void imx_epit_realize(DeviceState *dev, Error *= *errp) 0x00001000); sysbus_init_mmio(sbd, &s->iomem); =20 - s->timer_reload =3D ptimer_init_with_bh(NULL, PTIMER_POLICY_DEFAULT); + s->timer_reload =3D ptimer_init(imx_epit_reload, s, PTIMER_POLICY_DEFA= ULT); =20 - bh =3D qemu_bh_new(imx_epit_cmp, s); - s->timer_cmp =3D ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); + s->timer_cmp =3D ptimer_init(imx_epit_cmp, s, PTIMER_POLICY_DEFAULT); } =20 static void imx_epit_class_init(ObjectClass *klass, void *data) --=20 2.20.1 From nobody Thu Apr 25 18:08:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id z9sm19135541wrl.35.2019.10.08.10.18.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Oct 2019 10:18:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6nsvqi4Uzwusg0ywFGM1w0nIdrA70CDt5J8J4ZUSnF0=; b=vVqr5RLRSOcHUcGvlEnyp75DhJaCjBVVrtKHAyxmr3kyJ3CZNl5IdcAlpSmaTvlEkT baHySrNONEkgAS8XSE5OwCtw5ALHRqL7PfmO7SfwI0F0pPaYn8wzzxCzQk+IvQDsGO+Y ODpW5FMMrJHxXgvFgZSA6x0Ee2Ixq6/5y6a3IhbDiYwwCkIDG7MKDV1as4OabbPBW4wS j6rF8R8ipXjqh6Y9vnEh6Uu5g0Jp3OO8P07fv+iqGIrwIPYPwZaJJSt8oyo4S1Ix2kaX 5wdZD0dE2D4I5ZoE50sxFECjDMRcJ6EGfjD9DMMp4e1mG+rHuCe9MPim8ersxkZvqjY+ Gm2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6nsvqi4Uzwusg0ywFGM1w0nIdrA70CDt5J8J4ZUSnF0=; b=hjKs730xXgb1ntyEmIGXCDNl6k3oexZBEmBz/+93DXXQGzfVT3DbQWDujQe+YdkUX5 raf9foVDOtUtHeC6IfDuuUxz+Wzn97NFPLqIOHIh3FwfqLf3Vx7xpdrPW0FNDqViGR3y Q+x8wZj+tfuLuhELfV3sTuiV3rFMLldS4YWHOaATDBKzOeermOV98wkfhf5fIOXPiUJb 1xOhE1lYuVqK3uoTtknEm/AJeRW2ViDGX486B0HxRFvSs8HffvWZHluuJOri+mmGmgvu GUzjBhkm3wwjoZIBHVMEOhnCPaqn5EtgYXGyGKXw8h+Xi/wKCz/LA/NuElCR82ejrdpm rvqA== X-Gm-Message-State: APjAAAUPvDZdFrcU4or8Q/Cr2FmEm8oz8zak0ak7GcanDEHnNYLNWyMP 9y5lcZJ4tPp5VH5xvov/3dCJTA== X-Google-Smtp-Source: APXvYqyyub6rfJwPu8Dp+4ayE7S51tuHKmAISNBQBk+R9mNsKXulW3lYNoBJNs60Mk52IYVog608JQ== X-Received: by 2002:a5d:4090:: with SMTP id o16mr10300916wrp.172.1570555086158; Tue, 08 Oct 2019 10:18:06 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 18/21] hw/timer/imx_gpt.c: Switch to transaction-based ptimer API Date: Tue, 8 Oct 2019 18:17:37 +0100 Message-Id: <20191008171740.9679-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191008171740.9679-1-peter.maydell@linaro.org> References: <20191008171740.9679-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Paolo Bonzini Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Switch the imx_epit.c code away from bottom-half based ptimers to the new transaction-based ptimer API. This just requires adding begin/commit calls around the various places that modify the ptimer state, and using the new ptimer_init() function to create the timer. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/timer/imx_gpt.c | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/hw/timer/imx_gpt.c b/hw/timer/imx_gpt.c index c535d191292..5c0d9a269ce 100644 --- a/hw/timer/imx_gpt.c +++ b/hw/timer/imx_gpt.c @@ -16,7 +16,6 @@ #include "hw/irq.h" #include "hw/timer/imx_gpt.h" #include "migration/vmstate.h" -#include "qemu/main-loop.h" #include "qemu/module.h" #include "qemu/log.h" =20 @@ -127,6 +126,7 @@ static const IMXClk imx7_gpt_clocks[] =3D { CLK_NONE, /* 111 not defined */ }; =20 +/* Must be called from within ptimer_transaction_begin/commit block */ static void imx_gpt_set_freq(IMXGPTState *s) { uint32_t clksrc =3D extract32(s->cr, GPT_CR_CLKSRC_SHIFT, 3); @@ -167,6 +167,7 @@ static inline uint32_t imx_gpt_find_limit(uint32_t coun= t, uint32_t reg, return timeout; } =20 +/* Must be called from within ptimer_transaction_begin/commit block */ static void imx_gpt_compute_next_timeout(IMXGPTState *s, bool event) { uint32_t timeout =3D GPT_TIMER_MAX; @@ -313,6 +314,7 @@ static uint64_t imx_gpt_read(void *opaque, hwaddr offse= t, unsigned size) =20 static void imx_gpt_reset_common(IMXGPTState *s, bool is_soft_reset) { + ptimer_transaction_begin(s->timer); /* stop timer */ ptimer_stop(s->timer); =20 @@ -350,6 +352,7 @@ static void imx_gpt_reset_common(IMXGPTState *s, bool i= s_soft_reset) if (s->freq && (s->cr & GPT_CR_EN)) { ptimer_run(s->timer, 1); } + ptimer_transaction_commit(s->timer); } =20 static void imx_gpt_soft_reset(DeviceState *dev) @@ -382,6 +385,7 @@ static void imx_gpt_write(void *opaque, hwaddr offset, = uint64_t value, imx_gpt_soft_reset(DEVICE(s)); } else { /* set our freq, as the source might have changed */ + ptimer_transaction_begin(s->timer); imx_gpt_set_freq(s); =20 if ((oldreg ^ s->cr) & GPT_CR_EN) { @@ -397,12 +401,15 @@ static void imx_gpt_write(void *opaque, hwaddr offset= , uint64_t value, ptimer_stop(s->timer); } } + ptimer_transaction_commit(s->timer); } break; =20 case 1: /* Prescaler */ s->pr =3D value & 0xfff; + ptimer_transaction_begin(s->timer); imx_gpt_set_freq(s); + ptimer_transaction_commit(s->timer); break; =20 case 2: /* SR */ @@ -414,13 +421,16 @@ static void imx_gpt_write(void *opaque, hwaddr offset= , uint64_t value, s->ir =3D value & 0x3f; imx_gpt_update_int(s); =20 + ptimer_transaction_begin(s->timer); imx_gpt_compute_next_timeout(s, false); + ptimer_transaction_commit(s->timer); =20 break; =20 case 4: /* OCR1 -- output compare register */ s->ocr1 =3D value; =20 + ptimer_transaction_begin(s->timer); /* In non-freerun mode, reset count when this register is written = */ if (!(s->cr & GPT_CR_FRR)) { s->next_timeout =3D GPT_TIMER_MAX; @@ -429,6 +439,7 @@ static void imx_gpt_write(void *opaque, hwaddr offset, = uint64_t value, =20 /* compute the new timeout */ imx_gpt_compute_next_timeout(s, false); + ptimer_transaction_commit(s->timer); =20 break; =20 @@ -436,7 +447,9 @@ static void imx_gpt_write(void *opaque, hwaddr offset, = uint64_t value, s->ocr2 =3D value; =20 /* compute the new timeout */ + ptimer_transaction_begin(s->timer); imx_gpt_compute_next_timeout(s, false); + ptimer_transaction_commit(s->timer); =20 break; =20 @@ -444,7 +457,9 @@ static void imx_gpt_write(void *opaque, hwaddr offset, = uint64_t value, s->ocr3 =3D value; =20 /* compute the new timeout */ + ptimer_transaction_begin(s->timer); imx_gpt_compute_next_timeout(s, false); + ptimer_transaction_commit(s->timer); =20 break; =20 @@ -484,15 +499,13 @@ static void imx_gpt_realize(DeviceState *dev, Error *= *errp) { IMXGPTState *s =3D IMX_GPT(dev); SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); - QEMUBH *bh; =20 sysbus_init_irq(sbd, &s->irq); memory_region_init_io(&s->iomem, OBJECT(s), &imx_gpt_ops, s, TYPE_IMX_= GPT, 0x00001000); sysbus_init_mmio(sbd, &s->iomem); =20 - bh =3D qemu_bh_new(imx_gpt_timeout, s); - s->timer =3D ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); + s->timer =3D ptimer_init(imx_gpt_timeout, s, PTIMER_POLICY_DEFAULT); } =20 static void imx_gpt_class_init(ObjectClass *klass, void *data) --=20 2.20.1 From nobody Thu Apr 25 18:08:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id z9sm19135541wrl.35.2019.10.08.10.18.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Oct 2019 10:18:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=utJl6lOKI6yGj+1Myezosvn3a88cspPU4H5F4QN8n/0=; b=N0LL/YfI2y+MrFGNlw4C8nWcYSF8E4lRaFlcbC1xXeGfN53mxUEDm51MRrh3FbeQu4 HCgrGEKJrPf7epG2YubFu6Cu+rMkodILuPXLZ70QPPnCzQvWQ8pWDjujjc4BHavDpzUv cAJrxckKI9xEFufW0ldYdNrHDPQRn/2upzKqYO05jaxYXAXeVXI0SfOdC+8VZG34NvNs bFvUJfEdREDP/fQwghCEmD9A+XMfBFriR+LysSLNvCWcTp9tQ526xD2URSwurDlzDbV1 /JptaBJGQf1NXyUzw78rYZWPweTbhsK0YKOu4tg8GkDonfza1F14w/5+/P8VylCds7HI Y8mw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=utJl6lOKI6yGj+1Myezosvn3a88cspPU4H5F4QN8n/0=; b=TFxBAYt1sAX5hUQVUGpTYDfp5KoaGnaoEpQC+u8LQzbgJ9Vmzqv4wPNpHMj0zgd15t Umb0ZQ1a8u+9MylCZIKOTya3CXO3SZvbuQjqmUopauw3kcN4XGEHxXqF5FlkZzLXzc1O N4C4Ylh+tAON30THmzAf3vEAcv8G4/TsaVU6GHwCWPPws9tfnk9C3QelePMpz/ZE/FyD kApKPypVWTdLAMzW6LHQjGqXN9UehpnhtteADJM4BZAJISF0vDMV3AVCA3aFpiGfEHkv zgdLGPnCcowqD7XDIbtmAC08TFQsNAUmfi73YukkzytFRwv/VU3XSsdoQ3y4jIJJ2FsX Qo/A== X-Gm-Message-State: APjAAAVf2GNsgAXz7a44ydHWsi0CzxY6Wo+8/jjh6u0KUkRQokvy8CCI xZKq+xAAXrUgsTFplClfoALlSg== X-Google-Smtp-Source: APXvYqyiiEoUz1ngnhVryKkPamLiz/223hkUkg33scvKYWpYfKtNLuPa84XuMpCxKWt466ZB8Jzx/Q== X-Received: by 2002:a7b:c94a:: with SMTP id i10mr4926860wml.40.1570555087431; Tue, 08 Oct 2019 10:18:07 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 19/21] hw/timer/mss-timerc: Switch to transaction-based ptimer API Date: Tue, 8 Oct 2019 18:17:38 +0100 Message-Id: <20191008171740.9679-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191008171740.9679-1-peter.maydell@linaro.org> References: <20191008171740.9679-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Paolo Bonzini Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Switch the mss-timer code away from bottom-half based ptimers to the new transaction-based ptimer API. This just requires adding begin/commit calls around the various places that modify the ptimer state, and using the new ptimer_init() function to create the timer. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/hw/timer/mss-timer.h | 1 - hw/timer/mss-timer.c | 11 ++++++++--- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/include/hw/timer/mss-timer.h b/include/hw/timer/mss-timer.h index d15d1732f81..e5a784b27e4 100644 --- a/include/hw/timer/mss-timer.h +++ b/include/hw/timer/mss-timer.h @@ -46,7 +46,6 @@ #define R_TIM1_MAX 6 =20 struct Msf2Timer { - QEMUBH *bh; ptimer_state *ptimer; =20 uint32_t regs[R_TIM1_MAX]; diff --git a/hw/timer/mss-timer.c b/hw/timer/mss-timer.c index a34c2402b00..b1c9a805011 100644 --- a/hw/timer/mss-timer.c +++ b/hw/timer/mss-timer.c @@ -24,7 +24,6 @@ */ =20 #include "qemu/osdep.h" -#include "qemu/main-loop.h" #include "qemu/module.h" #include "qemu/log.h" #include "hw/irq.h" @@ -67,6 +66,7 @@ static void timer_update_irq(struct Msf2Timer *st) qemu_set_irq(st->irq, (ier && isr)); } =20 +/* Must be called from within a ptimer_transaction_begin/commit block */ static void timer_update(struct Msf2Timer *st) { uint64_t count; @@ -159,7 +159,9 @@ timer_write(void *opaque, hwaddr offset, switch (addr) { case R_TIM_CTRL: st->regs[R_TIM_CTRL] =3D value; + ptimer_transaction_begin(st->ptimer); timer_update(st); + ptimer_transaction_commit(st->ptimer); break; =20 case R_TIM_RIS: @@ -171,7 +173,9 @@ timer_write(void *opaque, hwaddr offset, case R_TIM_LOADVAL: st->regs[R_TIM_LOADVAL] =3D value; if (st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL) { + ptimer_transaction_begin(st->ptimer); timer_update(st); + ptimer_transaction_commit(st->ptimer); } break; =20 @@ -228,9 +232,10 @@ static void mss_timer_init(Object *obj) for (i =3D 0; i < NUM_TIMERS; i++) { struct Msf2Timer *st =3D &t->timers[i]; =20 - st->bh =3D qemu_bh_new(timer_hit, st); - st->ptimer =3D ptimer_init_with_bh(st->bh, PTIMER_POLICY_DEFAULT); + st->ptimer =3D ptimer_init(timer_hit, st, PTIMER_POLICY_DEFAULT); + ptimer_transaction_begin(st->ptimer); ptimer_set_freq(st->ptimer, t->freq_hz); + ptimer_transaction_commit(st->ptimer); sysbus_init_irq(SYS_BUS_DEVICE(obj), &st->irq); } =20 --=20 2.20.1 From nobody Thu Apr 25 18:08:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1570556975; cv=none; d=zoho.com; s=zohoarc; b=dI0Pl2zjTRwwOOKqtQtkBLQj2Q1y9vpAPWwLEotwe3pxnp+wn4iLGTjezp9BODOofPEir+yWe77JMd9kr+Wf7l88zsh8+2rQs8TGCZwgosfXP3LqtjOMeo0MPy7Ydr666oFMfUbFdvW3mcFJZq7BunwzjzCQd42iZO7h4APzfCU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1570556975; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=w9v8i3Z8RpP3GEkRyZK5PY2Ra4/gXWlier/tTCtR2T0=; b=i/u0lJsvhFJN1WfaAYkbY60Z3QTJbBS4ZA+f+X83t//QFAaaYmTNs1BT1IpS+Tj9eMdOQQCoR6/5s0PKXXkFyyRS7n9dbURGQNVyJT4CQ2MDLH1EvpHRL/BKHnqu7e/tHuLxDdHI5Ii8XZQHm+rjXnRjQVBzYb3CVbVer0SFB1g= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1570556975492835.8483433012585; Tue, 8 Oct 2019 10:49:35 -0700 (PDT) Received: from localhost ([::1]:59484 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iHtc6-000149-E9 for importer@patchew.org; Tue, 08 Oct 2019 13:49:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49180) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iHt7j-0006uE-02 for qemu-devel@nongnu.org; Tue, 08 Oct 2019 13:18:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iHt7h-0002SE-N6 for qemu-devel@nongnu.org; Tue, 08 Oct 2019 13:18:10 -0400 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:42932) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iHt7h-0002Rp-HH for qemu-devel@nongnu.org; Tue, 08 Oct 2019 13:18:09 -0400 Received: by mail-wr1-x441.google.com with SMTP id n14so20286386wrw.9 for ; Tue, 08 Oct 2019 10:18:09 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id z9sm19135541wrl.35.2019.10.08.10.18.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Oct 2019 10:18:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=w9v8i3Z8RpP3GEkRyZK5PY2Ra4/gXWlier/tTCtR2T0=; b=uu3mMPxnTsZkR066RpXGGzyAATRaGZCoNsy5bswUmDUQ18p7+G/h/T/1XD6U7pDbH9 HKfp1HQx/56U00GWWh8BdVx2L5zSuJ7HynrD0/geTmsoAKWpzIoOjDhJH4/Ws72EAQVV rObpKPgnqmEInsrRy+B60k7+pRQODWZ8WYVlH2FEaMQ/e4yWNlbmK92TQZNj6G1fazHc ZPm4WQzRI5uKkytYpgJsBTKedj7wFWgERhaqDCinEf+Zhkf99/BcSkeQ6Xri9axIPulL sW+UQhinO9uIOTwS0oR1enCeos3A8nQfUH1cxSqscjAoaynTpCXPGQ3EUQnkSZAAKAF2 Eb0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=w9v8i3Z8RpP3GEkRyZK5PY2Ra4/gXWlier/tTCtR2T0=; b=LKYysoyi0TTbP56sdfcy6B6OL31AbukjK73LKffR6XpA0ilI1NypTrCb4xeAt4Unsr DAto/0D8ZRsA+VkymMwvtsZar1tCuCDXz6FPKZy5OtFkLai1ftljZaT3ATtB/qtkdL1A ZJvEJ378fIymV6ySkvSlzPdEN5+5l8h/idcpq2ox15XDqBhLuii4CJch/Y6pcklRJEjI YQtskr/lKQ2r0yN/LrvqobbSAk57lYljwvvP9+BhZmoRUOPvMXwbH7saTnUIsvI2HLZL cdRK3KpexXAwDk5nNZeWmhc+gxv2GFn83T/4AYBAxPz+FzNRoEm1Bid7twJCmL0imlEM 8weA== X-Gm-Message-State: APjAAAWWCtZMdzuNFHuxYgPIc4iv/SLAjXK6OEhHygWhSKPBN8aEhUGz VGLk/k+0PmvKmkyKeaOeKT2w6A== X-Google-Smtp-Source: APXvYqyU7FJIusM6SbN9sPKdDx0W4GA3Kb31qFguRiTGVUk01/WLc0aQtwogHjE4QJaTosyNxgI+Aw== X-Received: by 2002:adf:b3d2:: with SMTP id x18mr29381135wrd.264.1570555088581; Tue, 08 Oct 2019 10:18:08 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 20/21] hw/watchdog/cmsdk-apb-watchdog.c: Switch to transaction-based ptimer API Date: Tue, 8 Oct 2019 18:17:39 +0100 Message-Id: <20191008171740.9679-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191008171740.9679-1-peter.maydell@linaro.org> References: <20191008171740.9679-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Paolo Bonzini Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Switch the cmsdk-apb-watchdog code away from bottom-half based ptimers to the new transaction-based ptimer API. This just requires adding begin/commit calls around the various places that modify the ptimer state, and using the new ptimer_init() function to create the timer. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/watchdog/cmsdk-apb-watchdog.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/hw/watchdog/cmsdk-apb-watchdog.c b/hw/watchdog/cmsdk-apb-watch= dog.c index e42c3ebd29d..e6f3b93c44e 100644 --- a/hw/watchdog/cmsdk-apb-watchdog.c +++ b/hw/watchdog/cmsdk-apb-watchdog.c @@ -24,7 +24,6 @@ #include "qemu/log.h" #include "trace.h" #include "qapi/error.h" -#include "qemu/main-loop.h" #include "qemu/module.h" #include "sysemu/watchdog.h" #include "hw/sysbus.h" @@ -200,8 +199,10 @@ static void cmsdk_apb_watchdog_write(void *opaque, hwa= ddr offset, * Reset the load value and the current count, and make sure * we're counting. */ + ptimer_transaction_begin(s->timer); ptimer_set_limit(s->timer, value, 1); ptimer_run(s->timer, 0); + ptimer_transaction_commit(s->timer); break; case A_WDOGCONTROL: if (s->is_luminary && 0 !=3D (R_WDOGCONTROL_INTEN_MASK & s->contro= l)) { @@ -217,7 +218,9 @@ static void cmsdk_apb_watchdog_write(void *opaque, hwad= dr offset, break; case A_WDOGINTCLR: s->intstatus =3D 0; + ptimer_transaction_begin(s->timer); ptimer_set_count(s->timer, ptimer_get_limit(s->timer)); + ptimer_transaction_commit(s->timer); cmsdk_apb_watchdog_update(s); break; case A_WDOGLOCK: @@ -299,8 +302,10 @@ static void cmsdk_apb_watchdog_reset(DeviceState *dev) s->itop =3D 0; s->resetstatus =3D 0; /* Set the limit and the count */ + ptimer_transaction_begin(s->timer); ptimer_set_limit(s->timer, 0xffffffff, 1); ptimer_run(s->timer, 0); + ptimer_transaction_commit(s->timer); } =20 static void cmsdk_apb_watchdog_init(Object *obj) @@ -320,7 +325,6 @@ static void cmsdk_apb_watchdog_init(Object *obj) static void cmsdk_apb_watchdog_realize(DeviceState *dev, Error **errp) { CMSDKAPBWatchdog *s =3D CMSDK_APB_WATCHDOG(dev); - QEMUBH *bh; =20 if (s->wdogclk_frq =3D=3D 0) { error_setg(errp, @@ -328,14 +332,15 @@ static void cmsdk_apb_watchdog_realize(DeviceState *d= ev, Error **errp) return; } =20 - bh =3D qemu_bh_new(cmsdk_apb_watchdog_tick, s); - s->timer =3D ptimer_init_with_bh(bh, + s->timer =3D ptimer_init(cmsdk_apb_watchdog_tick, s, PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD | PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT | PTIMER_POLICY_NO_IMMEDIATE_RELOAD | PTIMER_POLICY_NO_COUNTER_ROUND_DOWN); =20 + ptimer_transaction_begin(s->timer); ptimer_set_freq(s->timer, s->wdogclk_frq); + ptimer_transaction_commit(s->timer); } =20 static const VMStateDescription cmsdk_apb_watchdog_vmstate =3D { --=20 2.20.1 From nobody Thu Apr 25 18:08:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1570557092; cv=none; d=zoho.com; s=zohoarc; b=XGw1zveZbjlyukWjKt6qg7LhGGIy+gUGsfw+0BXiTQpbYoErZjY4QHFSEK3Q6KRNbm5T/rNjqXPaw6nT8EHXQwyvnr/xCrxfVHzScqGdeUNotdIgxe5l8ByWxNcHf+vs8mzPgaVVV6Z6jFnpq8MiOICTqPdh3/lKruuQ7b6wM6w= ARC-Message-Signature: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id z9sm19135541wrl.35.2019.10.08.10.18.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Oct 2019 10:18:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=meYD3iu+SqBh5zzbJLsZrb0S302wohjRCr6pGE0T3yQ=; b=H8pXsMwdnFTERlEMgNCj9E+kEDcEH9WKgDy1O27HZmsLslyMNGkegSx71gY5fnQ1Mu uNxAOlnihYFw1PJA5IaK2/AA+Mb1RdG6i9YfzbOUhpSj/x/LW+OPSeRtxo4TKb/gBvmV HoTcC6mVAMSpgIv5hWlt1M5LCOf8AqSmLoTI6VbTHzn+xfLvZ/gmL5BJIwhdpbrca29Q a1x8AB00i7ZJMu4XRWhhytllKZR8f7qttFnodKMqYMdWRT2hRvINqe2zoKr2eGwUJ2c0 4h9N7NELr8/686UY6gvIEIz4gEQ3T+0pBG7YxIBEg/RDH21RU4PFECfbOwYpCchWpwrV F+BQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=meYD3iu+SqBh5zzbJLsZrb0S302wohjRCr6pGE0T3yQ=; b=C52ntmC1fUqbzVgDdUDKHxMJlwZsiTF/sa+jjeNld+L7HYHzFOMZbEQ0tF1pNRlEQG IxC9sanE3bNxt3IxUy5bTMPzhAlDJ96WRsIDDx1+s+OZVgNKpN8y6oq8+19PE2fMGl49 V7Bfk5IzAxLjTv1xhKgf5UNUserwuw+Q328vuvWHjvsvcaRlqqDh2YBBvO7XuO3MFa6e DNyRtiLsuV29yjwq2VU5wYagG1zGyyxklEIhNroBBrPhiqIM96HiYSmpBk0GgbGp4n/o CRLqoxqS0vPUMmZ2dBiBp6Xob1eM5kd/ei4VU8rX8f5wWXVkwJajRI1wScrKwgdMVYZQ ONHg== X-Gm-Message-State: APjAAAWlLiJlyeihku9HZ1YQ/bZWD4yqIi6yfJL3XmklV4KQ61KkKgg3 cyyT4HOowIzGF3npTAXaXmLKug== X-Google-Smtp-Source: APXvYqzQo4uV3ZAGpZhIjum9TlMLdDZNun0ciWrlrbEZY3x83+LJuFP7R9AW1OMXp34IwY6LkZ5HcA== X-Received: by 2002:adf:f684:: with SMTP id v4mr25276739wrp.155.1570555089730; Tue, 08 Oct 2019 10:18:09 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 21/21] hw/net/lan9118.c: Switch to transaction-based ptimer API Date: Tue, 8 Oct 2019 18:17:40 +0100 Message-Id: <20191008171740.9679-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191008171740.9679-1-peter.maydell@linaro.org> References: <20191008171740.9679-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Paolo Bonzini Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Switch the cmsdk-apb-watchdog code away from bottom-half based ptimers to the new transaction-based ptimer API. This just requires adding begin/commit calls around the various places that modify the ptimer state, and using the new ptimer_init() function to create the timer. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/net/lan9118.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c index 0ea51433dca..ed551f2178b 100644 --- a/hw/net/lan9118.c +++ b/hw/net/lan9118.c @@ -21,7 +21,6 @@ #include "hw/ptimer.h" #include "hw/qdev-properties.h" #include "qemu/log.h" -#include "qemu/main-loop.h" #include "qemu/module.h" /* For crc32 */ #include @@ -450,8 +449,10 @@ static void lan9118_reset(DeviceState *d) s->e2p_data =3D 0; s->free_timer_start =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / 40; =20 + ptimer_transaction_begin(s->timer); ptimer_stop(s->timer); ptimer_set_count(s->timer, 0xffff); + ptimer_transaction_commit(s->timer); s->gpt_cfg =3D 0xffff; =20 s->mac_cr =3D MAC_CR_PRMS; @@ -1100,6 +1101,7 @@ static void lan9118_writel(void *opaque, hwaddr offse= t, break; case CSR_GPT_CFG: if ((s->gpt_cfg ^ val) & GPT_TIMER_EN) { + ptimer_transaction_begin(s->timer); if (val & GPT_TIMER_EN) { ptimer_set_count(s->timer, val & 0xffff); ptimer_run(s->timer, 0); @@ -1107,6 +1109,7 @@ static void lan9118_writel(void *opaque, hwaddr offse= t, ptimer_stop(s->timer); ptimer_set_count(s->timer, 0xffff); } + ptimer_transaction_commit(s->timer); } s->gpt_cfg =3D val & (GPT_TIMER_EN | 0xffff); break; @@ -1328,7 +1331,6 @@ static void lan9118_realize(DeviceState *dev, Error *= *errp) { SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); lan9118_state *s =3D LAN9118(dev); - QEMUBH *bh; int i; const MemoryRegionOps *mem_ops =3D s->mode_16bit ? &lan9118_16bit_mem_ops : &lan9118_mem_ops; @@ -1349,10 +1351,11 @@ static void lan9118_realize(DeviceState *dev, Error= **errp) s->pmt_ctrl =3D 1; s->txp =3D &s->tx_packet; =20 - bh =3D qemu_bh_new(lan9118_tick, s); - s->timer =3D ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); + s->timer =3D ptimer_init(lan9118_tick, s, PTIMER_POLICY_DEFAULT); + ptimer_transaction_begin(s->timer); ptimer_set_freq(s->timer, 10000); ptimer_set_limit(s->timer, 0xffff, 1); + ptimer_transaction_commit(s->timer); } =20 static Property lan9118_properties[] =3D { --=20 2.20.1