From nobody Thu Apr 25 09:05:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1570544956; cv=none; d=zoho.com; s=zohoarc; b=a/EWw3oUM9EMvlPdsHX4M6IB6HuWzXdkfUQxFc64PtA5Jzn6/NObCzwTVlBp66+lL7XvxB5fFXoCF9OJxUEAhAjOLF2ery3PG+E3ROeAbcZJxuFOPA/B0VHtqCXauqQ4h50/7BosqQ5eo6TwFcgsPjeII/49H07QzC/tCgdq6n0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1570544956; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=sDbXzIS1Se+QTfpJNuy7szMpKrhpQ/d3eaMgNbT88Nk=; b=Y0fC0w8NNPU/g+uj4Aiassxq9JqUVJptuOmhvan4kx7esIRCdthERz0ltP+TCZ3s0n8sz/Ma3wRz0/Q+vhGrZE01sm/0Yvl/jZc1eSY1aE9hdLJEQpLSqA349bCCqrzJrmt9hTIeusuKzCCdbLlW5vrvMQOWdi7Z0Sm7a/YXWmI= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1570544956758986.1045150155403; Tue, 8 Oct 2019 07:29:16 -0700 (PDT) Received: from localhost ([::1]:56630 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iHqUC-0008SG-70 for importer@patchew.org; Tue, 08 Oct 2019 10:29:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49927) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iHqRW-0006DW-1o for qemu-devel@nongnu.org; Tue, 08 Oct 2019 10:26:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iHqRU-0008QP-Oa for qemu-devel@nongnu.org; Tue, 08 Oct 2019 10:26:25 -0400 Received: from mx1.redhat.com ([209.132.183.28]:10503) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iHqRP-0008OI-Cx; Tue, 08 Oct 2019 10:26:19 -0400 Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 8330710DCC9C; Tue, 8 Oct 2019 14:26:18 +0000 (UTC) Received: from x1w.redhat.com (ovpn-204-43.brq.redhat.com [10.40.204.43]) by smtp.corp.redhat.com (Postfix) with ESMTPS id C81CD19C69; Tue, 8 Oct 2019 14:26:00 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Eduardo Habkost , qemu-devel@nongnu.org Subject: [PATCH v2 1/8] hw/acpi/piix4: Convert reset handler to DeviceReset Date: Tue, 8 Oct 2019 16:25:32 +0200 Message-Id: <20191008142539.7793-2-philmd@redhat.com> In-Reply-To: <20191008142539.7793-1-philmd@redhat.com> References: <20191008142539.7793-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.6.2 (mx1.redhat.com [10.5.110.64]); Tue, 08 Oct 2019 14:26:18 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-block@nongnu.org, "Michael S. Tsirkin" , Aleksandar Rikalo , John Snow , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, qemu-ppc@nongnu.org, Aleksandar Markovic , Igor Mammedov , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The PIIX4/PM is a PCI device within the PIIX4 chipset, it will be reset when the PCI bus it stands on is reset. Convert its reset handler into a proper Device reset method. Reviewed-by: Igor Mammedov Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Li Qiang Reviewed-by: Michael S. Tsirkin --- hw/acpi/piix4.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c index 5742c3df87..4e079b39bd 100644 --- a/hw/acpi/piix4.c +++ b/hw/acpi/piix4.c @@ -27,7 +27,6 @@ #include "hw/pci/pci.h" #include "hw/qdev-properties.h" #include "hw/acpi/acpi.h" -#include "sysemu/reset.h" #include "sysemu/runstate.h" #include "sysemu/sysemu.h" #include "qapi/error.h" @@ -344,9 +343,9 @@ static const VMStateDescription vmstate_acpi =3D { } }; =20 -static void piix4_reset(void *opaque) +static void piix4_pm_reset(DeviceState *dev) { - PIIX4PMState *s =3D opaque; + PIIX4PMState *s =3D PIIX4_PM(dev); PCIDevice *d =3D PCI_DEVICE(s); uint8_t *pci_conf =3D d->config; =20 @@ -542,7 +541,6 @@ static void piix4_pm_realize(PCIDevice *dev, Error **er= rp) =20 s->machine_ready.notify =3D piix4_pm_machine_ready; qemu_add_machine_init_done_notifier(&s->machine_ready); - qemu_register_reset(piix4_reset, s); =20 piix4_acpi_system_hot_add_init(pci_address_space_io(dev), pci_get_bus(dev), s); @@ -692,6 +690,7 @@ static void piix4_pm_class_init(ObjectClass *klass, voi= d *data) k->device_id =3D PCI_DEVICE_ID_INTEL_82371AB_3; k->revision =3D 0x03; k->class_id =3D PCI_CLASS_BRIDGE_OTHER; + dc->reset =3D piix4_pm_reset; dc->desc =3D "PM"; dc->vmsd =3D &vmstate_acpi; dc->props =3D piix4_pm_properties; --=20 2.21.0 From nobody Thu Apr 25 09:05:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1570546174; cv=none; d=zoho.com; s=zohoarc; b=eg0ygknxJm83gXkP0+xlaoT9qlrk6qwsXpT2J5+HrboczrDr+K+LRpiIzcienetW6Ejr94iSCPfd5rjzlpFacZgcDQRiMXhaOcmn8jFPUGaMBuMbGHK16BOnEQtsC536t2QXn9kpUds2YQ66wBEx71s/ViesuVh9JTqrUy9DGaM= ARC-Message-Signature: i=1; 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Tue, 8 Oct 2019 14:26:18 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Eduardo Habkost , qemu-devel@nongnu.org Subject: [PATCH v2 2/8] hw/isa/piix4: Convert reset handler to DeviceReset Date: Tue, 8 Oct 2019 16:25:33 +0200 Message-Id: <20191008142539.7793-3-philmd@redhat.com> In-Reply-To: <20191008142539.7793-1-philmd@redhat.com> References: <20191008142539.7793-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.31]); Tue, 08 Oct 2019 14:26:27 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-block@nongnu.org, "Michael S. Tsirkin" , Aleksandar Rikalo , John Snow , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, qemu-ppc@nongnu.org, Aleksandar Markovic , Igor Mammedov , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The PIIX4/ISA is a PCI device within the PIIX4 chipset, it will be reset when the PCI bus it stands on is reset. Convert its reset handler into a proper Device reset method. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Li Qiang --- hw/isa/piix4.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 3294056cd5..890d999abf 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -28,7 +28,6 @@ #include "hw/isa/isa.h" #include "hw/sysbus.h" #include "migration/vmstate.h" -#include "sysemu/reset.h" =20 PCIDevice *piix4_dev; =20 @@ -40,9 +39,9 @@ typedef struct PIIX4State { #define PIIX4_PCI_DEVICE(obj) \ OBJECT_CHECK(PIIX4State, (obj), TYPE_PIIX4_PCI_DEVICE) =20 -static void piix4_reset(void *opaque) +static void piix4_isa_reset(DeviceState *dev) { - PIIX4State *d =3D opaque; + PIIX4State *d =3D PIIX4_PCI_DEVICE(dev); uint8_t *pci_conf =3D d->dev.config; =20 pci_conf[0x04] =3D 0x07; // master, memory and I/O @@ -97,7 +96,6 @@ static void piix4_realize(PCIDevice *dev, Error **errp) return; } piix4_dev =3D &d->dev; - qemu_register_reset(piix4_reset, d); } =20 int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn) @@ -118,6 +116,7 @@ static void piix4_class_init(ObjectClass *klass, void *= data) k->vendor_id =3D PCI_VENDOR_ID_INTEL; k->device_id =3D PCI_DEVICE_ID_INTEL_82371AB_0; k->class_id =3D PCI_CLASS_BRIDGE_ISA; + dc->reset =3D piix4_isa_reset; dc->desc =3D "ISA bridge"; dc->vmsd =3D &vmstate_piix4; /* --=20 2.21.0 From nobody Thu Apr 25 09:05:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1570545200; cv=none; d=zoho.com; s=zohoarc; b=RLC165ZtpjtQAAotREbX2J/z2IK2g23Kg9bvm5S9w7+7W5EQcQQI+ea3VPgU1DpsgmSbFf/wxOVCI7jPi0MPF6rG3Ov2ctJac2zNQH7R5CUMO9rKURLpuVXkFG/MAn8smzXOnNFdKOqoJwxdPW9gSnmU1AlSSf8kfGkbtYgzSbk= ARC-Message-Signature: i=1; a=rsa-sha256; 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Tue, 8 Oct 2019 14:26:27 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Eduardo Habkost , qemu-devel@nongnu.org Subject: [PATCH v2 3/8] hw/ide/piix: Convert reset handler to DeviceReset Date: Tue, 8 Oct 2019 16:25:34 +0200 Message-Id: <20191008142539.7793-4-philmd@redhat.com> In-Reply-To: <20191008142539.7793-1-philmd@redhat.com> References: <20191008142539.7793-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.27]); Tue, 08 Oct 2019 14:26:40 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-block@nongnu.org, "Michael S. Tsirkin" , Aleksandar Rikalo , John Snow , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, qemu-ppc@nongnu.org, Aleksandar Markovic , Igor Mammedov , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The PIIX3/IDE is a PCI device within the PIIX3 chipset, it will be reset when the PCI bus it stands on is reset. Convert its reset handler into a proper Device reset method. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/ide/piix.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/hw/ide/piix.c b/hw/ide/piix.c index fba6bc8bff..18b2c3b722 100644 --- a/hw/ide/piix.c +++ b/hw/ide/piix.c @@ -30,7 +30,6 @@ #include "sysemu/block-backend.h" #include "sysemu/blockdev.h" #include "sysemu/dma.h" -#include "sysemu/reset.h" =20 #include "hw/ide/pci.h" #include "trace.h" @@ -103,9 +102,9 @@ static void bmdma_setup_bar(PCIIDEState *d) } } =20 -static void piix3_reset(void *opaque) +static void piix3_ide_reset(DeviceState *dev) { - PCIIDEState *d =3D opaque; + PCIIDEState *d =3D PCI_IDE(dev); PCIDevice *pd =3D PCI_DEVICE(d); uint8_t *pci_conf =3D pd->config; int i; @@ -154,8 +153,6 @@ static void pci_piix_ide_realize(PCIDevice *dev, Error = **errp) =20 pci_conf[PCI_CLASS_PROG] =3D 0x80; // legacy ATA mode =20 - qemu_register_reset(piix3_reset, d); - bmdma_setup_bar(d); pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar); =20 @@ -247,6 +244,7 @@ static void piix3_ide_class_init(ObjectClass *klass, vo= id *data) DeviceClass *dc =3D DEVICE_CLASS(klass); PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); =20 + dc->reset =3D piix3_ide_reset; k->realize =3D pci_piix_ide_realize; k->exit =3D pci_piix_ide_exitfn; k->vendor_id =3D PCI_VENDOR_ID_INTEL; --=20 2.21.0 From nobody Thu Apr 25 09:05:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1570545196; cv=none; d=zoho.com; s=zohoarc; b=lyRWYil1dL0+Hc1PVFOMVyT2gccW3RQQEWA7ColItgq40XkBYKwSk3E9RfZtYi+XVRH1SJXPkqS83134zf+Nq2eRlPJwXtau64+eezsPpc2GuzgQE3+EwGZvYLpxMhIJYzkyd+qIRSjLtsDwQa39HbfA0E6HY1mSsWdh/+z3oV8= ARC-Message-Signature: i=1; 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Tue, 8 Oct 2019 14:26:40 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Eduardo Habkost , qemu-devel@nongnu.org Subject: [PATCH v2 4/8] hw/ide/sii3112: Convert reset handler to DeviceReset Date: Tue, 8 Oct 2019 16:25:35 +0200 Message-Id: <20191008142539.7793-5-philmd@redhat.com> In-Reply-To: <20191008142539.7793-1-philmd@redhat.com> References: <20191008142539.7793-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.6.2 (mx1.redhat.com [10.5.110.65]); Tue, 08 Oct 2019 14:26:49 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-block@nongnu.org, "Michael S. Tsirkin" , Aleksandar Rikalo , John Snow , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, qemu-ppc@nongnu.org, Aleksandar Markovic , Igor Mammedov , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The SiI3112A SATA controller is a PCI device, it will be reset when the PCI bus it stands on is reset. Convert its reset handler into a proper Device reset method. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Li Qiang --- hw/ide/sii3112.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/hw/ide/sii3112.c b/hw/ide/sii3112.c index 2181260531..06605d7af2 100644 --- a/hw/ide/sii3112.c +++ b/hw/ide/sii3112.c @@ -15,7 +15,6 @@ #include "qemu/osdep.h" #include "hw/ide/pci.h" #include "qemu/module.h" -#include "sysemu/reset.h" #include "trace.h" =20 #define TYPE_SII3112_PCI "sii3112" @@ -237,9 +236,9 @@ static void sii3112_set_irq(void *opaque, int channel, = int level) sii3112_update_irq(s); } =20 -static void sii3112_reset(void *opaque) +static void sii3112_reset(DeviceState *dev) { - SiI3112PCIState *s =3D opaque; + SiI3112PCIState *s =3D SII3112_PCI(dev); int i; =20 for (i =3D 0; i < 2; i++) { @@ -290,7 +289,6 @@ static void sii3112_pci_realize(PCIDevice *dev, Error *= *errp) s->bmdma[i].bus =3D &s->bus[i]; ide_register_restart_cb(&s->bus[i]); } - qemu_register_reset(sii3112_reset, s); } =20 static void sii3112_pci_class_init(ObjectClass *klass, void *data) @@ -303,6 +301,7 @@ static void sii3112_pci_class_init(ObjectClass *klass, = void *data) pd->class_id =3D PCI_CLASS_STORAGE_RAID; pd->revision =3D 1; pd->realize =3D sii3112_pci_realize; + dc->reset =3D sii3112_reset; dc->desc =3D "SiI3112A SATA controller"; set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); } --=20 2.21.0 From nobody Thu Apr 25 09:05:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1570545394; cv=none; d=zoho.com; s=zohoarc; b=JviAMil87qitCFsdKqCSml/mb0pP6/YNCmpX51sBPPjLd0TtimlRF+uKwEdtyWvpdjhhEU+e0tT21jqmrDuTaC/KWpkb/k3YfwXrgrQyJAiOGo9Ivx+i1HHW+DmDMmGu7eWSBuRQQnAQTtjVpwBwWO4s0DB80vdZb4f9Qxyqvj4= ARC-Message-Signature: i=1; a=rsa-sha256; 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Tue, 8 Oct 2019 14:26:49 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Eduardo Habkost , qemu-devel@nongnu.org Subject: [PATCH v2 5/8] hw/ide/via82c: Convert reset handler to DeviceReset Date: Tue, 8 Oct 2019 16:25:36 +0200 Message-Id: <20191008142539.7793-6-philmd@redhat.com> In-Reply-To: <20191008142539.7793-1-philmd@redhat.com> References: <20191008142539.7793-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.6.2 (mx1.redhat.com [10.5.110.70]); Tue, 08 Oct 2019 14:27:05 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-block@nongnu.org, "Michael S. Tsirkin" , Aleksandar Rikalo , John Snow , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, qemu-ppc@nongnu.org, Aleksandar Markovic , Igor Mammedov , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The VIA82C686B IDE controller is a PCI device, it will be reset when the PCI bus it stands on is reset. Convert its reset handler into a proper Device reset method. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Li Qiang --- hw/ide/via.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/hw/ide/via.c b/hw/ide/via.c index 7087dc676e..053622bd82 100644 --- a/hw/ide/via.c +++ b/hw/ide/via.c @@ -29,7 +29,6 @@ #include "migration/vmstate.h" #include "qemu/module.h" #include "sysemu/dma.h" -#include "sysemu/reset.h" =20 #include "hw/ide/pci.h" #include "trace.h" @@ -120,10 +119,10 @@ static void via_ide_set_irq(void *opaque, int n, int = level) } } =20 -static void via_ide_reset(void *opaque) +static void via_ide_reset(DeviceState *dev) { - PCIIDEState *d =3D opaque; - PCIDevice *pd =3D PCI_DEVICE(d); + PCIIDEState *d =3D PCI_IDE(dev); + PCIDevice *pd =3D PCI_DEVICE(dev); uint8_t *pci_conf =3D pd->config; int i; =20 @@ -172,8 +171,6 @@ static void via_ide_realize(PCIDevice *dev, Error **err= p) pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0); dev->wmask[PCI_INTERRUPT_LINE] =3D 0xf; =20 - qemu_register_reset(via_ide_reset, d); - memory_region_init_io(&d->data_bar[0], OBJECT(d), &pci_ide_data_le_ops, &d->bus[0], "via-ide0-data", 8); pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->data_bar[0]); @@ -229,6 +226,7 @@ static void via_ide_class_init(ObjectClass *klass, void= *data) DeviceClass *dc =3D DEVICE_CLASS(klass); PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); =20 + dc->reset =3D via_ide_reset; k->realize =3D via_ide_realize; k->exit =3D via_ide_exitfn; k->vendor_id =3D PCI_VENDOR_ID_VIA; --=20 2.21.0 From nobody Thu Apr 25 09:05:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; 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Tue, 8 Oct 2019 14:27:23 +0000 (UTC) Received: from x1w.redhat.com (ovpn-204-43.brq.redhat.com [10.40.204.43]) by smtp.corp.redhat.com (Postfix) with ESMTPS id C54DF19C69; Tue, 8 Oct 2019 14:27:05 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Eduardo Habkost , qemu-devel@nongnu.org Subject: [PATCH v2 6/8] hw/isa/vt82c686: Convert reset handler to DeviceReset Date: Tue, 8 Oct 2019 16:25:37 +0200 Message-Id: <20191008142539.7793-7-philmd@redhat.com> In-Reply-To: <20191008142539.7793-1-philmd@redhat.com> References: <20191008142539.7793-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.48]); Tue, 08 Oct 2019 14:27:23 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-block@nongnu.org, "Michael S. Tsirkin" , Aleksandar Rikalo , John Snow , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, qemu-ppc@nongnu.org, Aleksandar Markovic , Igor Mammedov , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The VIA VT82C686 Southbridge is a PCI device, it will be reset when the PCI bus it stands on is reset. Convert its reset handler into a proper Device reset method. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Li Qiang --- hw/isa/vt82c686.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c index 50bd28fa82..616f67f347 100644 --- a/hw/isa/vt82c686.c +++ b/hw/isa/vt82c686.c @@ -23,7 +23,6 @@ #include "hw/isa/apm.h" #include "hw/acpi/acpi.h" #include "hw/i2c/pm_smbus.h" -#include "sysemu/reset.h" #include "qemu/module.h" #include "qemu/timer.h" #include "exec/address-spaces.h" @@ -116,11 +115,10 @@ static const MemoryRegionOps superio_ops =3D { }, }; =20 -static void vt82c686b_reset(void * opaque) +static void vt82c686b_isa_reset(DeviceState *dev) { - PCIDevice *d =3D opaque; - uint8_t *pci_conf =3D d->config; - VT82C686BState *vt82c =3D VT82C686B_DEVICE(d); + VT82C686BState *vt82c =3D VT82C686B_DEVICE(dev); + uint8_t *pci_conf =3D vt82c->dev.config; =20 pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0); pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMO= RY | @@ -476,8 +474,6 @@ static void vt82c686b_realize(PCIDevice *d, Error **err= p) * But we do not emulate a floppy, so just set it here. */ memory_region_add_subregion(isa_bus->address_space_io, 0x3f0, &vt82c->superio); - - qemu_register_reset(vt82c686b_reset, d); } =20 ISABus *vt82c686b_isa_init(PCIBus *bus, int devfn) @@ -501,6 +497,7 @@ static void via_class_init(ObjectClass *klass, void *da= ta) k->device_id =3D PCI_DEVICE_ID_VIA_ISA_BRIDGE; k->class_id =3D PCI_CLASS_BRIDGE_ISA; k->revision =3D 0x40; + dc->reset =3D vt82c686b_isa_reset; dc->desc =3D "ISA bridge"; dc->vmsd =3D &vmstate_via; /* --=20 2.21.0 From nobody Thu Apr 25 09:05:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1570545530; cv=none; d=zoho.com; s=zohoarc; b=MAkSzrZ9ACoh/Tjs8zrfJxW9/Br38Oi4+vlz4frNCZI2k0/V3zKPjTaEcah97hWU7rmxl0XwWNifYdamyMJn93g3naVCATxlYANXSEsEohrmhNKxT11AIWZb6Q7YEW9NrGTXsSlfm0GBLJ9zItnGlYLBuwbO+frQVSgPfAmeKX8= ARC-Message-Signature: i=1; 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Tue, 8 Oct 2019 14:27:23 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Eduardo Habkost , qemu-devel@nongnu.org Subject: [PATCH v2 7/8] hw/input/lm832x: Convert reset handler to DeviceReset Date: Tue, 8 Oct 2019 16:25:38 +0200 Message-Id: <20191008142539.7793-8-philmd@redhat.com> In-Reply-To: <20191008142539.7793-1-philmd@redhat.com> References: <20191008142539.7793-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.6.2 (mx1.redhat.com [10.5.110.71]); Tue, 08 Oct 2019 14:27:29 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-block@nongnu.org, "Michael S. Tsirkin" , Aleksandar Rikalo , John Snow , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, qemu-ppc@nongnu.org, Aleksandar Markovic , Igor Mammedov , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The LM8323 key-scan controller is a I2C device, it will be reset when the I2C bus it stands on is reset. Convert its reset handler into a proper Device reset method. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Li Qiang --- hw/input/lm832x.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/hw/input/lm832x.c b/hw/input/lm832x.c index a37eb854b9..aa629ddbf1 100644 --- a/hw/input/lm832x.c +++ b/hw/input/lm832x.c @@ -24,7 +24,6 @@ #include "migration/vmstate.h" #include "qemu/module.h" #include "qemu/timer.h" -#include "sysemu/reset.h" #include "ui/console.h" =20 #define TYPE_LM8323 "lm8323" @@ -94,8 +93,10 @@ static void lm_kbd_gpio_update(LM823KbdState *s) { } =20 -static void lm_kbd_reset(LM823KbdState *s) +static void lm_kbd_reset(DeviceState *dev) { + LM823KbdState *s =3D LM8323(dev); + s->config =3D 0x80; s->status =3D INT_NOINIT; s->acttime =3D 125; @@ -273,7 +274,7 @@ static void lm_kbd_write(LM823KbdState *s, int reg, int= byte, uint8_t value) =20 case LM832x_CMD_RESET: if (value =3D=3D 0xaa) - lm_kbd_reset(s); + lm_kbd_reset(DEVICE(s)); else lm_kbd_error(s, ERR_BADPAR); s->reg =3D LM832x_GENERAL_ERROR; @@ -476,10 +477,6 @@ static void lm8323_realize(DeviceState *dev, Error **e= rrp) s->pwm.tm[1] =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, lm_kbd_pwm1_tick, s); s->pwm.tm[2] =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, lm_kbd_pwm2_tick, s); qdev_init_gpio_out(dev, &s->nirq, 1); - - lm_kbd_reset(s); - - qemu_register_reset((void *) lm_kbd_reset, s); } =20 void lm832x_key_event(DeviceState *dev, int key, int state) @@ -507,6 +504,7 @@ static void lm8323_class_init(ObjectClass *klass, void = *data) DeviceClass *dc =3D DEVICE_CLASS(klass); I2CSlaveClass *k =3D I2C_SLAVE_CLASS(klass); =20 + dc->reset =3D lm_kbd_reset; dc->realize =3D lm8323_realize; k->event =3D lm_i2c_event; k->recv =3D lm_i2c_rx; --=20 2.21.0 From nobody Thu Apr 25 09:05:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; 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spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1570545727018295.11856042206284; Tue, 8 Oct 2019 07:42:07 -0700 (PDT) Received: from localhost ([::1]:56812 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iHqgX-0005q4-Gg for importer@patchew.org; Tue, 08 Oct 2019 10:41:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51144) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iHqa8-0006gB-TO for qemu-devel@nongnu.org; Tue, 08 Oct 2019 10:35:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iHqa7-0004eC-Nj for qemu-devel@nongnu.org; Tue, 08 Oct 2019 10:35:20 -0400 Received: from mx1.redhat.com ([209.132.183.28]:39716) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iHqa7-0004dZ-HW for qemu-devel@nongnu.org; Tue, 08 Oct 2019 10:35:19 -0400 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id C3A7580F6D for ; Tue, 8 Oct 2019 14:35:18 +0000 (UTC) Received: from x1w.redhat.com (ovpn-204-43.brq.redhat.com [10.40.204.43]) by smtp.corp.redhat.com (Postfix) with ESMTPS id C337710013A1; Tue, 8 Oct 2019 14:35:11 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Eduardo Habkost , qemu-devel@nongnu.org Subject: [PATCH v2 8/8] hw/misc/vmcoreinfo: Add comment about reset handler Date: Tue, 8 Oct 2019 16:34:55 +0200 Message-Id: <20191008143455.8524-1-philmd@redhat.com> In-Reply-To: <20191008142539.7793-1-philmd@redhat.com> References: <20191008142539.7793-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.27]); Tue, 08 Oct 2019 14:35:18 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The VM coreinfo device does not sit on a bus, so it won't be reset automatically. This is why it calls qemu_register_reset(). Add a comment about it, so we don't convert its reset handler to a DeviceReset method. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Li Qiang Reviewed-by: Marc-Andr=C3=A9 Lureau --- hw/misc/vmcoreinfo.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/misc/vmcoreinfo.c b/hw/misc/vmcoreinfo.c index 326a3ce8f4..a9d718fc23 100644 --- a/hw/misc/vmcoreinfo.c +++ b/hw/misc/vmcoreinfo.c @@ -61,6 +61,10 @@ static void vmcoreinfo_realize(DeviceState *dev, Error *= *errp) NULL, fw_cfg_vmci_write, s, &s->vmcoreinfo, sizeof(s->vmcoreinfo), false); =20 + /* + * This device requires to register a global reset because it is + * not plugged to a bus (which, as its QOM parent, would reset it). + */ qemu_register_reset(vmcoreinfo_reset, dev); vmcoreinfo_state =3D s; } --=20 2.21.0