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[83.42.66.46]) by smtp.gmail.com with ESMTPSA id o22sm24542294wra.96.2019.10.05.08.47.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 05 Oct 2019 08:47:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cNN3zQlFhxT6iWGCrzkAdnUP+7NnUIzpyS9EQoIRQR4=; b=JqbRLn/SSsx3jDPMksphf3Pr+g5XNUQeJ1HfM1cAu4jOb5wg3788xC6s7NUuNTg7Hm DYhCjvtvVKBPAo78V5UkM/x3bi1V8IspkdkNV7bp2XXFJiv4yiaB0JaqYN535CELxpHZ CnR/ifhhEBQZj8um1FC58jE2M+JCnM67HMKizsc7CXt7xBylcpARsDEW6Cnwrd95NXoA 0m0hlB/tZjwDPNVsWJaPf1esu9yJfIwCD8D20l3LRLRm6/uOw9fEm3KcbSibVyJIQQsB B4UwXrowNli4IVbMJlhJ9OnrLqAHjaMTDpAd/Hs8q+98yPfDwnvQjvfCcLOBYrY7TvYi JqgQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=cNN3zQlFhxT6iWGCrzkAdnUP+7NnUIzpyS9EQoIRQR4=; b=tvQnoD/rSZCw7I5O6AIOCO6F5d5e4az1qhQsU9VLtsfgA2q83zHcNniGLU86DGIbHK QpGRdDqu723Z20gbTirE0oKmNn14jWpnnIGHm4950sOc+4myLSQ3/V4d4lYRrIltjgvl W207NRBvw5/uJUvQBiOwcLx73HIJ10eyzhJXUYpg1NkPVc5fcVDD+RutDJ/YEy+QKYS+ 5NgPd8Ten+YDBV8IX6/4E5usDPe/p0dSc2XYY0kufPWUeM6nxdvQ0ub6fuQrZsU5c1ZX z6hKFk2sxbvUvmu8iMqsVfmiQbUFmbfie3CfHoa1alq8afA4XQMJTjHeQC35wRuC+jKy Q00A== X-Gm-Message-State: APjAAAU63EdQlzfAWPqpxyOuhHBK5QGn+5tXdsFf9pmSuFw+rwFcxPlS K/bQ2EjF1FfCfcgt0m3eqot44Xwum3s= X-Google-Smtp-Source: APXvYqzSG5PGCSenCjwNYiwzqbh2B1823YqpSd3zAXjT6SFJYjqgT2t+TuVG2lPsayAoiv9IrziCWA== X-Received: by 2002:adf:afed:: with SMTP id y45mr15778527wrd.347.1570290475969; Sat, 05 Oct 2019 08:47:55 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH 3/5] hw/sd/sdhci: Add dummy Samsung SDHCI controller Date: Sat, 5 Oct 2019 17:47:46 +0200 Message-Id: <20191005154748.21718-4-f4bug@amsat.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191005154748.21718-1-f4bug@amsat.org> References: <20191005154748.21718-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Basse?= , Peter Maydell , Eduardo Habkost , Evgeny Voevodin , Bartlomiej Zolnierkiewicz , Igor Mitsyanko , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Krzysztof Kozlowski , Jean-Christophe Dubois , qemu-arm@nongnu.org, Dmitry Solodkiy , Cleber Rosa , Maksim Kozlov , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Guenter Roeck Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) The Linux kernel access few S3C-specific registers [1] to set some clock. We don't care about this part for device emulation [2]. Add a dummy device to properly ignore these accesses, so we can focus on the important registers missing. [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree= /drivers/mmc/host/sdhci-s3c-regs.h?h=3Dcc014f3 [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree= /drivers/mmc/host/sdhci-s3c.c?h=3Dv5.3#n263 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Krzysztof Kozlowski --- Eventually we should add the ADMA changes Igor sent in this patch: https://patchwork.ozlabs.org/patch/181854/ They might solve the boot timing issues when using SD cards. --- hw/sd/sdhci.c | 65 +++++++++++++++++++++++++++++++++++++++++++ include/hw/sd/sdhci.h | 2 ++ 2 files changed, 67 insertions(+) diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index 82ec5c1b4a..88404d0e9d 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -1761,11 +1761,76 @@ static const TypeInfo imx_usdhc_info =3D { .instance_init =3D imx_usdhc_init, }; =20 +/* --- qdev Samsung s3c --- */ + +#define S3C_SDHCI_CONTROL2 0x80 +#define S3C_SDHCI_CONTROL3 0x84 +#define S3C_SDHCI_CONTROL4 0x8c + +static uint64_t sdhci_s3c_read(void *opaque, hwaddr offset, unsigned size) +{ + uint64_t ret; + + switch (offset) { + case S3C_SDHCI_CONTROL2: + case S3C_SDHCI_CONTROL3: + case S3C_SDHCI_CONTROL4: + /* ignore */ + ret =3D 0; + break; + default: + ret =3D sdhci_read(opaque, offset, size); + break; + } + + return ret; +} + +static void sdhci_s3c_write(void *opaque, hwaddr offset, uint64_t val, + unsigned size) +{ + switch (offset) { + case S3C_SDHCI_CONTROL2: + case S3C_SDHCI_CONTROL3: + case S3C_SDHCI_CONTROL4: + /* ignore */ + break; + default: + sdhci_write(opaque, offset, val, size); + break; + } +} + +static const MemoryRegionOps sdhci_s3c_mmio_ops =3D { + .read =3D sdhci_s3c_read, + .write =3D sdhci_s3c_write, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 4, + .unaligned =3D false + }, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + +static void sdhci_s3c_init(Object *obj) +{ + SDHCIState *s =3D SYSBUS_SDHCI(obj); + + s->io_ops =3D &sdhci_s3c_mmio_ops; +} + +static const TypeInfo sdhci_s3c_info =3D { + .name =3D TYPE_S3C_SDHCI , + .parent =3D TYPE_SYSBUS_SDHCI, + .instance_init =3D sdhci_s3c_init, +}; + static void sdhci_register_types(void) { type_register_static(&sdhci_sysbus_info); type_register_static(&sdhci_bus_info); type_register_static(&imx_usdhc_info); + type_register_static(&sdhci_s3c_info); } =20 type_init(sdhci_register_types) diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h index cbf415e43a..c6868c9699 100644 --- a/include/hw/sd/sdhci.h +++ b/include/hw/sd/sdhci.h @@ -116,4 +116,6 @@ typedef struct SDHCIState { =20 #define TYPE_IMX_USDHC "imx-usdhc" =20 +#define TYPE_S3C_SDHCI "s3c-sdhci" + #endif /* SDHCI_H */ --=20 2.20.1