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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id t17sm11962094wrp.72.2019.10.04.04.48.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Oct 2019 04:48:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tWO1/w2pbq76WDihTU7NTfFwpS052NS/zIcxZUmg9Z8=; b=VaahP1bJi2xcdpZhg4k/R8BFCQFmrQYArrykQIiM8pk+iSZTAzNfkqW01rTKJ/HBwD JYTCSgpQGxFSNQdKpxx/nOjFyc3hipOiPj1vJxVBvR2hiQjisBao7pHUmBVnp7iieEeU zpLc3/HTMMz+k75G98FtI2+Xnv6NnSSC8TriTnLcZh0r2fd4qZm23Se5aEmeJVpzbTa0 js5WjDUkScoDwgR9xGBNmCJjWnq2Sd19Q+vYmeFKcTCzER01OVapPnAEnAEbKRhcHwQt X5+foWggR9vpSoK+hPcWkk81cMVzaHbR+/tN9PgZVWn6nSEPOJ1OD7TH4Z4qPajsqL26 n7Ew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tWO1/w2pbq76WDihTU7NTfFwpS052NS/zIcxZUmg9Z8=; b=TzqO/gS6ryUlyjimHR9H1FKdzh5FeOqY2zob0GobxQQhg/YvEPl4uzoVUPAE1zFvLc Tp2LRRdn86lus/iEWx/MNk20kbIKgRgRO3kVntxrv2LvndcGOo6csSMQ7rkzcje6OVO9 NAab/MIMclclhJejR0yqL3rwCvmOwmqhXVdtKTdpo905iDED9uTJyGYEs2r/mbkYFcRs WYMkPfF+wlQMq/w0HJe/yJXWfbFc2FTYDGtNrVb3Me7sr5Vu3ZBXnBQqRgg7b4phUvVo fYtnAwxqbeWvgjdMlEu+KnTfqt5mdTovZvYL69FnCm3F2nAxTNfFVfnUQONB4t3fEsSl +ayQ== X-Gm-Message-State: APjAAAWcfrT0fYFTsbwjkbUtjsrGuxCyqtGIM47me1II1eg4fzzNfIxZ aiPiQo1ERs5eZ4eWUt0xQnu62A== X-Google-Smtp-Source: APXvYqwTw9AH0FDLiRvJx65Zve+aM97SE6hg4t30FuS7+ZdCT2oAREl5HvYTNtylXed3Q9uIer9rnw== X-Received: by 2002:adf:fcc7:: with SMTP id f7mr11092345wrs.319.1570189732496; Fri, 04 Oct 2019 04:48:52 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [RFC 1/4] hw/timer/arm_timer: Add trace events Date: Fri, 4 Oct 2019 12:48:45 +0100 Message-Id: <20191004114848.16831-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191004114848.16831-1-peter.maydell@linaro.org> References: <20191004114848.16831-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Paolo Bonzini Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Add some basic trace events to the arm_timer device. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/timer/arm_timer.c | 27 +++++++++++++++++++++------ hw/timer/trace-events | 7 +++++++ 2 files changed, 28 insertions(+), 6 deletions(-) diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c index c2e6211188b..283ae1e74a9 100644 --- a/hw/timer/arm_timer.c +++ b/hw/timer/arm_timer.c @@ -17,6 +17,7 @@ #include "qemu/main-loop.h" #include "qemu/module.h" #include "qemu/log.h" +#include "trace.h" =20 /* Common timer implementation. */ =20 @@ -43,7 +44,10 @@ typedef struct { static void arm_timer_update(arm_timer_state *s) { /* Update interrupts. */ - if (s->int_level && (s->control & TIMER_CTRL_IE)) { + int level =3D s->int_level && (s->control & TIMER_CTRL_IE); + + trace_sp804_arm_timer_update(level); + if (level) { qemu_irq_raise(s->irq); } else { qemu_irq_lower(s->irq); @@ -216,17 +220,21 @@ static uint64_t sp804_read(void *opaque, hwaddr offse= t, unsigned size) { SP804State *s =3D (SP804State *)opaque; + uint64_t res; =20 if (offset < 0x20) { - return arm_timer_read(s->timer[0], offset); + res =3D arm_timer_read(s->timer[0], offset); + goto out; } if (offset < 0x40) { - return arm_timer_read(s->timer[1], offset - 0x20); + res =3D arm_timer_read(s->timer[1], offset - 0x20); + goto out; } =20 /* TimerPeriphID */ if (offset >=3D 0xfe0 && offset <=3D 0xffc) { - return sp804_ids[(offset - 0xfe0) >> 2]; + res =3D sp804_ids[(offset - 0xfe0) >> 2]; + goto out; } =20 switch (offset) { @@ -236,12 +244,17 @@ static uint64_t sp804_read(void *opaque, hwaddr offse= t, qemu_log_mask(LOG_UNIMP, "%s: integration test registers unimplemented\n", __func__); - return 0; + res =3D 0; + goto out; } =20 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %x\n", __func__, (int)offset); - return 0; + res =3D 0; + +out: + trace_sp804_read(offset, res); + return res; } =20 static void sp804_write(void *opaque, hwaddr offset, @@ -249,6 +262,8 @@ static void sp804_write(void *opaque, hwaddr offset, { SP804State *s =3D (SP804State *)opaque; =20 + trace_sp804_write(offset, value); + if (offset < 0x20) { arm_timer_write(s->timer[0], offset, value); return; diff --git a/hw/timer/trace-events b/hw/timer/trace-events index db02a9142cd..600b002c7bf 100644 --- a/hw/timer/trace-events +++ b/hw/timer/trace-events @@ -87,3 +87,10 @@ pl031_read(uint32_t addr, uint32_t value) "addr 0x%08x v= alue 0x%08x" pl031_write(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x" pl031_alarm_raised(void) "alarm raised" pl031_set_alarm(uint32_t ticks) "alarm set for %u ticks" + +# arm_timer.c +sp804_read(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x" +sp804_write(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x" +# Note that this trace event can't distinguish which of the two timers +# in the sp804 is being updated +sp804_arm_timer_update(int level) "level %d" --=20 2.20.1 From nobody Sat May 18 19:12:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id t17sm11962094wrp.72.2019.10.04.04.48.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Oct 2019 04:48:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YDhUeH3cVFOIwL0G3f1j5lyNalM6S+Oh7XIJeTypydU=; b=ytr+K8e78T+0t/dLWsJRBjXWDNWI+IhN3H7V4eOEOEbHWx4GOWyAwPEHFZCBAVmy9S U1Q8KdexJfrluSRfhtvOv25I5Dw+IP6z67xJ3/ZSNahAC1NAqSR9kNE5ZP9/s2tY5526 d8lkzyaE1HniyrRuT4LnyO+WQiqc9OCjWTXPVZCxftb5X36Tz0Qt8AlmupdYuJhuILJF T70ZehsxcjxB9iK6/yMJI3ZyQH3XUYJwaaRJZMNhR+NHsPUe8hY7GZXmtcz+QShFyQ8Q 9d2Hc+YXcI4ApkxW5QjK9RWx9lSo5wm1YngX8HbJqI8BTQk9U69zbiK9MM8dK0h4yx5A 8kLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YDhUeH3cVFOIwL0G3f1j5lyNalM6S+Oh7XIJeTypydU=; b=qSHFSdAzj04M/bB0rCybO/Kv5ap/0TJPYVHIgAafhzOjGIqGPlHD9kgXFvpI39mEds OvSJom10u+EQBHVoBGPNtChsXhIwZGpOC8ddNBql0tDT5tjypa6QUF+Ii5AyTWYrC9Ew OOIkC3dGHTQ48BXNIPtwIHdCvVzJa2M7Q8TmlYdCAH1np0+sVUhz4/7IO7qOatLC+Wg4 WR6SMaaOFseBylDb7yxvcyEdhy71H0ZKcH7TAxMkL00zB/AIJbnu/ZXYNSj91Sn+BLY+ r/fT1wzEkanaAx47Vv1JglOu++9kmYEzgFrtyX2oFxHrcJ/aRYsu/0mRn609RgmE38m1 FPDg== X-Gm-Message-State: APjAAAUDTam6UdbwRMDgrhw1h/XJD3hwn5zdJ0fGzz65TAwJeuyLQO97 jInM4uNH8bc8q/OWc6BeSn84TGI5j8oFKw== X-Google-Smtp-Source: APXvYqwoUNKQITRZo+ChGxm6AZkC67zE87QomWrs9WYhqFC7wnkqi7gfbphtAfFsXSKYmkn5MKIyAw== X-Received: by 2002:adf:9788:: with SMTP id s8mr8803814wrb.123.1570189734065; Fri, 04 Oct 2019 04:48:54 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [RFC 2/4] ptimer: Rename ptimer_init() to ptimer_init_with_bh() Date: Fri, 4 Oct 2019 12:48:46 +0100 Message-Id: <20191004114848.16831-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191004114848.16831-1-peter.maydell@linaro.org> References: <20191004114848.16831-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::430 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Paolo Bonzini Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Currently the ptimer design uses a QEMU bottom-half as its mechanism for calling back into the device model using the ptimer when the timer has expired. Unfortunately this design is fatally flawed, because it means that there is a lag between the ptimer updating its own state and the device callback function updating device state, and guest accesses to device registers between the two can return inconsistent device state. We want to replace the bottom-half design with one where the guest device's callback is called either immediately (when the ptimer triggers by timeout) or when the device model code closes a transaction-begin/end section (when the ptimer triggers because the device model changed the ptimer's count value or other state). As the first step, rename ptimer_init() to ptimer_init_with_bh(), to free up the ptimer_init() name for the new API. We can then convert all the ptimer users away from ptimer_init_with_bh() before removing it entirely. (Commit created with git grep -l ptimer_init | xargs sed -i -e 's/ptimer_init/ptimer_init_with_= bh/' and three overlong lines folded by hand.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/hw/ptimer.h | 11 ++++++----- hw/arm/musicpal.c | 2 +- hw/core/ptimer.c | 2 +- hw/dma/xilinx_axidma.c | 2 +- hw/m68k/mcf5206.c | 2 +- hw/m68k/mcf5208.c | 2 +- hw/net/fsl_etsec/etsec.c | 2 +- hw/net/lan9118.c | 2 +- hw/timer/allwinner-a10-pit.c | 2 +- hw/timer/altera_timer.c | 2 +- hw/timer/arm_mptimer.c | 6 +++--- hw/timer/arm_timer.c | 2 +- hw/timer/cmsdk-apb-dualtimer.c | 2 +- hw/timer/cmsdk-apb-timer.c | 2 +- hw/timer/digic-timer.c | 2 +- hw/timer/etraxfs_timer.c | 6 +++--- hw/timer/exynos4210_mct.c | 7 ++++--- hw/timer/exynos4210_pwm.c | 2 +- hw/timer/exynos4210_rtc.c | 4 ++-- hw/timer/grlib_gptimer.c | 2 +- hw/timer/imx_epit.c | 4 ++-- hw/timer/imx_gpt.c | 2 +- hw/timer/lm32_timer.c | 2 +- hw/timer/milkymist-sysctl.c | 4 ++-- hw/timer/mss-timer.c | 2 +- hw/timer/puv3_ost.c | 2 +- hw/timer/sh_timer.c | 2 +- hw/timer/slavio_timer.c | 2 +- hw/timer/xilinx_timer.c | 2 +- hw/watchdog/cmsdk-apb-watchdog.c | 2 +- tests/ptimer-test.c | 22 +++++++++++----------- 31 files changed, 56 insertions(+), 54 deletions(-) diff --git a/include/hw/ptimer.h b/include/hw/ptimer.h index 9c770552290..2fb9ba1915e 100644 --- a/include/hw/ptimer.h +++ b/include/hw/ptimer.h @@ -72,7 +72,7 @@ * ptimer_set_count() or ptimer_set_limit() will not trigger the timer * (though it will cause a reload). Only a counter decrement to "0" * will cause a trigger. Not compatible with NO_IMMEDIATE_TRIGGER; - * ptimer_init() will assert() that you don't set both. + * ptimer_init_with_bh() will assert() that you don't set both. */ #define PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT (1 << 5) =20 @@ -81,7 +81,7 @@ typedef struct ptimer_state ptimer_state; typedef void (*ptimer_cb)(void *opaque); =20 /** - * ptimer_init - Allocate and return a new ptimer + * ptimer_init_with_bh - Allocate and return a new ptimer * @bh: QEMU bottom half which is run on timer expiry * @policy: PTIMER_POLICY_* bits specifying behaviour * @@ -89,13 +89,13 @@ typedef void (*ptimer_cb)(void *opaque); * The ptimer takes ownership of @bh and will delete it * when the ptimer is eventually freed. */ -ptimer_state *ptimer_init(QEMUBH *bh, uint8_t policy_mask); +ptimer_state *ptimer_init_with_bh(QEMUBH *bh, uint8_t policy_mask); =20 /** * ptimer_free - Free a ptimer * @s: timer to free * - * Free a ptimer created using ptimer_init() (including + * Free a ptimer created using ptimer_init_with_bh() (including * deleting the bottom half which it is using). */ void ptimer_free(ptimer_state *s); @@ -178,7 +178,8 @@ void ptimer_set_count(ptimer_state *s, uint64_t count); * @oneshot: non-zero if this timer should only count down once * * Start a ptimer counting down; when it reaches zero the bottom half - * passed to ptimer_init() will be invoked. If the @oneshot argument is ze= ro, + * passed to ptimer_init_with_bh() will be invoked. + * If the @oneshot argument is zero, * the counter value will then be reloaded from the limit and it will * start counting down again. If @oneshot is non-zero, then the counter * will disable itself when it reaches zero. diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c index 246cbb13363..b3624d5e280 100644 --- a/hw/arm/musicpal.c +++ b/hw/arm/musicpal.c @@ -849,7 +849,7 @@ static void mv88w8618_timer_init(SysBusDevice *dev, mv8= 8w8618_timer_state *s, s->freq =3D freq; =20 bh =3D qemu_bh_new(mv88w8618_timer_tick, s); - s->ptimer =3D ptimer_init(bh, PTIMER_POLICY_DEFAULT); + s->ptimer =3D ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); } =20 static uint64_t mv88w8618_pit_read(void *opaque, hwaddr offset, diff --git a/hw/core/ptimer.c b/hw/core/ptimer.c index d58e2dfdb08..f0d3ce11398 100644 --- a/hw/core/ptimer.c +++ b/hw/core/ptimer.c @@ -358,7 +358,7 @@ const VMStateDescription vmstate_ptimer =3D { } }; =20 -ptimer_state *ptimer_init(QEMUBH *bh, uint8_t policy_mask) +ptimer_state *ptimer_init_with_bh(QEMUBH *bh, uint8_t policy_mask) { ptimer_state *s; =20 diff --git a/hw/dma/xilinx_axidma.c b/hw/dma/xilinx_axidma.c index a254275b64e..e035d1f7504 100644 --- a/hw/dma/xilinx_axidma.c +++ b/hw/dma/xilinx_axidma.c @@ -552,7 +552,7 @@ static void xilinx_axidma_realize(DeviceState *dev, Err= or **errp) =20 st->nr =3D i; st->bh =3D qemu_bh_new(timer_hit, st); - st->ptimer =3D ptimer_init(st->bh, PTIMER_POLICY_DEFAULT); + st->ptimer =3D ptimer_init_with_bh(st->bh, PTIMER_POLICY_DEFAULT); ptimer_set_freq(st->ptimer, s->freqhz); } return; diff --git a/hw/m68k/mcf5206.c b/hw/m68k/mcf5206.c index a9c2c95b0d1..a49096367cb 100644 --- a/hw/m68k/mcf5206.c +++ b/hw/m68k/mcf5206.c @@ -141,7 +141,7 @@ static m5206_timer_state *m5206_timer_init(qemu_irq irq) =20 s =3D g_new0(m5206_timer_state, 1); bh =3D qemu_bh_new(m5206_timer_trigger, s); - s->timer =3D ptimer_init(bh, PTIMER_POLICY_DEFAULT); + s->timer =3D ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); s->irq =3D irq; m5206_timer_reset(s); return s; diff --git a/hw/m68k/mcf5208.c b/hw/m68k/mcf5208.c index 012710d057d..45c28b75a17 100644 --- a/hw/m68k/mcf5208.c +++ b/hw/m68k/mcf5208.c @@ -192,7 +192,7 @@ static void mcf5208_sys_init(MemoryRegion *address_spac= e, qemu_irq *pic) for (i =3D 0; i < 2; i++) { s =3D g_new0(m5208_timer_state, 1); bh =3D qemu_bh_new(m5208_timer_trigger, s); - s->timer =3D ptimer_init(bh, PTIMER_POLICY_DEFAULT); + s->timer =3D ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); memory_region_init_io(&s->iomem, NULL, &m5208_timer_ops, s, "m5208-timer", 0x00004000); memory_region_add_subregion(address_space, 0xfc080000 + 0x4000 * i, diff --git a/hw/net/fsl_etsec/etsec.c b/hw/net/fsl_etsec/etsec.c index 8451c17fb8f..d9b3e8c691e 100644 --- a/hw/net/fsl_etsec/etsec.c +++ b/hw/net/fsl_etsec/etsec.c @@ -393,7 +393,7 @@ static void etsec_realize(DeviceState *dev, Error **err= p) =20 =20 etsec->bh =3D qemu_bh_new(etsec_timer_hit, etsec); - etsec->ptimer =3D ptimer_init(etsec->bh, PTIMER_POLICY_DEFAULT); + etsec->ptimer =3D ptimer_init_with_bh(etsec->bh, PTIMER_POLICY_DEFAULT= ); ptimer_set_freq(etsec->ptimer, 100); } =20 diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c index 8bba2a80568..0ea51433dca 100644 --- a/hw/net/lan9118.c +++ b/hw/net/lan9118.c @@ -1350,7 +1350,7 @@ static void lan9118_realize(DeviceState *dev, Error *= *errp) s->txp =3D &s->tx_packet; =20 bh =3D qemu_bh_new(lan9118_tick, s); - s->timer =3D ptimer_init(bh, PTIMER_POLICY_DEFAULT); + s->timer =3D ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); ptimer_set_freq(s->timer, 10000); ptimer_set_limit(s->timer, 0xffff, 1); } diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index ca5a9050591..28d055e42f3 100644 --- a/hw/timer/allwinner-a10-pit.c +++ b/hw/timer/allwinner-a10-pit.c @@ -271,7 +271,7 @@ static void a10_pit_init(Object *obj) tc->container =3D s; tc->index =3D i; bh[i] =3D qemu_bh_new(a10_pit_timer_cb, tc); - s->timer[i] =3D ptimer_init(bh[i], PTIMER_POLICY_DEFAULT); + s->timer[i] =3D ptimer_init_with_bh(bh[i], PTIMER_POLICY_DEFAULT); } } =20 diff --git a/hw/timer/altera_timer.c b/hw/timer/altera_timer.c index 936b31311d2..ee32e0ec1ff 100644 --- a/hw/timer/altera_timer.c +++ b/hw/timer/altera_timer.c @@ -184,7 +184,7 @@ static void altera_timer_realize(DeviceState *dev, Erro= r **errp) } =20 t->bh =3D qemu_bh_new(timer_hit, t); - t->ptimer =3D ptimer_init(t->bh, PTIMER_POLICY_DEFAULT); + t->ptimer =3D ptimer_init_with_bh(t->bh, PTIMER_POLICY_DEFAULT); ptimer_set_freq(t->ptimer, t->freq_hz); =20 memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t, diff --git a/hw/timer/arm_mptimer.c b/hw/timer/arm_mptimer.c index 9f63abef10e..2a54a011431 100644 --- a/hw/timer/arm_mptimer.c +++ b/hw/timer/arm_mptimer.c @@ -228,7 +228,7 @@ static void arm_mptimer_reset(DeviceState *dev) } } =20 -static void arm_mptimer_init(Object *obj) +static void arm_mptimer_init_with_bh(Object *obj) { ARMMPTimerState *s =3D ARM_MPTIMER(obj); =20 @@ -261,7 +261,7 @@ static void arm_mptimer_realize(DeviceState *dev, Error= **errp) for (i =3D 0; i < s->num_cpu; i++) { TimerBlock *tb =3D &s->timerblock[i]; QEMUBH *bh =3D qemu_bh_new(timerblock_tick, tb); - tb->timer =3D ptimer_init(bh, PTIMER_POLICY); + tb->timer =3D ptimer_init_with_bh(bh, PTIMER_POLICY); sysbus_init_irq(sbd, &tb->irq); memory_region_init_io(&tb->iomem, OBJECT(s), &timerblock_ops, tb, "arm_mptimer_timerblock", 0x20); @@ -311,7 +311,7 @@ static const TypeInfo arm_mptimer_info =3D { .name =3D TYPE_ARM_MPTIMER, .parent =3D TYPE_SYS_BUS_DEVICE, .instance_size =3D sizeof(ARMMPTimerState), - .instance_init =3D arm_mptimer_init, + .instance_init =3D arm_mptimer_init_with_bh, .class_init =3D arm_mptimer_class_init, }; =20 diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c index 283ae1e74a9..848fbcb0e25 100644 --- a/hw/timer/arm_timer.c +++ b/hw/timer/arm_timer.c @@ -177,7 +177,7 @@ static arm_timer_state *arm_timer_init(uint32_t freq) s->control =3D TIMER_CTRL_IE; =20 bh =3D qemu_bh_new(arm_timer_tick, s); - s->timer =3D ptimer_init(bh, PTIMER_POLICY_DEFAULT); + s->timer =3D ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); vmstate_register(NULL, -1, &vmstate_arm_timer, s); return s; } diff --git a/hw/timer/cmsdk-apb-dualtimer.c b/hw/timer/cmsdk-apb-dualtimer.c index 5e2352dd326..44d23c80364 100644 --- a/hw/timer/cmsdk-apb-dualtimer.c +++ b/hw/timer/cmsdk-apb-dualtimer.c @@ -453,7 +453,7 @@ static void cmsdk_apb_dualtimer_realize(DeviceState *de= v, Error **errp) QEMUBH *bh =3D qemu_bh_new(cmsdk_dualtimermod_tick, m); =20 m->parent =3D s; - m->timer =3D ptimer_init(bh, + m->timer =3D ptimer_init_with_bh(bh, PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD | PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT | PTIMER_POLICY_NO_IMMEDIATE_RELOAD | diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c index c83e26566a9..c9ce9770cef 100644 --- a/hw/timer/cmsdk-apb-timer.c +++ b/hw/timer/cmsdk-apb-timer.c @@ -218,7 +218,7 @@ static void cmsdk_apb_timer_realize(DeviceState *dev, E= rror **errp) } =20 bh =3D qemu_bh_new(cmsdk_apb_timer_tick, s); - s->timer =3D ptimer_init(bh, + s->timer =3D ptimer_init_with_bh(bh, PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD | PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT | PTIMER_POLICY_NO_IMMEDIATE_RELOAD | diff --git a/hw/timer/digic-timer.c b/hw/timer/digic-timer.c index 021c4ef714f..b111e1fe643 100644 --- a/hw/timer/digic-timer.c +++ b/hw/timer/digic-timer.c @@ -129,7 +129,7 @@ static void digic_timer_init(Object *obj) { DigicTimerState *s =3D DIGIC_TIMER(obj); =20 - s->ptimer =3D ptimer_init(NULL, PTIMER_POLICY_DEFAULT); + s->ptimer =3D ptimer_init_with_bh(NULL, PTIMER_POLICY_DEFAULT); =20 /* * FIXME: there is no documentation on Digic timer diff --git a/hw/timer/etraxfs_timer.c b/hw/timer/etraxfs_timer.c index d62025b8797..ab27fe1895b 100644 --- a/hw/timer/etraxfs_timer.c +++ b/hw/timer/etraxfs_timer.c @@ -328,9 +328,9 @@ static void etraxfs_timer_realize(DeviceState *dev, Err= or **errp) t->bh_t0 =3D qemu_bh_new(timer0_hit, t); t->bh_t1 =3D qemu_bh_new(timer1_hit, t); t->bh_wd =3D qemu_bh_new(watchdog_hit, t); - t->ptimer_t0 =3D ptimer_init(t->bh_t0, PTIMER_POLICY_DEFAULT); - t->ptimer_t1 =3D ptimer_init(t->bh_t1, PTIMER_POLICY_DEFAULT); - t->ptimer_wd =3D ptimer_init(t->bh_wd, PTIMER_POLICY_DEFAULT); + t->ptimer_t0 =3D ptimer_init_with_bh(t->bh_t0, PTIMER_POLICY_DEFAULT); + t->ptimer_t1 =3D ptimer_init_with_bh(t->bh_t1, PTIMER_POLICY_DEFAULT); + t->ptimer_wd =3D ptimer_init_with_bh(t->bh_wd, PTIMER_POLICY_DEFAULT); =20 sysbus_init_irq(sbd, &t->irq); sysbus_init_irq(sbd, &t->nmi); diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c index 77b9af05f41..9f2e8dd0a42 100644 --- a/hw/timer/exynos4210_mct.c +++ b/hw/timer/exynos4210_mct.c @@ -1429,7 +1429,7 @@ static void exynos4210_mct_init(Object *obj) =20 /* Global timer */ bh[0] =3D qemu_bh_new(exynos4210_gfrc_event, s); - s->g_timer.ptimer_frc =3D ptimer_init(bh[0], PTIMER_POLICY_DEFAULT); + s->g_timer.ptimer_frc =3D ptimer_init_with_bh(bh[0], PTIMER_POLICY_DEF= AULT); memset(&s->g_timer.reg, 0, sizeof(struct gregs)); =20 /* Local timers */ @@ -1437,8 +1437,9 @@ static void exynos4210_mct_init(Object *obj) bh[0] =3D qemu_bh_new(exynos4210_ltick_event, &s->l_timer[i]); bh[1] =3D qemu_bh_new(exynos4210_lfrc_event, &s->l_timer[i]); s->l_timer[i].tick_timer.ptimer_tick =3D - ptimer_init(bh[0], PTIMER_POLICY_DEFAUL= T); - s->l_timer[i].ptimer_frc =3D ptimer_init(bh[1], PTIMER_POLICY_DEFA= ULT); + ptimer_init_with_bh(bh[0], PTIMER_POLICY_DEFAULT); + s->l_timer[i].ptimer_frc =3D + ptimer_init_with_bh(bh[1], PTIMER_POLICY_DEFAULT); s->l_timer[i].id =3D i; } =20 diff --git a/hw/timer/exynos4210_pwm.c b/hw/timer/exynos4210_pwm.c index b7fad2ad449..aa5dca68ef7 100644 --- a/hw/timer/exynos4210_pwm.c +++ b/hw/timer/exynos4210_pwm.c @@ -393,7 +393,7 @@ static void exynos4210_pwm_init(Object *obj) for (i =3D 0; i < EXYNOS4210_PWM_TIMERS_NUM; i++) { bh =3D qemu_bh_new(exynos4210_pwm_tick, &s->timer[i]); sysbus_init_irq(dev, &s->timer[i].irq); - s->timer[i].ptimer =3D ptimer_init(bh, PTIMER_POLICY_DEFAULT); + s->timer[i].ptimer =3D ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAU= LT); s->timer[i].id =3D i; s->timer[i].parent =3D s; } diff --git a/hw/timer/exynos4210_rtc.c b/hw/timer/exynos4210_rtc.c index ea689042297..d5d7c91fb15 100644 --- a/hw/timer/exynos4210_rtc.c +++ b/hw/timer/exynos4210_rtc.c @@ -558,12 +558,12 @@ static void exynos4210_rtc_init(Object *obj) QEMUBH *bh; =20 bh =3D qemu_bh_new(exynos4210_rtc_tick, s); - s->ptimer =3D ptimer_init(bh, PTIMER_POLICY_DEFAULT); + s->ptimer =3D ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); ptimer_set_freq(s->ptimer, RTC_BASE_FREQ); exynos4210_rtc_update_freq(s, 0); =20 bh =3D qemu_bh_new(exynos4210_rtc_1Hz_tick, s); - s->ptimer_1Hz =3D ptimer_init(bh, PTIMER_POLICY_DEFAULT); + s->ptimer_1Hz =3D ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); ptimer_set_freq(s->ptimer_1Hz, RTC_BASE_FREQ); =20 sysbus_init_irq(dev, &s->alm_irq); diff --git a/hw/timer/grlib_gptimer.c b/hw/timer/grlib_gptimer.c index 32dbf870d4b..bb09268ea14 100644 --- a/hw/timer/grlib_gptimer.c +++ b/hw/timer/grlib_gptimer.c @@ -366,7 +366,7 @@ static void grlib_gptimer_realize(DeviceState *dev, Err= or **errp) =20 timer->unit =3D unit; timer->bh =3D qemu_bh_new(grlib_gptimer_hit, timer); - timer->ptimer =3D ptimer_init(timer->bh, PTIMER_POLICY_DEFAULT); + timer->ptimer =3D ptimer_init_with_bh(timer->bh, PTIMER_POLICY_DEF= AULT); timer->id =3D i; =20 /* One IRQ line for each timer */ diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c index f54e059910b..39810ac8b03 100644 --- a/hw/timer/imx_epit.c +++ b/hw/timer/imx_epit.c @@ -317,10 +317,10 @@ static void imx_epit_realize(DeviceState *dev, Error = **errp) 0x00001000); sysbus_init_mmio(sbd, &s->iomem); =20 - s->timer_reload =3D ptimer_init(NULL, PTIMER_POLICY_DEFAULT); + s->timer_reload =3D ptimer_init_with_bh(NULL, PTIMER_POLICY_DEFAULT); =20 bh =3D qemu_bh_new(imx_epit_cmp, s); - s->timer_cmp =3D ptimer_init(bh, PTIMER_POLICY_DEFAULT); + s->timer_cmp =3D ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); } =20 static void imx_epit_class_init(ObjectClass *klass, void *data) diff --git a/hw/timer/imx_gpt.c b/hw/timer/imx_gpt.c index 49a441f4517..c535d191292 100644 --- a/hw/timer/imx_gpt.c +++ b/hw/timer/imx_gpt.c @@ -492,7 +492,7 @@ static void imx_gpt_realize(DeviceState *dev, Error **e= rrp) sysbus_init_mmio(sbd, &s->iomem); =20 bh =3D qemu_bh_new(imx_gpt_timeout, s); - s->timer =3D ptimer_init(bh, PTIMER_POLICY_DEFAULT); + s->timer =3D ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); } =20 static void imx_gpt_class_init(ObjectClass *klass, void *data) diff --git a/hw/timer/lm32_timer.c b/hw/timer/lm32_timer.c index ac3edaff4f8..f79f818d22c 100644 --- a/hw/timer/lm32_timer.c +++ b/hw/timer/lm32_timer.c @@ -187,7 +187,7 @@ static void lm32_timer_init(Object *obj) sysbus_init_irq(dev, &s->irq); =20 s->bh =3D qemu_bh_new(timer_hit, s); - s->ptimer =3D ptimer_init(s->bh, PTIMER_POLICY_DEFAULT); + s->ptimer =3D ptimer_init_with_bh(s->bh, PTIMER_POLICY_DEFAULT); =20 memory_region_init_io(&s->iomem, obj, &timer_ops, s, "timer", R_MAX * 4); diff --git a/hw/timer/milkymist-sysctl.c b/hw/timer/milkymist-sysctl.c index 958350767ae..aeba889bba4 100644 --- a/hw/timer/milkymist-sysctl.c +++ b/hw/timer/milkymist-sysctl.c @@ -285,8 +285,8 @@ static void milkymist_sysctl_init(Object *obj) =20 s->bh0 =3D qemu_bh_new(timer0_hit, s); s->bh1 =3D qemu_bh_new(timer1_hit, s); - s->ptimer0 =3D ptimer_init(s->bh0, PTIMER_POLICY_DEFAULT); - s->ptimer1 =3D ptimer_init(s->bh1, PTIMER_POLICY_DEFAULT); + s->ptimer0 =3D ptimer_init_with_bh(s->bh0, PTIMER_POLICY_DEFAULT); + s->ptimer1 =3D ptimer_init_with_bh(s->bh1, PTIMER_POLICY_DEFAULT); =20 memory_region_init_io(&s->regs_region, obj, &sysctl_mmio_ops, s, "milkymist-sysctl", R_MAX * 4); diff --git a/hw/timer/mss-timer.c b/hw/timer/mss-timer.c index 45f1cf42f9e..a34c2402b00 100644 --- a/hw/timer/mss-timer.c +++ b/hw/timer/mss-timer.c @@ -229,7 +229,7 @@ static void mss_timer_init(Object *obj) struct Msf2Timer *st =3D &t->timers[i]; =20 st->bh =3D qemu_bh_new(timer_hit, st); - st->ptimer =3D ptimer_init(st->bh, PTIMER_POLICY_DEFAULT); + st->ptimer =3D ptimer_init_with_bh(st->bh, PTIMER_POLICY_DEFAULT); ptimer_set_freq(st->ptimer, t->freq_hz); sysbus_init_irq(SYS_BUS_DEVICE(obj), &st->irq); } diff --git a/hw/timer/puv3_ost.c b/hw/timer/puv3_ost.c index 6fe370049b5..0898da5ce97 100644 --- a/hw/timer/puv3_ost.c +++ b/hw/timer/puv3_ost.c @@ -129,7 +129,7 @@ static void puv3_ost_realize(DeviceState *dev, Error **= errp) sysbus_init_irq(sbd, &s->irq); =20 s->bh =3D qemu_bh_new(puv3_ost_tick, s); - s->ptimer =3D ptimer_init(s->bh, PTIMER_POLICY_DEFAULT); + s->ptimer =3D ptimer_init_with_bh(s->bh, PTIMER_POLICY_DEFAULT); ptimer_set_freq(s->ptimer, 50 * 1000 * 1000); =20 memory_region_init_io(&s->iomem, OBJECT(s), &puv3_ost_ops, s, "puv3_os= t", diff --git a/hw/timer/sh_timer.c b/hw/timer/sh_timer.c index adcc0c138e7..48a81b4dc79 100644 --- a/hw/timer/sh_timer.c +++ b/hw/timer/sh_timer.c @@ -204,7 +204,7 @@ static void *sh_timer_init(uint32_t freq, int feat, qem= u_irq irq) s->irq =3D irq; =20 bh =3D qemu_bh_new(sh_timer_tick, s); - s->timer =3D ptimer_init(bh, PTIMER_POLICY_DEFAULT); + s->timer =3D ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); =20 sh_timer_write(s, OFFSET_TCOR >> 2, s->tcor); sh_timer_write(s, OFFSET_TCNT >> 2, s->tcnt); diff --git a/hw/timer/slavio_timer.c b/hw/timer/slavio_timer.c index 38fd32b62a0..692d213897d 100644 --- a/hw/timer/slavio_timer.c +++ b/hw/timer/slavio_timer.c @@ -393,7 +393,7 @@ static void slavio_timer_init(Object *obj) tc->timer_index =3D i; =20 bh =3D qemu_bh_new(slavio_timer_irq, tc); - s->cputimer[i].timer =3D ptimer_init(bh, PTIMER_POLICY_DEFAULT); + s->cputimer[i].timer =3D ptimer_init_with_bh(bh, PTIMER_POLICY_DEF= AULT); ptimer_set_period(s->cputimer[i].timer, TIMER_PERIOD); =20 size =3D i =3D=3D 0 ? SYS_TIMER_SIZE : CPU_TIMER_SIZE; diff --git a/hw/timer/xilinx_timer.c b/hw/timer/xilinx_timer.c index 355518232cd..92dbff304d9 100644 --- a/hw/timer/xilinx_timer.c +++ b/hw/timer/xilinx_timer.c @@ -221,7 +221,7 @@ static void xilinx_timer_realize(DeviceState *dev, Erro= r **errp) xt->parent =3D t; xt->nr =3D i; xt->bh =3D qemu_bh_new(timer_hit, xt); - xt->ptimer =3D ptimer_init(xt->bh, PTIMER_POLICY_DEFAULT); + xt->ptimer =3D ptimer_init_with_bh(xt->bh, PTIMER_POLICY_DEFAULT); ptimer_set_freq(xt->ptimer, t->freq_hz); } =20 diff --git a/hw/watchdog/cmsdk-apb-watchdog.c b/hw/watchdog/cmsdk-apb-watch= dog.c index 6bf43f943fb..e42c3ebd29d 100644 --- a/hw/watchdog/cmsdk-apb-watchdog.c +++ b/hw/watchdog/cmsdk-apb-watchdog.c @@ -329,7 +329,7 @@ static void cmsdk_apb_watchdog_realize(DeviceState *dev= , Error **errp) } =20 bh =3D qemu_bh_new(cmsdk_apb_watchdog_tick, s); - s->timer =3D ptimer_init(bh, + s->timer =3D ptimer_init_with_bh(bh, PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD | PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT | PTIMER_POLICY_NO_IMMEDIATE_RELOAD | diff --git a/tests/ptimer-test.c b/tests/ptimer-test.c index 5b20e91599e..a3c82d1d147 100644 --- a/tests/ptimer-test.c +++ b/tests/ptimer-test.c @@ -68,7 +68,7 @@ static void check_set_count(gconstpointer arg) { const uint8_t *policy =3D arg; QEMUBH *bh =3D qemu_bh_new(ptimer_trigger, NULL); - ptimer_state *ptimer =3D ptimer_init(bh, *policy); + ptimer_state *ptimer =3D ptimer_init_with_bh(bh, *policy); =20 triggered =3D false; =20 @@ -82,7 +82,7 @@ static void check_set_limit(gconstpointer arg) { const uint8_t *policy =3D arg; QEMUBH *bh =3D qemu_bh_new(ptimer_trigger, NULL); - ptimer_state *ptimer =3D ptimer_init(bh, *policy); + ptimer_state *ptimer =3D ptimer_init_with_bh(bh, *policy); =20 triggered =3D false; =20 @@ -102,7 +102,7 @@ static void check_oneshot(gconstpointer arg) { const uint8_t *policy =3D arg; QEMUBH *bh =3D qemu_bh_new(ptimer_trigger, NULL); - ptimer_state *ptimer =3D ptimer_init(bh, *policy); + ptimer_state *ptimer =3D ptimer_init_with_bh(bh, *policy); bool no_round_down =3D (*policy & PTIMER_POLICY_NO_COUNTER_ROUND_DOWN); =20 triggered =3D false; @@ -205,7 +205,7 @@ static void check_periodic(gconstpointer arg) { const uint8_t *policy =3D arg; QEMUBH *bh =3D qemu_bh_new(ptimer_trigger, NULL); - ptimer_state *ptimer =3D ptimer_init(bh, *policy); + ptimer_state *ptimer =3D ptimer_init_with_bh(bh, *policy); bool wrap_policy =3D (*policy & PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD); bool no_immediate_trigger =3D (*policy & PTIMER_POLICY_NO_IMMEDIATE_TR= IGGER); bool no_immediate_reload =3D (*policy & PTIMER_POLICY_NO_IMMEDIATE_REL= OAD); @@ -373,7 +373,7 @@ static void check_on_the_fly_mode_change(gconstpointer = arg) { const uint8_t *policy =3D arg; QEMUBH *bh =3D qemu_bh_new(ptimer_trigger, NULL); - ptimer_state *ptimer =3D ptimer_init(bh, *policy); + ptimer_state *ptimer =3D ptimer_init_with_bh(bh, *policy); bool wrap_policy =3D (*policy & PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD); bool no_round_down =3D (*policy & PTIMER_POLICY_NO_COUNTER_ROUND_DOWN); =20 @@ -420,7 +420,7 @@ static void check_on_the_fly_period_change(gconstpointe= r arg) { const uint8_t *policy =3D arg; QEMUBH *bh =3D qemu_bh_new(ptimer_trigger, NULL); - ptimer_state *ptimer =3D ptimer_init(bh, *policy); + ptimer_state *ptimer =3D ptimer_init_with_bh(bh, *policy); bool no_round_down =3D (*policy & PTIMER_POLICY_NO_COUNTER_ROUND_DOWN); =20 triggered =3D false; @@ -453,7 +453,7 @@ static void check_on_the_fly_freq_change(gconstpointer = arg) { const uint8_t *policy =3D arg; QEMUBH *bh =3D qemu_bh_new(ptimer_trigger, NULL); - ptimer_state *ptimer =3D ptimer_init(bh, *policy); + ptimer_state *ptimer =3D ptimer_init_with_bh(bh, *policy); bool no_round_down =3D (*policy & PTIMER_POLICY_NO_COUNTER_ROUND_DOWN); =20 triggered =3D false; @@ -486,7 +486,7 @@ static void check_run_with_period_0(gconstpointer arg) { const uint8_t *policy =3D arg; QEMUBH *bh =3D qemu_bh_new(ptimer_trigger, NULL); - ptimer_state *ptimer =3D ptimer_init(bh, *policy); + ptimer_state *ptimer =3D ptimer_init_with_bh(bh, *policy); =20 triggered =3D false; =20 @@ -504,7 +504,7 @@ static void check_run_with_delta_0(gconstpointer arg) { const uint8_t *policy =3D arg; QEMUBH *bh =3D qemu_bh_new(ptimer_trigger, NULL); - ptimer_state *ptimer =3D ptimer_init(bh, *policy); + ptimer_state *ptimer =3D ptimer_init_with_bh(bh, *policy); bool wrap_policy =3D (*policy & PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD); bool no_immediate_trigger =3D (*policy & PTIMER_POLICY_NO_IMMEDIATE_TR= IGGER); bool no_immediate_reload =3D (*policy & PTIMER_POLICY_NO_IMMEDIATE_REL= OAD); @@ -610,7 +610,7 @@ static void check_periodic_with_load_0(gconstpointer ar= g) { const uint8_t *policy =3D arg; QEMUBH *bh =3D qemu_bh_new(ptimer_trigger, NULL); - ptimer_state *ptimer =3D ptimer_init(bh, *policy); + ptimer_state *ptimer =3D ptimer_init_with_bh(bh, *policy); bool continuous_trigger =3D (*policy & PTIMER_POLICY_CONTINUOUS_TRIGGE= R); bool no_immediate_trigger =3D (*policy & PTIMER_POLICY_NO_IMMEDIATE_TR= IGGER); bool trig_only_on_dec =3D (*policy & PTIMER_POLICY_TRIGGER_ONLY_ON_DEC= REMENT); @@ -670,7 +670,7 @@ static void check_oneshot_with_load_0(gconstpointer arg) { const uint8_t *policy =3D arg; QEMUBH *bh =3D qemu_bh_new(ptimer_trigger, NULL); - ptimer_state *ptimer =3D ptimer_init(bh, *policy); + ptimer_state *ptimer =3D ptimer_init_with_bh(bh, *policy); bool no_immediate_trigger =3D (*policy & PTIMER_POLICY_NO_IMMEDIATE_TR= IGGER); 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id t17sm11962094wrp.72.2019.10.04.04.48.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Oct 2019 04:48:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=aZ62Msi6+VMnCAAUmgOLUV4qO75/pTiQ0YCB2BZ1mjM=; b=SjkGs1W65IL/u/a4xu8YoHSuiFwdRvy9o2hk4tLqPV1ShQ/kNx6S+Mww4foH6r6xED LuwWpzB7V5vVvTtsJpGvL5tYEHEKqZ6CPCTccfVzvPb/ZnSRtwQzpwr0cDOdhMcpno++ 2jg2uzeY5dkQ1eeH58gwIS0NW0tN6N0qwejbbDu0oVIIOIKRdTJ9WXnBXW9kHA0/Ykda 4zhmPjlUp5b7RhLFVCJelKn+sTePQHJBpeeD3IVXX2nlckpwzB3ecbXS/KHr6vGLMrG/ zR2Xeq7FCQPRhQ1f+grxxj8MHKH1IDwAKc+uV++5pyoGfpcNW6Ps6WypH4+UsDVeunFO PETg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aZ62Msi6+VMnCAAUmgOLUV4qO75/pTiQ0YCB2BZ1mjM=; b=nMAcVosagYBEekugu9VuiEuNr0OriQookVd6JE+kpmGJ1SdXsVBrptGYqTNsmEoMoF VNYP/Q3iWYl7TAYFwobovdhOgAmpu4EoH9eW+ErvjRzRpWItKNty8fR/FHc9nn6axnxO urIhySYqMcJibt8J2YJDLgN21nEvEksPb4leGUBTDFC6s7pX2I+40OKIBC+WWD51pOpu qv/yrVyBRi7jnnA3kW/Hq+zQl13q+VahrYcat0Dz6w9HVoaHOOHkfG4/wWLYu/BUtDDz soZG4dt6Zzaw7pNkzytTcQ29vjKES5s6i5XmMGXbQykpZoG+YoEsq5u1pYs1vQMUdlr2 NyIg== X-Gm-Message-State: APjAAAV25oazygCencdiJ4XoEYiniYTEzd3/7OdyKjYsmwKfMyvpHhy8 wJDgsngx8ugezrQQhwAZMMZqPA== X-Google-Smtp-Source: APXvYqzdYcw65dFIEp+ZMbNGEjUW1Ich7+NTKb8jxHfedvrgl+ruX7T159fPPWI/rIaUPt8X6JCYBQ== X-Received: by 2002:a1c:980e:: with SMTP id a14mr10063954wme.99.1570189735425; Fri, 04 Oct 2019 04:48:55 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [RFC 3/4] ptimer: Provide new transaction-based API Date: Fri, 4 Oct 2019 12:48:47 +0100 Message-Id: <20191004114848.16831-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191004114848.16831-1-peter.maydell@linaro.org> References: <20191004114848.16831-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::332 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Paolo Bonzini Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Provide the new transaction-based API. If a ptimer is created using ptimer_init() rather than ptimer_init_with_bh(), then instead of providing a QEMUBH, it provides a pointer to the callback function directly, and has opted into the transaction API. All calls to functions which modify ptimer state: - ptimer_set_period() - ptimer_set_freq() - ptimer_set_limit() - ptimer_set_count() - ptimer_run() - ptimer_stop() must be between matched calls to ptimer_transaction_begin() and ptimer_transaction_commit(). When ptimer_transaction_commit() is called it will evaluate the state of the timer after all the changes in the transaction, and call the callback if necessary. In the old API the individual update functions generally would call ptimer_trigger() immediately, which would schedule the QEMUBH. In the new API the update functions will instead defer the "set s->next_event and call ptimer_reload()" work to ptimer_transaction_commit(). We use assertions to check that: * the functions modifying ptimer state are not called outside a transaction block * ptimer_transaction_begin() and _commit() calls are paired * the transaction API is not used with a QEMUBH ptimer There is some slight repetition of code: * most of the set functions have similar looking "if s->bh call ptimer_reload, otherwise set s->need_reload" code * ptimer_init() and ptimer_init_with_bh() have similar code We deliberately don't try to avoid this repetition, because it will all be deleted when the QEMUBH version of the API is removed. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/hw/ptimer.h | 66 +++++++++++++++++++++++++ hw/core/ptimer.c | 114 +++++++++++++++++++++++++++++++++++++++----- 2 files changed, 169 insertions(+), 11 deletions(-) diff --git a/include/hw/ptimer.h b/include/hw/ptimer.h index 2fb9ba1915e..b9cd301ab02 100644 --- a/include/hw/ptimer.h +++ b/include/hw/ptimer.h @@ -91,6 +91,32 @@ typedef void (*ptimer_cb)(void *opaque); */ ptimer_state *ptimer_init_with_bh(QEMUBH *bh, uint8_t policy_mask); =20 +/** + * ptimer_init - Allocate and return a new ptimer + * @callback: function to call on ptimer expiry + * @callback_data: opaque pointer passed to @callback + * @policy: PTIMER_POLICY_* bits specifying behaviour + * + * The ptimer returned must be freed using ptimer_free(). + * + * If a ptimer is created using this API then will use the + * transaction-based API for modifying ptimer state: all calls + * to functions which modify ptimer state: + * - ptimer_set_period() + * - ptimer_set_freq() + * - ptimer_set_limit() + * - ptimer_set_count() + * - ptimer_run() + * - ptimer_stop() + * must be between matched calls to ptimer_transaction_begin() + * and ptimer_transaction_commit(). When ptimer_transaction_commit() + * is called it will evaluate the state of the timer after all the + * changes in the transaction, and call the callback if necessary. + */ +ptimer_state *ptimer_init(ptimer_cb callback, + void *callback_opaque, + uint8_t policy_mask); + /** * ptimer_free - Free a ptimer * @s: timer to free @@ -100,6 +126,28 @@ ptimer_state *ptimer_init_with_bh(QEMUBH *bh, uint8_t = policy_mask); */ void ptimer_free(ptimer_state *s); =20 +/** + * ptimer_transaction_begin() - Start a ptimer modification transaction + * + * This function must be called before making any calls to functions + * which modify the ptimer's state (see the ptimer_init() documentation + * for a list of these), and must always have a matched call to + * ptimer_transaction_commit(). + * It is an error to call this function for a BH-based ptimer; + * attempting to do this will trigger an assert. + */ +void ptimer_transaction_begin(ptimer_state *s); + +/** + * ptimer_transaction_commit() - Commit a ptimer modification transaction + * + * This function must be called after calls to functions which modify + * the ptimer's state, and completes the update of the ptimer. If the + * ptimer state now means that we should trigger the timer expiry + * callback, it will be called directly. + */ +void ptimer_transaction_commit(ptimer_state *s); + /** * ptimer_set_period - Set counter increment interval in nanoseconds * @s: ptimer to configure @@ -108,6 +156,9 @@ void ptimer_free(ptimer_state *s); * Note that if your counter behaviour is specified as having a * particular frequency rather than a period then ptimer_set_freq() * may be more appropriate. + * + * This function will assert if it is called outside a + * ptimer_transaction_begin/commit block, unless this is a bottom-half pti= mer. */ void ptimer_set_period(ptimer_state *s, int64_t period); =20 @@ -121,6 +172,9 @@ void ptimer_set_period(ptimer_state *s, int64_t period); * as setting the frequency then this function is more appropriate, * because it allows specifying an effective period which is * precise to fractions of a nanosecond, avoiding rounding errors. + * + * This function will assert if it is called outside a + * ptimer_transaction_begin/commit block, unless this is a bottom-half pti= mer. */ void ptimer_set_freq(ptimer_state *s, uint32_t freq); =20 @@ -148,6 +202,9 @@ uint64_t ptimer_get_limit(ptimer_state *s); * Set the limit value of the down-counter. The @reload flag can * be used to emulate the behaviour of timers which immediately * reload the counter when their reload register is written to. + * + * This function will assert if it is called outside a + * ptimer_transaction_begin/commit block, unless this is a bottom-half pti= mer. */ void ptimer_set_limit(ptimer_state *s, uint64_t limit, int reload); =20 @@ -169,6 +226,9 @@ uint64_t ptimer_get_count(ptimer_state *s); * Set the value of the down-counter. If the counter is currently * enabled this will arrange for a timer callback at the appropriate * point in the future. + * + * This function will assert if it is called outside a + * ptimer_transaction_begin/commit block, unless this is a bottom-half pti= mer. */ void ptimer_set_count(ptimer_state *s, uint64_t count); =20 @@ -183,6 +243,9 @@ void ptimer_set_count(ptimer_state *s, uint64_t count); * the counter value will then be reloaded from the limit and it will * start counting down again. If @oneshot is non-zero, then the counter * will disable itself when it reaches zero. + * + * This function will assert if it is called outside a + * ptimer_transaction_begin/commit block, unless this is a bottom-half pti= mer. */ void ptimer_run(ptimer_state *s, int oneshot); =20 @@ -195,6 +258,9 @@ void ptimer_run(ptimer_state *s, int oneshot); * * Note that this can cause it to "lose" time, even if it is immediately * restarted. + * + * This function will assert if it is called outside a + * ptimer_transaction_begin/commit block, unless this is a bottom-half pti= mer. */ void ptimer_stop(ptimer_state *s); =20 diff --git a/hw/core/ptimer.c b/hw/core/ptimer.c index f0d3ce11398..89228132650 100644 --- a/hw/core/ptimer.c +++ b/hw/core/ptimer.c @@ -31,6 +31,16 @@ struct ptimer_state uint8_t policy_mask; QEMUBH *bh; QEMUTimer *timer; + ptimer_cb callback; + void *callback_opaque; + /* + * These track whether we're in a transaction block, and if we + * need to do a timer reload when the block finishes. They don't + * need to be migrated because migration can never happen in the + * middle of a transaction block. + */ + bool in_transaction; + bool need_reload; }; =20 /* Use a bottom-half routine to avoid reentrancy issues. */ @@ -39,6 +49,9 @@ static void ptimer_trigger(ptimer_state *s) if (s->bh) { replay_bh_schedule_event(s->bh); } + if (s->callback) { + s->callback(s->callback_opaque); + } } =20 static void ptimer_reload(ptimer_state *s, int delta_adjust) @@ -263,10 +276,15 @@ uint64_t ptimer_get_count(ptimer_state *s) =20 void ptimer_set_count(ptimer_state *s, uint64_t count) { + assert(s->in_transaction || !s->callback); s->delta =3D count; if (s->enabled) { - s->next_event =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); - ptimer_reload(s, 0); + if (!s->callback) { + s->next_event =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + ptimer_reload(s, 0); + } else { + s->need_reload =3D true; + } } } =20 @@ -274,6 +292,8 @@ void ptimer_run(ptimer_state *s, int oneshot) { bool was_disabled =3D !s->enabled; =20 + assert(s->in_transaction || !s->callback); + if (was_disabled && s->period =3D=3D 0) { if (!qtest_enabled()) { fprintf(stderr, "Timer with period zero, disabling\n"); @@ -282,8 +302,12 @@ void ptimer_run(ptimer_state *s, int oneshot) } s->enabled =3D oneshot ? 2 : 1; if (was_disabled) { - s->next_event =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); - ptimer_reload(s, 0); + if (!s->callback) { + s->next_event =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + ptimer_reload(s, 0); + } else { + s->need_reload =3D true; + } } } =20 @@ -291,35 +315,50 @@ void ptimer_run(ptimer_state *s, int oneshot) is immediately restarted. */ void ptimer_stop(ptimer_state *s) { + assert(s->in_transaction || !s->callback); + if (!s->enabled) return; =20 s->delta =3D ptimer_get_count(s); timer_del(s->timer); s->enabled =3D 0; + if (s->callback) { + s->need_reload =3D false; + } } =20 /* Set counter increment interval in nanoseconds. */ void ptimer_set_period(ptimer_state *s, int64_t period) { + assert(s->in_transaction || !s->callback); s->delta =3D ptimer_get_count(s); s->period =3D period; s->period_frac =3D 0; if (s->enabled) { - s->next_event =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); - ptimer_reload(s, 0); + if (!s->callback) { + s->next_event =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + ptimer_reload(s, 0); + } else { + s->need_reload =3D true; + } } } =20 /* Set counter frequency in Hz. */ void ptimer_set_freq(ptimer_state *s, uint32_t freq) { + assert(s->in_transaction || !s->callback); s->delta =3D ptimer_get_count(s); s->period =3D 1000000000ll / freq; s->period_frac =3D (1000000000ll << 32) / freq; if (s->enabled) { - s->next_event =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); - ptimer_reload(s, 0); + if (!s->callback) { + s->next_event =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + ptimer_reload(s, 0); + } else { + s->need_reload =3D true; + } } } =20 @@ -327,12 +366,17 @@ void ptimer_set_freq(ptimer_state *s, uint32_t freq) count =3D limit. */ void ptimer_set_limit(ptimer_state *s, uint64_t limit, int reload) { + assert(s->in_transaction || !s->callback); s->limit =3D limit; if (reload) s->delta =3D limit; if (s->enabled && reload) { - s->next_event =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); - ptimer_reload(s, 0); + if (!s->callback) { + s->next_event =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + ptimer_reload(s, 0); + } else { + s->need_reload =3D true; + } } } =20 @@ -341,6 +385,22 @@ uint64_t ptimer_get_limit(ptimer_state *s) return s->limit; } =20 +void ptimer_transaction_begin(ptimer_state *s) +{ + assert(!s->in_transaction && s->callback); + s->in_transaction =3D true; +} + +void ptimer_transaction_commit(ptimer_state *s) +{ + assert(s->in_transaction); + s->in_transaction =3D false; + if (s->need_reload) { + s->next_event =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + ptimer_reload(s, 0); + } +} + const VMStateDescription vmstate_ptimer =3D { .name =3D "ptimer", .version_id =3D 1, @@ -377,9 +437,41 @@ ptimer_state *ptimer_init_with_bh(QEMUBH *bh, uint8_t = policy_mask) return s; } =20 +ptimer_state *ptimer_init(ptimer_cb callback, void *callback_opaque, + uint8_t policy_mask) +{ + ptimer_state *s; + + /* + * The callback function is mandatory; so we use it to distinguish + * old-style QEMUBH ptimers from new transaction API ptimers. + * (ptimer_init_with_bh() allows a NULL bh pointer and at least + * one device (digic-timer) passes NULL, so it's not the case + * that either s->bh !=3D NULL or s->callback !=3D NULL.) + */ + assert(callback); + + s =3D g_new0(ptimer_state, 1); + s->timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, ptimer_tick, s); + s->policy_mask =3D policy_mask; + s->callback =3D callback; + s->callback_opaque =3D callback_opaque; + + /* + * These two policies are incompatible -- trigger-on-decrement implies + * a timer trigger when the count becomes 0, but no-immediate-trigger + * implies a trigger when the count stops being 0. + */ + assert(!((policy_mask & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT) && + (policy_mask & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER))); + return s; +} + void ptimer_free(ptimer_state *s) { - qemu_bh_delete(s->bh); + if (s->bh) { + qemu_bh_delete(s->bh); + } timer_free(s->timer); g_free(s); } --=20 2.20.1 From nobody Sat May 18 19:12:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1570190972; cv=none; d=zoho.com; s=zohoarc; b=F0vD3/xXUm+LTryEGfEDsDaD2rbjCroDcYYhrS6BRb8Pir/RocUX2skxia7Cqzm0u0whYEP53CnEYEl5n/NNYtg7G01xaNXakSJCUuWpQUhWM4Y8Olm34ngPCXSTJtb/WbQKTH/ztAdMtlConevpOvOB9O3Ae3mzs2UtiiWjIHo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1570190972; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id t17sm11962094wrp.72.2019.10.04.04.48.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Oct 2019 04:48:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vp4+p4FLQruJ614qug2AywQIur5rU9O0ZC+bqOyPTzg=; b=y0eYyBKuPQJhvyzvNExbbBu6LW/3Kxgz85hSt9/HVrhIy+FDQM7xSQXE+ifLU+VkOg FRqufp2Rnq4q7dvSYOBS1UYZKKoTvJXE1masHBdAaY9K/NuiPf6Zf/ecrY9qdDmNSACC BSez378zfyIJ/OT6T/XXP1rvYXtgePMRMnJXx78GhqOL7G6PfV4YfSKoCs+xRY4+0sWX S+8LxZUSFs2V8Exd6GyW6Zh2P/E0JFWUsglJLJt3AgUVF/0NFMEMvLEBbYwR6PDBQ6ZY 4rNA0J5CGxorpWBcZJUgeRduBC3o3RGtkn7pslDP+svPufJr94AVAeZiO60YL84pAxgN Is9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vp4+p4FLQruJ614qug2AywQIur5rU9O0ZC+bqOyPTzg=; b=sZRrDyS/x8+eEh2COmOcQ5Ri27p9vwYEYUD7jTmgEq6TBhfdw3Fqr2Awi/yH/3QvoC ve8AasIimNvk7Qpt5QFj/UAwiECYndRygjdG0jGhSSQvGtKYgTyVDqDhAGGPMFpn4TR3 6sfjtIEUii6SEmnOTqE1yfjlvaMxvj95tuk/1bPsMzXah9sp9HFF94KaZQGLrbgwtv/y BIEIUZxtBKwF2f7roDLU+lBefb031Xdkb40TEB9vOL9WOv21PjQUAZm3I2ScTQ7urSzu 1b9BdscMG7fwuQDdHAbqUsfTreHaZr0hW/XlbtC8eN516THYXix6v80EuLzejEPp1Gh1 fdvQ== X-Gm-Message-State: APjAAAVWQ798qugbje0YX+LLJZLgeUH8RRTKxPdJeJTBRkncPcF8l+FP E9XFRXO6omxigxW4dxkDwGRK8g== X-Google-Smtp-Source: APXvYqwv9JWnYMBhQx0Vc1pSAIDY1X/CQR/N7D2n4P2SrpbAXzjanCC4sib4WEY6rUD8SF2M8FYNLw== X-Received: by 2002:a5d:5403:: with SMTP id g3mr10640252wrv.338.1570189736840; Fri, 04 Oct 2019 04:48:56 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [RFC 4/4] hw/timer/arm_timer.c: Switch to transaction-based ptimer API Date: Fri, 4 Oct 2019 12:48:48 +0100 Message-Id: <20191004114848.16831-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191004114848.16831-1-peter.maydell@linaro.org> References: <20191004114848.16831-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Paolo Bonzini Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Switch the arm_timer.c code away from bottom-half based ptimers to the new transaction-based ptimer API. This just requires adding begin/commit calls around the various arms of arm_timer_write() that modify the ptimer state, and using the new ptimer_init() function to create the timer. Fixes: https://bugs.launchpad.net/qemu/+bug/1777777 Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/timer/arm_timer.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c index 848fbcb0e25..255def3deec 100644 --- a/hw/timer/arm_timer.c +++ b/hw/timer/arm_timer.c @@ -14,7 +14,6 @@ #include "hw/irq.h" #include "hw/ptimer.h" #include "hw/qdev-properties.h" -#include "qemu/main-loop.h" #include "qemu/module.h" #include "qemu/log.h" #include "trace.h" @@ -79,7 +78,10 @@ static uint32_t arm_timer_read(void *opaque, hwaddr offs= et) } } =20 -/* Reset the timer limit after settings have changed. */ +/* + * Reset the timer limit after settings have changed. + * May only be called from inside a ptimer transaction block. + */ static void arm_timer_recalibrate(arm_timer_state *s, int reload) { uint32_t limit; @@ -106,13 +108,16 @@ static void arm_timer_write(void *opaque, hwaddr offs= et, switch (offset >> 2) { case 0: /* TimerLoad */ s->limit =3D value; + ptimer_transaction_begin(s->timer); arm_timer_recalibrate(s, 1); + ptimer_transaction_commit(s->timer); break; case 1: /* TimerValue */ /* ??? Linux seems to want to write to this readonly register. Ignore it. */ break; case 2: /* TimerControl */ + ptimer_transaction_begin(s->timer); if (s->control & TIMER_CTRL_ENABLE) { /* Pause the timer if it is running. This may cause some inaccuracy dure to rounding, but avoids a whole lot of other @@ -132,13 +137,16 @@ static void arm_timer_write(void *opaque, hwaddr offs= et, /* Restart the timer if still enabled. */ ptimer_run(s->timer, (s->control & TIMER_CTRL_ONESHOT) !=3D 0); } + ptimer_transaction_commit(s->timer); break; case 3: /* TimerIntClr */ s->int_level =3D 0; break; case 6: /* TimerBGLoad */ s->limit =3D value; + ptimer_transaction_begin(s->timer); arm_timer_recalibrate(s, 0); + ptimer_transaction_commit(s->timer); break; default: qemu_log_mask(LOG_GUEST_ERROR, @@ -170,14 +178,12 @@ static const VMStateDescription vmstate_arm_timer =3D= { static arm_timer_state *arm_timer_init(uint32_t freq) { arm_timer_state *s; - QEMUBH *bh; =20 s =3D (arm_timer_state *)g_malloc0(sizeof(arm_timer_state)); s->freq =3D freq; s->control =3D TIMER_CTRL_IE; =20 - bh =3D qemu_bh_new(arm_timer_tick, s); - s->timer =3D ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); + s->timer =3D ptimer_init(arm_timer_tick, s, PTIMER_POLICY_DEFAULT); vmstate_register(NULL, -1, &vmstate_arm_timer, s); return s; } --=20 2.20.1