From nobody Wed Nov 12 11:54:55 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1570185619; cv=none; d=zoho.com; s=zohoarc; b=eeswf6HPEyrfsHqO9dyXUEdmARoGy444l5OYwBnlJ3KXNxknmmnv3QtVFiZ4zai4As8icV4UjuR8jzgji7D7Yr8AUeHlENL1gEsNIKX0YAMzdqgM0G16Wu65MQ5by+3WtKUrpIFceHEW2ZKYZNawaMkT2b3586KvXrfwSfP2HdA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1570185619; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=jCOZ9/ev7GB9BC0JLQfVjGWJXjUYxPKACoOWXOjE37o=; b=cZR6Bco4fYUt9JB9GKUniG1ijj6wlyJDGGpp3tSBknACawuAZkX5b/P/RunhMTjtOW8PpWdMYx8HejYRzVXrrlizI5JXALJFbIykFoBNE0Kwmtr55G+AUOTWXU8Vi1vfZeTMPumkjl9SiZO/AI58tChMCkm+IjEB4zx+6jepmQI= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1570185619701395.007979623134; Fri, 4 Oct 2019 03:40:19 -0700 (PDT) Received: from localhost ([::1]:45868 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iGL0U-0003tk-B0 for importer@patchew.org; Fri, 04 Oct 2019 06:40:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53843) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iGK3o-0006n3-M4 for qemu-devel@nongnu.org; Fri, 04 Oct 2019 05:39:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iGK3n-0006dd-AZ for qemu-devel@nongnu.org; Fri, 04 Oct 2019 05:39:40 -0400 Received: from bilbo.ozlabs.org ([203.11.71.1]:54975 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iGK3m-0006Iy-VX; Fri, 04 Oct 2019 05:39:39 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 46l4YT0SFdz9sSb; Fri, 4 Oct 2019 19:38:04 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1570181885; bh=FwPA1UCWDxFC1kFf5rMGk2U3mKvgbSbEKO/0mZf2f+4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TcVVaW/0RNZJzLd5+SGiEvLA1GfN1Yo2rBPSNvdLHdjhsxc6V7nEkCtNBX+KXni6d rQqiNuImyvIXE/+pD4dIUEQAESmwn6IL7RTaVV0l9Eex6Dx2tzYNeTGkRDz8snM/ym UX1Sp3DShrvS0/G/iJN36IYbOdOByG25trSDkyUI= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 50/53] spapr: Use less cryptic representation of which irq backends are supported Date: Fri, 4 Oct 2019 19:37:44 +1000 Message-Id: <20191004093747.31350-51-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191004093747.31350-1-david@gibson.dropbear.id.au> References: <20191004093747.31350-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" SpaprIrq::ov5 stores the value for a particular byte in PAPR option vector 5 which indicates whether XICS, XIVE or both interrupt controllers are available. As usual for PAPR, the encoding is kind of overly complicated and confusing (though to be fair there are some backwards compat things it has to handle). But to make our internal code clearer, have SpaprIrq encode more directly which backends are available as two booleans, and derive the OV5 value from that at the point we need it. Signed-off-by: David Gibson Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Greg Kurz --- hw/ppc/spapr.c | 15 ++++++++++++--- hw/ppc/spapr_hcall.c | 6 +++--- hw/ppc/spapr_irq.c | 12 ++++++++---- include/hw/ppc/spapr_irq.h | 3 ++- 4 files changed, 25 insertions(+), 11 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 43920c140d..514a17ae74 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -1066,19 +1066,28 @@ static void spapr_dt_ov5_platform_support(SpaprMach= ineState *spapr, void *fdt, PowerPCCPU *first_ppc_cpu =3D POWERPC_CPU(first_cpu); =20 char val[2 * 4] =3D { - 23, spapr->irq->ov5, /* Xive mode. */ + 23, 0x00, /* XICS / XIVE mode */ 24, 0x00, /* Hash/Radix, filled in below. */ 25, 0x00, /* Hash options: Segment Tables =3D=3D no, GTSE =3D=3D n= o. */ 26, 0x40, /* Radix options: GTSE =3D=3D yes. */ }; =20 + if (spapr->irq->xics && spapr->irq->xive) { + val[1] =3D SPAPR_OV5_XIVE_BOTH; + } else if (spapr->irq->xive) { + val[1] =3D SPAPR_OV5_XIVE_EXPLOIT; + } else { + assert(spapr->irq->xics); + val[1] =3D SPAPR_OV5_XIVE_LEGACY; + } + if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, first_ppc_cpu->compat_pvr)) { /* * If we're in a pre POWER9 compat mode then the guest should * do hash and use the legacy interrupt mode */ - val[1] =3D 0x00; /* XICS */ + val[1] =3D SPAPR_OV5_XIVE_LEGACY; /* XICS */ val[3] =3D 0x00; /* Hash */ } else if (kvm_enabled()) { if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { @@ -2767,7 +2776,7 @@ static void spapr_machine_init(MachineState *machine) spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); =20 /* advertise XIVE on POWER9 machines */ - if (spapr->irq->ov5 & (SPAPR_OV5_XIVE_EXPLOIT | SPAPR_OV5_XIVE_BOTH)) { + if (spapr->irq->xive) { spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); } =20 diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index 3d3a67149a..140f05c1c6 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc/spapr_hcall.c @@ -1784,13 +1784,13 @@ static target_ulong h_client_architecture_support(P= owerPCCPU *cpu, * terminate the boot. */ if (guest_xive) { - if (spapr->irq->ov5 =3D=3D SPAPR_OV5_XIVE_LEGACY) { + if (!spapr->irq->xive) { error_report( "Guest requested unavailable interrupt mode (XIVE), try the ic-mode=3Dxive= or ic-mode=3Ddual machine property"); exit(EXIT_FAILURE); } } else { - if (spapr->irq->ov5 =3D=3D SPAPR_OV5_XIVE_EXPLOIT) { + if (!spapr->irq->xics) { error_report( "Guest requested unavailable interrupt mode (XICS), either don't set the i= c-mode machine property or try ic-mode=3Dxics or ic-mode=3Ddual"); exit(EXIT_FAILURE); @@ -1804,7 +1804,7 @@ static target_ulong h_client_architecture_support(Pow= erPCCPU *cpu, */ if (!spapr->cas_reboot) { spapr->cas_reboot =3D spapr_ovec_test(ov5_updates, OV5_XIVE_EXPLOI= T) - && spapr->irq->ov5 & SPAPR_OV5_XIVE_BOTH; + && spapr->irq->xics && spapr->irq->xive; } =20 spapr_ovec_cleanup(ov5_updates); diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c index 516bf00a35..3ac67ba0c7 100644 --- a/hw/ppc/spapr_irq.c +++ b/hw/ppc/spapr_irq.c @@ -210,7 +210,8 @@ static void spapr_irq_init_kvm_xics(SpaprMachineState *= spapr, Error **errp) SpaprIrq spapr_irq_xics =3D { .nr_xirqs =3D SPAPR_NR_XIRQS, .nr_msis =3D SPAPR_NR_MSIS, - .ov5 =3D SPAPR_OV5_XIVE_LEGACY, + .xics =3D true, + .xive =3D false, =20 .init =3D spapr_irq_init_xics, .claim =3D spapr_irq_claim_xics, @@ -350,7 +351,8 @@ static void spapr_irq_init_kvm_xive(SpaprMachineState *= spapr, Error **errp) SpaprIrq spapr_irq_xive =3D { .nr_xirqs =3D SPAPR_NR_XIRQS, .nr_msis =3D SPAPR_NR_MSIS, - .ov5 =3D SPAPR_OV5_XIVE_EXPLOIT, + .xics =3D false, + .xive =3D true, =20 .init =3D spapr_irq_init_xive, .claim =3D spapr_irq_claim_xive, @@ -511,7 +513,8 @@ static void spapr_irq_set_irq_dual(void *opaque, int ir= q, int val) SpaprIrq spapr_irq_dual =3D { .nr_xirqs =3D SPAPR_NR_XIRQS, .nr_msis =3D SPAPR_NR_MSIS, - .ov5 =3D SPAPR_OV5_XIVE_BOTH, + .xics =3D true, + .xive =3D true, =20 .init =3D spapr_irq_init_dual, .claim =3D spapr_irq_claim_dual, @@ -754,7 +757,8 @@ int spapr_irq_find(SpaprMachineState *spapr, int num, b= ool align, Error **errp) SpaprIrq spapr_irq_xics_legacy =3D { .nr_xirqs =3D SPAPR_IRQ_XICS_LEGACY_NR_XIRQS, .nr_msis =3D SPAPR_IRQ_XICS_LEGACY_NR_XIRQS, - .ov5 =3D SPAPR_OV5_XIVE_LEGACY, + .xics =3D true, + .xive =3D false, =20 .init =3D spapr_irq_init_xics, .claim =3D spapr_irq_claim_xics, diff --git a/include/hw/ppc/spapr_irq.h b/include/hw/ppc/spapr_irq.h index ed88b4599a..d3f3b85eb9 100644 --- a/include/hw/ppc/spapr_irq.h +++ b/include/hw/ppc/spapr_irq.h @@ -39,7 +39,8 @@ void spapr_irq_msi_free(SpaprMachineState *spapr, int irq= , uint32_t num); typedef struct SpaprIrq { uint32_t nr_xirqs; uint32_t nr_msis; - uint8_t ov5; + bool xics; + bool xive; =20 void (*init)(SpaprMachineState *spapr, Error **errp); int (*claim)(SpaprMachineState *spapr, int irq, bool lsi, Error **errp= ); --=20 2.21.0