From nobody Wed Nov 12 11:54:56 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1570182533; cv=none; d=zoho.com; s=zohoarc; b=n6o5l2s23YRF/O1dXA4hP65Eo0jwFXO3jc/VUah3y9mWBCbICAQdUbKxbHuZbHCrmNijinTfUU1fjrUBQgpdpsYbJaC2uwPkJKtTVHUf9jLHvMa7qQ6oACkSpWOb0HLNv6FEmYh7JcWE6rHiHGshrVjHQdvxADWKEPz10L/S0m4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1570182533; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=bvHHB5axSwtfkwAFNCd8pUy574K9wWDSg2eIvdhbRb0=; b=fvXXSqpOr9KJYVktCUMsoGUXaRzElBqVSJUQDi6swAYqeGyZUnVov4JC9PXPD52Cr4WKL0oLlaYOBq/6LgyIE2+0BNMEO2roLCxUVdc1cxmCiqS17R3vJc7SuE/xtMdQOFxoicB/UDOY5AOahvsNlFtUdtnf2aSfvMyHUi+vTG4= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1570182533832563.7951888620263; Fri, 4 Oct 2019 02:48:53 -0700 (PDT) Received: from localhost ([::1]:43850 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iGKCb-0006xC-T6 for importer@patchew.org; Fri, 04 Oct 2019 05:48:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52336) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iGK2H-0004ry-CO for qemu-devel@nongnu.org; Fri, 04 Oct 2019 05:38:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iGK2F-00054Q-Pc for qemu-devel@nongnu.org; Fri, 04 Oct 2019 05:38:05 -0400 Received: from ozlabs.org ([2401:3900:2:1::2]:45553) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iGK2F-0004zy-CV; Fri, 04 Oct 2019 05:38:03 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 46l4YG6W1Wz9sRM; Fri, 4 Oct 2019 19:37:54 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1570181874; bh=0zIgGb9ZpShprkbrlZSPiKcM+hjW4q8CoJVbG3S44vk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VGWQxzTt0C1RqOCOlXPwCiYu6N3RfohmiT2tC5PjZVyf/4uWn67oT8Agi0vNlAY/r RkGSPDeYE2MENl3mHkkFiRnr9NbzLOGXs/+2rg1vm76+tLh9Vl+1n4Inqz6I6ZTnjN UF2o+TazoGWxOSSKL85mxBW0ZWLlGWIbBfcx1NUE= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 12/53] ppc: Add support for 'mffsce' instruction Date: Fri, 4 Oct 2019 19:37:06 +1000 Message-Id: <20191004093747.31350-13-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191004093747.31350-1-david@gibson.dropbear.id.au> References: <20191004093747.31350-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, Richard Henderson , qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson , "Paul A. Clarke" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: "Paul A. Clarke" ISA 3.0B added a set of Floating-Point Status and Control Register (FPSCR) instructions: mffsce, mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl. This patch adds support for 'mffsce' instruction. 'mffsce' is identical to 'mffs', except that it also clears the exception enable bits in the FPSCR. On CPUs without support for 'mffsce' (below ISA 3.0), the instruction will execute identically to 'mffs'. Signed-off-by: Paul A. Clarke Reviewed-by: Richard Henderson Message-Id: <1568817082-1384-1-git-send-email-pc@us.ibm.com> Signed-off-by: David Gibson --- target/ppc/translate/fp-impl.inc.c | 30 ++++++++++++++++++++++++++++++ target/ppc/translate/fp-ops.inc.c | 2 ++ 2 files changed, 32 insertions(+) diff --git a/target/ppc/translate/fp-impl.inc.c b/target/ppc/translate/fp-i= mpl.inc.c index 75f9523b07..d8e27bf4d5 100644 --- a/target/ppc/translate/fp-impl.inc.c +++ b/target/ppc/translate/fp-impl.inc.c @@ -639,6 +639,36 @@ static void gen_mffsl(DisasContext *ctx) tcg_temp_free_i64(t0); } =20 +/* mffsce */ +static void gen_mffsce(DisasContext *ctx) +{ + TCGv_i64 t0; + TCGv_i32 mask; + + if (unlikely(!(ctx->insns_flags2 & PPC2_ISA300))) { + return gen_mffs(ctx); + } + + if (unlikely(!ctx->fpu_enabled)) { + gen_exception(ctx, POWERPC_EXCP_FPU); + return; + } + + t0 =3D tcg_temp_new_i64(); + + gen_reset_fpstatus(); + tcg_gen_extu_tl_i64(t0, cpu_fpscr); + set_fpr(rD(ctx->opcode), t0); + + /* Clear exception enable bits in the FPSCR. */ + tcg_gen_andi_i64(t0, t0, ~FP_ENABLES); + mask =3D tcg_const_i32(0x0003); + gen_helper_store_fpscr(cpu_env, t0, mask); + + tcg_temp_free_i32(mask); + tcg_temp_free_i64(t0); +} + static void gen_helper_mffscrn(DisasContext *ctx, TCGv_i64 t1) { TCGv_i64 t0 =3D tcg_temp_new_i64(); diff --git a/target/ppc/translate/fp-ops.inc.c b/target/ppc/translate/fp-op= s.inc.c index f2bcf0e67b..88fab65628 100644 --- a/target/ppc/translate/fp-ops.inc.c +++ b/target/ppc/translate/fp-ops.inc.c @@ -105,6 +105,8 @@ GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x00000001, PPC= _NONE, PPC2_VSX207), GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207), GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT), GEN_HANDLER_E_2(mffs, 0x3F, 0x07, 0x12, 0x00, 0x00000000, PPC_FLOAT, PPC_N= ONE), +GEN_HANDLER_E_2(mffsce, 0x3F, 0x07, 0x12, 0x01, 0x00000000, PPC_FLOAT, + PPC2_ISA300), GEN_HANDLER_E_2(mffsl, 0x3F, 0x07, 0x12, 0x18, 0x00000000, PPC_FLOAT, PPC2_ISA300), GEN_HANDLER_E_2(mffscrn, 0x3F, 0x07, 0x12, 0x16, 0x00000000, PPC_FLOAT, --=20 2.21.0