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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id r28sm15336802pfg.62.2019.09.30.13.21.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Sep 2019 13:21:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Cci9veTgtcLoAvyGrfQMINQKyTlVjrX+2t66fnd3opE=; b=v2LM3FdiLSTrNZWBFNixompm+O/X9LAqHsU0a9F5oL4ywBSSV87p+r3wbcQq/aKu3s RXgHzWeYjH5WBMiMNlzwV/zuPUZqiF+XbcUhw/zSVE1guCc0PPwDQjLAfUP9ZOxtxmBV z+ziOZaM68LeAf0x60Wk2a93YQNd763Kkip2DWzfmw/cIU12RpkAXhqg56wqCM2Nd+tQ evLISv48YkfzuWRKgQd+ZJTIoEudVHjSzOCQf3nHnCsNTuzKjGrBYdXhJ8jqkcJpO/hd 6rL9LEuTbHk2BiIfhbZCLQoughHJKqUlbzxRHPzEKz50wdC51MLHcKpyMZLEZrUqfz65 ja6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Cci9veTgtcLoAvyGrfQMINQKyTlVjrX+2t66fnd3opE=; b=VITR6wioXwoyFMqIy3/62ik0UMGL0yEgknpuZFgA9sMWycn5v0PezQujs0UTrI39/p Hnf1Sq4r22kYV+nc7b1UZulthKmcVTckORvWFcoarrgzlArT/u4MDfxUgtTdCeyik/oD ckk+7HL0vDX/wffH6ewKOKHv1BmnmNZ4oHA4uvTRUnBgX8j5HjRiYHc0rrR6I39xocCy 64XsOa+z8cRrn/OfXdLhQoEPyRug814UXvZm27tUsojT37wYyHEhHLiLtHgL1LkRayfP fkYxCWju00CQk/iGMw6UC7l9RHCxFvWdua0zq2f1uTVWK7atGaX5n/M4Qj7qhPJ31O9X 60CA== X-Gm-Message-State: APjAAAVbR0mO9L0HHrtZacyZWnD6C0+cM4oOPR72UJT225k9r0RVLiIu P/pMqUEvc7f4Lw21drYEFyHjvecPAN0= X-Google-Smtp-Source: APXvYqxwHdOcegh0z6KVaSBY4WklJQwWFG46mL6A46CEPv8nAffrIRNoUzoGxB2z6mHLmTs30KnI/w== X-Received: by 2002:a17:90a:7d06:: with SMTP id g6mr1099175pjl.53.1569874912837; Mon, 30 Sep 2019 13:21:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v7 20/22] tcg/ppc: Update vector support for v3.00 Altivec Date: Mon, 30 Sep 2019 13:21:23 -0700 Message-Id: <20190930202125.21064-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190930202125.21064-1-richard.henderson@linaro.org> References: <20190930202125.21064-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.cave-ayland@ilande.co.uk, amarkovic@wavecomp.com, hsp.cat7@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" These new instructions are conditional only on MSR.VEC and are thus part of the Altivec instruction set, and not VSX. This includes negation and compare not equal. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.h | 2 +- tcg/ppc/tcg-target.inc.c | 23 +++++++++++++++++++++++ 2 files changed, 24 insertions(+), 1 deletion(-) diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 13197eddce..4fa21f0e71 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -159,7 +159,7 @@ extern bool have_vsx; #define TCG_TARGET_HAS_andc_vec 1 #define TCG_TARGET_HAS_orc_vec have_isa_2_07 #define TCG_TARGET_HAS_not_vec 1 -#define TCG_TARGET_HAS_neg_vec 0 +#define TCG_TARGET_HAS_neg_vec have_isa_3_00 #define TCG_TARGET_HAS_abs_vec 0 #define TCG_TARGET_HAS_shi_vec 0 #define TCG_TARGET_HAS_shs_vec 0 diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 840464aab5..bd9259c60f 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -499,6 +499,9 @@ static int tcg_target_const_match(tcg_target_long val, = TCGType type, #define VSUBUWM VX4(1152) #define VSUBUDM VX4(1216) /* v2.07 */ =20 +#define VNEGW (VX4(1538) | (6 << 16)) /* v3.00 */ +#define VNEGD (VX4(1538) | (7 << 16)) /* v3.00 */ + #define VMAXSB VX4(258) #define VMAXSH VX4(322) #define VMAXSW VX4(386) @@ -528,6 +531,9 @@ static int tcg_target_const_match(tcg_target_long val, = TCGType type, #define VCMPGTUH VX4(582) #define VCMPGTUW VX4(646) #define VCMPGTUD VX4(711) /* v2.07 */ +#define VCMPNEB VX4(7) /* v3.00 */ +#define VCMPNEH VX4(71) /* v3.00 */ +#define VCMPNEW VX4(135) /* v3.00 */ =20 #define VSLB VX4(260) #define VSLH VX4(324) @@ -2976,6 +2982,8 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, = unsigned vece) case INDEX_op_shri_vec: case INDEX_op_sari_vec: return vece <=3D MO_32 || have_isa_2_07 ? -1 : 0; + case INDEX_op_neg_vec: + return vece >=3D MO_32 && have_isa_3_00; case INDEX_op_mul_vec: switch (vece) { case MO_8: @@ -3090,7 +3098,9 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode o= pc, static const uint32_t add_op[4] =3D { VADDUBM, VADDUHM, VADDUWM, VADDUDM }, sub_op[4] =3D { VSUBUBM, VSUBUHM, VSUBUWM, VSUBUDM }, + neg_op[4] =3D { 0, 0, VNEGW, VNEGD }, eq_op[4] =3D { VCMPEQUB, VCMPEQUH, VCMPEQUW, VCMPEQUD }, + ne_op[4] =3D { VCMPNEB, VCMPNEH, VCMPNEW, 0 }, gts_op[4] =3D { VCMPGTSB, VCMPGTSH, VCMPGTSW, VCMPGTSD }, gtu_op[4] =3D { VCMPGTUB, VCMPGTUH, VCMPGTUW, VCMPGTUD }, ssadd_op[4] =3D { VADDSBS, VADDSHS, VADDSWS, 0 }, @@ -3132,6 +3142,11 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, case INDEX_op_sub_vec: insn =3D sub_op[vece]; break; + case INDEX_op_neg_vec: + insn =3D neg_op[vece]; + a2 =3D a1; + a1 =3D 0; + break; case INDEX_op_mul_vec: tcg_debug_assert(vece =3D=3D MO_32 && have_isa_2_07); insn =3D VMULUWM; @@ -3194,6 +3209,9 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode o= pc, case TCG_COND_EQ: insn =3D eq_op[vece]; break; + case TCG_COND_NE: + insn =3D ne_op[vece]; + break; case TCG_COND_GT: insn =3D gts_op[vece]; break; @@ -3276,6 +3294,10 @@ static void expand_vec_cmp(TCGType type, unsigned ve= ce, TCGv_vec v0, case TCG_COND_GTU: break; case TCG_COND_NE: + if (have_isa_3_00 && vece <=3D MO_32) { + break; + } + /* fall through */ case TCG_COND_LE: case TCG_COND_LEU: need_inv =3D true; @@ -3599,6 +3621,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) case INDEX_op_dup2_vec: return &v_v_v; case INDEX_op_not_vec: + case INDEX_op_neg_vec: case INDEX_op_dup_vec: return &v_v; case INDEX_op_ld_vec: --=20 2.17.1