From nobody Wed Nov 12 08:34:28 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1569819221; cv=none; d=zoho.com; s=zohoarc; b=lqcpPpdARlRAuPEhdRIo48Lm52IsjGyPSWFQ+5zzYPrfhKp2Ggzki2c0sfQWqLVGpR/jb3n2YGkQ4KEyYuPYih4Pw6sgz0ndZV/N0AHwjkEXzRjL6v1mZBMMYsveqUWRlXNz0ST2kC3/AEPY7wGR85WBaFs8nigt5bPIJXUKlhc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569819221; h=Content-Transfer-Encoding:Cc:Date:From:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:To:ARC-Authentication-Results; bh=MEqebdnUURZi8OjiWLC0WjWYJusnpH4ZO+sWzV+Oxx0=; b=g/3sZCxchmc/wR5paoVvqaCwCeasdGbyBPFnz2fMVJhYumI/zz4/QZ7cVo03hcrW1RA2hLFsna5CLtwPrc+zyYn/rhuu89KTVhcnvNRVZS3Z8JgzZr2U9qEgfhksjYgrQut0G2Z1aEfsNLoA85i+Kc16qmXj78eQAp66yeUQtO8= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1569819221604457.07805178995113; Sun, 29 Sep 2019 21:53:41 -0700 (PDT) Received: from localhost ([::1]:44918 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iEngk-0006zL-TR for importer@patchew.org; Mon, 30 Sep 2019 00:53:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51455) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iEnfH-0006BL-8P for qemu-devel@nongnu.org; Mon, 30 Sep 2019 00:52:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iEnfF-0000tA-5c for qemu-devel@nongnu.org; Mon, 30 Sep 2019 00:52:02 -0400 Received: from mga11.intel.com ([192.55.52.93]:55303) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iEnfE-0000oD-Uc for qemu-devel@nongnu.org; Mon, 30 Sep 2019 00:52:01 -0400 Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Sep 2019 21:51:52 -0700 Received: from a23004-02.sh.intel.com ([10.239.9.19]) by FMSMGA003.fm.intel.com with ESMTP; 29 Sep 2019 21:51:51 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,565,1559545200"; d="scan'208";a="197433734" From: qi1.zhang@intel.com To: qemu-devel@nongnu.org Subject: [PATCH] intel_iommu: split the resevred fields arrays into two ones Date: Mon, 30 Sep 2019 12:41:43 +0800 Message-Id: <20190930044143.7461-1-qi1.zhang@intel.com> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.93 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qi1.zhang@intel.com, ehabkost@redhat.com, mst@redhat.com, pbonzini@redhat.com, rth@twiddle.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: "Zhang, Qi" Signed-off-by: Zhang, Qi --- hw/i386/intel_iommu.c | 31 +++++++++++++++++-------------- 1 file changed, 17 insertions(+), 14 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index f1de8fdb75..a118efaeaf 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -910,18 +910,19 @@ static dma_addr_t vtd_get_iova_pgtbl_base(IntelIOMMUS= tate *s, =20 /* * Rsvd field masks for spte: - * Index [1] to [4] 4k pages - * Index [5] to [8] large pages + * vtd_spte_rsvd 4k pages + * vtd_spte_rsvd_large large pages */ -static uint64_t vtd_paging_entry_rsvd_field[9]; +static uint64_t vtd_spte_rsvd[5]; +static uint64_t vtd_spte_rsvd_large[5]; =20 static bool vtd_slpte_nonzero_rsvd(uint64_t slpte, uint32_t level) { if (slpte & VTD_SL_PT_PAGE_SIZE_MASK) { /* Maybe large page */ - return slpte & vtd_paging_entry_rsvd_field[level + 4]; + return slpte & vtd_spte_rsvd_large[level]; } else { - return slpte & vtd_paging_entry_rsvd_field[level]; + return slpte & vtd_spte_rsvd[level]; } } =20 @@ -3547,15 +3548,17 @@ static void vtd_init(IntelIOMMUState *s) /* * Rsvd field masks for spte */ - vtd_paging_entry_rsvd_field[0] =3D ~0ULL; - vtd_paging_entry_rsvd_field[1] =3D VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bi= ts); - vtd_paging_entry_rsvd_field[2] =3D VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bi= ts); - vtd_paging_entry_rsvd_field[3] =3D VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bi= ts); - vtd_paging_entry_rsvd_field[4] =3D VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bi= ts); - vtd_paging_entry_rsvd_field[5] =3D VTD_SPTE_LPAGE_L1_RSVD_MASK(s->aw_b= its); - vtd_paging_entry_rsvd_field[6] =3D VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_b= its); - vtd_paging_entry_rsvd_field[7] =3D VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_b= its); - vtd_paging_entry_rsvd_field[8] =3D VTD_SPTE_LPAGE_L4_RSVD_MASK(s->aw_b= its); + vtd_spte_rsvd[0] =3D ~0ULL; + vtd_spte_rsvd[1] =3D VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits); + vtd_spte_rsvd[2] =3D VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits); + vtd_spte_rsvd[3] =3D VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits); + vtd_spte_rsvd[4] =3D VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits); + + vtd_spte_rsvd_large[0] =3D ~0ULL; + vtd_spte_rsvd_large[1] =3D VTD_SPTE_LPAGE_L1_RSVD_MASK(s->aw_bits); + vtd_spte_rsvd_large[2] =3D VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits); + vtd_spte_rsvd_large[3] =3D VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits); + vtd_spte_rsvd_large[4] =3D VTD_SPTE_LPAGE_L4_RSVD_MASK(s->aw_bits); =20 if (x86_iommu_ir_supported(x86_iommu)) { s->ecap |=3D VTD_ECAP_IR | VTD_ECAP_MHMV; --=20 2.20.1