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[88.21.68.240]) by smtp.gmail.com with ESMTPSA id b186sm9918980wmd.16.2019.09.26.10.34.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Sep 2019 10:34:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GlaMMIfLZjSDDtTHA/uHOissc0A853GaqoDlAhxsiJM=; b=QmupJf/2U6S3tX/1kh4MFs5BaT311mz8YFy6GDfe48td7bhn2osy22KsyarRVS923C 8X3/iIygr3eeECtn+stZAmoPSUm8V67qnRi8JsomTI9FPiRnVQDjnsRV4FHlvyGSx9o2 M+pTAkfrdtx+ihkxpo5eFEVff+KzWz46t9NdFQJsRo+W2adA38IxhisCAvG6FV0Q1L9Z WEuR909D8JpwJaGWIGd+zAYcYpg4FbnhAyLNy8M69cMZf3Z1sRWDW5yPY541PycNqnma U2LjSk+eslIW5vBuroQIVTBKO9AVooov6G7BfVwqUMbwqDLHjW849bJkFtCtlfzsl5oy 1Vtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=GlaMMIfLZjSDDtTHA/uHOissc0A853GaqoDlAhxsiJM=; b=aQVQmNT7cGw4eHuGAhtfaWuSpRxkaUKXjcBhq4THGyhDXdS46b+JFcCqjfTMc6F6DA LXX6npwXfnqeVpm18qbdm6DEolFAL9MXS8lIfxmYyBj0Jf9cbvnbu7nEM6if0tn/bjOi 6fTYHfJFlpDXyjGmfJYeItgFBzp6os6fND/LxL1I4z7SETLA+kcrIOGC2VF2SFgyvcyg bByGaub/at3TqHAyUdwsMtgKAk3apP/W64T3Ry9u4aG+whQYzCMFOWndyXqYYZSzXolw HnbMcL2h+Gj1yeSioHn3kfGtTNvoXt9iXI67p7lJRlva6pLMcFy7hwID9pkMspG8UBEf QnAw== X-Gm-Message-State: APjAAAXfkPelNXCdsoapHbt6l4KYi1bAju2T8vTOmTTUsrwajbRPDlCU TK/4B8lGLJ3xmlEWs2Si98J3SagBFhk= X-Google-Smtp-Source: APXvYqw+fkY52vMHrG//JdryzcdZScvMMu4GxtjhI4Rnv3uQ6n1RZUgwXDegCA/wvOTM46oIhEVFQw== X-Received: by 2002:a5d:6284:: with SMTP id k4mr1834075wru.205.1569519282325; Thu, 26 Sep 2019 10:34:42 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH 04/19] hw/arm/bcm2835: Rename some definitions Date: Thu, 26 Sep 2019 19:34:12 +0200 Message-Id: <20190926173428.10713-5-f4bug@amsat.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190926173428.10713-1-f4bug@amsat.org> References: <20190926173428.10713-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.221.66 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , =?UTF-8?q?Zolt=C3=A1n=20Baldaszti?= , Laurent Bonnans , Esteban Bosse , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Andrew Baumann , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , qemu-arm@nongnu.org, Clement Deschamps , Cleber Rosa , Paolo Bonzini , Cheng Xiang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pekka Enberg , Guenter Roeck , Eduardo Habkost Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) The UART1 is part of the AUX peripheral, the PCM_CLOCK (yet unimplemented) is part of the CPRMAN. Reviewed-by: Peter Maydell Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Alistair Francis --- I dunno if this is OK to do that since the header has: * These definitions are derived from those in Raspbian Linux at * arch/arm/mach-{bcm2708,bcm2709}/include/mach/platform.h * where they carry the following notice: * * Copyright (C) 2010 Broadcom --- hw/arm/bcm2835_peripherals.c | 7 ++++--- hw/arm/bcm2836.c | 2 +- include/hw/arm/raspi_platform.h | 16 +++++++--------- 3 files changed, 12 insertions(+), 13 deletions(-) diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c index 8984e2e91f..1bd2ff41d5 100644 --- a/hw/arm/bcm2835_peripherals.c +++ b/hw/arm/bcm2835_peripherals.c @@ -165,7 +165,8 @@ static void bcm2835_peripherals_realize(DeviceState *de= v, Error **errp) sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart0), 0)); sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart0), 0, qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, - INTERRUPT_UART)); + INTERRUPT_UART0)); + /* AUX / UART1 */ qdev_prop_set_chr(DEVICE(&s->aux), "chardev", serial_hd(1)); =20 @@ -175,7 +176,7 @@ static void bcm2835_peripherals_realize(DeviceState *de= v, Error **errp) return; } =20 - memory_region_add_subregion(&s->peri_mr, UART1_OFFSET, + memory_region_add_subregion(&s->peri_mr, AUX_OFFSET, sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->aux), 0)); sysbus_connect_irq(SYS_BUS_DEVICE(&s->aux), 0, qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, @@ -268,7 +269,7 @@ static void bcm2835_peripherals_realize(DeviceState *de= v, Error **errp) return; } =20 - memory_region_add_subregion(&s->peri_mr, EMMC_OFFSET, + memory_region_add_subregion(&s->peri_mr, EMMC1_OFFSET, sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->sdhci), 0)); sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index 493a913f89..723aef6bf5 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -126,7 +126,7 @@ static void bcm2836_realize(DeviceState *dev, Error **e= rrp) =20 /* set periphbase/CBAR value for CPU-local registers */ object_property_set_int(OBJECT(&s->cpus[n]), - BCM2836_PERI_BASE + MCORE_OFFSET, + BCM2836_PERI_BASE + MSYNC_OFFSET, "reset-cbar", &err); if (err) { error_propagate(errp, err); diff --git a/include/hw/arm/raspi_platform.h b/include/hw/arm/raspi_platfor= m.h index 10083d33df..66969fac5d 100644 --- a/include/hw/arm/raspi_platform.h +++ b/include/hw/arm/raspi_platform.h @@ -25,8 +25,7 @@ #ifndef HW_ARM_RASPI_PLATFORM_H #define HW_ARM_RASPI_PLATFORM_H =20 -#define MCORE_OFFSET 0x0000 /* Fake frame buffer device - * (the multicore sync block) */ +#define MSYNC_OFFSET 0x0000 /* Multicore Sync Block */ #define IC0_OFFSET 0x2000 #define ST_OFFSET 0x3000 /* System Timer */ #define MPHI_OFFSET 0x6000 /* Message-based Parallel Host In= tf. */ @@ -37,9 +36,8 @@ #define ARMCTRL_TIMER0_1_OFFSET (ARM_OFFSET + 0x400) /* Timer 0 and 1 */ #define ARMCTRL_0_SBM_OFFSET (ARM_OFFSET + 0x800) /* User 0 (ARM) Semap= hores * Doorbells & Mailbo= xes */ -#define PM_OFFSET 0x100000 /* Power Management, Reset contro= ller - * and Watchdog registers */ -#define PCM_CLOCK_OFFSET 0x101098 +#define CPRMAN_OFFSET 0x100000 /* Power Management, Watchdog */ +#define CM_OFFSET 0x101000 /* Clock Management */ #define RNG_OFFSET 0x104000 #define GPIO_OFFSET 0x200000 #define UART0_OFFSET 0x201000 @@ -47,11 +45,11 @@ #define I2S_OFFSET 0x203000 #define SPI0_OFFSET 0x204000 #define BSC0_OFFSET 0x205000 /* BSC0 I2C/TWI */ -#define UART1_OFFSET 0x215000 -#define EMMC_OFFSET 0x300000 +#define AUX_OFFSET 0x215000 /* AUX: UART1/SPI1/SPI2 */ +#define EMMC1_OFFSET 0x300000 #define SMI_OFFSET 0x600000 #define BSC1_OFFSET 0x804000 /* BSC1 I2C/TWI */ -#define USB_OFFSET 0x980000 /* DTC_OTG USB controller */ +#define USB_OTG_OFFSET 0x980000 /* DTC_OTG USB controller */ #define DMA15_OFFSET 0xE05000 /* DMA controller, channel 15 */ =20 /* GPU interrupts */ @@ -112,7 +110,7 @@ #define INTERRUPT_SPI 54 #define INTERRUPT_I2SPCM 55 #define INTERRUPT_SDIO 56 -#define INTERRUPT_UART 57 +#define INTERRUPT_UART0 57 #define INTERRUPT_SLIMBUS 58 #define INTERRUPT_VEC 59 #define INTERRUPT_CPG 60 --=20 2.20.1