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[88.21.68.240]) by smtp.gmail.com with ESMTPSA id b186sm9918980wmd.16.2019.09.26.10.34.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Sep 2019 10:34:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=g3nQVTK9GRsWGCd+XSVezaLWTAj2OLG2kci059FNOZg=; b=Vzs5sgC75Z+MJsuTbcMwEDqv6i/qd7z5YfPlMArif9Bc+Ub35xddM4qSQwYq+UrnXd 3DnIxO7FZjFmyTgQ/Wyao5/kjQ/DqwuLeNPrm/bZN1CTdJNT6MFRbRp5sQnc7lBvO3N8 mWUpXWkgBFow+wTvMvCTf0pk86LczFWakNX4c0aOThYo2jv1R6/TgWoP7Bh+yJZ2Le1b ufn3lpxLWfD4amCfXgvZ/jwY+hMQJukbj12yQNAdNp4Shc0DEKt6wIQtvD2iRtD1Y9JT Ul8wBt+fk8SaRIqvCvOL8QTXkuuQqIDMNZtSTwfDAcOTzR4bUkuw+UBc8TMQ7wj46cEE lhdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=g3nQVTK9GRsWGCd+XSVezaLWTAj2OLG2kci059FNOZg=; b=hg56DIscyk+Qu0D8to3cmsROOEpNZjJn8t41eXNcOd6H6eheWKnuE1caH7VQT4QhWQ AqRkaFBRaDQ3nvWawc2S+o4jUzR7/yzINVfWy6xatq/+mMnIWp4oXIySsNlC+o50gQ9x 67BfLO+8XZrk6SvtlUSHEs8Mz8khZ3RkZKFpttMOhoftkAU+BAxOychFgAnd0CQKFz2I QmCC654yfvd892uev+eJkp1pfzUmoLMc8fyiGmaF+zeGXF4ramMTSv1WpeEsm4DUuH2h 9pMd7SNB0VkIstPTgPLOOeNUiNu4ym4V5BJKpooOvz7ETz8atAkgFCSr/na3riucca/I nBhQ== X-Gm-Message-State: APjAAAUqa/cZCT8E/K59ZyO6e7wR3R6QTMOT92ub2L4Aiu0wUCbfKVRb c+fEtl46CGFWbLLeEVhsmnVNm8tX9Po= X-Google-Smtp-Source: APXvYqy/ur8XJQRonW1wmDDHBychrQSja2bkKGZMfSGL7rwkC1P560x/x2mQIdTJpwgu8Wk1eMEMLw== X-Received: by 2002:a7b:c84f:: with SMTP id c15mr4148285wml.52.1569519301185; Thu, 26 Sep 2019 10:35:01 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH 13/19] hw/arm/raspi: Define various blocks base addresses Date: Thu, 26 Sep 2019 19:34:21 +0200 Message-Id: <20190926173428.10713-14-f4bug@amsat.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190926173428.10713-1-f4bug@amsat.org> References: <20190926173428.10713-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.128.67 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , =?UTF-8?q?Zolt=C3=A1n=20Baldaszti?= , Laurent Bonnans , Esteban Bosse , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Andrew Baumann , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , qemu-arm@nongnu.org, Clement Deschamps , Cleber Rosa , Paolo Bonzini , Cheng Xiang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pekka Enberg , Guenter Roeck , Eduardo Habkost Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) The Raspberry firmware is closed-source. While running it, it accesses various I/O registers. Logging these accesses as UNIMP (unimplemented) help to understand what the firmware is doing (ideally we want it able to boot a Linux kernel). Document various blocks we might use later. Adresses and names based on: https://github.com/hermanhermitage/videocoreiv/wiki/MMIO-Register-map Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alex Benn=C3=A9e --- Now the header is incorrect, should I add that in another file or update the header? * These definitions are derived from those in Raspbian Linux at * arch/arm/mach-{bcm2708,bcm2709}/include/mach/platform.h * where they carry the following notice: * * Copyright (C) 2010 Broadcom --- include/hw/arm/raspi_platform.h | 47 +++++++++++++++++++++++++++------ 1 file changed, 39 insertions(+), 8 deletions(-) diff --git a/include/hw/arm/raspi_platform.h b/include/hw/arm/raspi_platfor= m.h index 61b04a1bd4..8bcf1c7c93 100644 --- a/include/hw/arm/raspi_platform.h +++ b/include/hw/arm/raspi_platform.h @@ -26,14 +26,19 @@ #define HW_ARM_RASPI_PLATFORM_H =20 #define MSYNC_OFFSET 0x0000 /* Multicore Sync Block */ -#define IC0_OFFSET 0x2000 +#define CCPT_OFFSET 0x1000 /* Compact Camera Port 2 TX */ +#define INTE_OFFSET 0x2000 /* VC Interrupt controller */ #define ST_OFFSET 0x3000 /* System Timer */ +#define TXP_OFFSET 0x4000 +#define JPEG_OFFSET 0x5000 #define MPHI_OFFSET 0x6000 /* Message-based Parallel Host In= tf. */ #define DMA_OFFSET 0x7000 /* DMA controller, channels 0-14 = */ -#define ARM_OFFSET 0xB000 /* BCM2708 ARM control block */ +#define ARBA_OFFSET 0x9000 +#define BRDG_OFFSET 0xa000 +#define ARM_OFFSET 0xB000 /* ARM control block */ #define ARMCTRL_OFFSET (ARM_OFFSET + 0x000) #define ARMCTRL_IC_OFFSET (ARM_OFFSET + 0x200) /* Interrupt controll= er */ -#define ARMCTRL_TIMER0_1_OFFSET (ARM_OFFSET + 0x400) /* Timer 0 and 1 */ +#define ARMCTRL_TIMER0_1_OFFSET (ARM_OFFSET + 0x400) /* Timer 0 and 1 (SP8= 04) */ #define ARMCTRL_0_SBM_OFFSET (ARM_OFFSET + 0x800) /* User 0 (ARM) Semap= hores * Doorbells & Mailbo= xes */ #define CPRMAN_OFFSET 0x100000 /* Power Management, Watchdog */ @@ -42,24 +47,50 @@ #define AVS_OFFSET 0x103000 /* Audio Video Standard */ #define RNG_OFFSET 0x104000 #define GPIO_OFFSET 0x200000 -#define UART0_OFFSET 0x201000 -#define MMCI0_OFFSET 0x202000 -#define I2S_OFFSET 0x203000 -#define SPI0_OFFSET 0x204000 +#define UART0_OFFSET 0x201000 /* PL011 */ +#define MMCI0_OFFSET 0x202000 /* Legacy MMC */ +#define I2S_OFFSET 0x203000 /* PCM */ +#define SPI0_OFFSET 0x204000 /* SPI master */ #define BSC0_OFFSET 0x205000 /* BSC0 I2C/TWI */ +#define PIXV0_OFFSET 0x206000 +#define PIXV1_OFFSET 0x207000 +#define DPI_OFFSET 0x208000 +#define DSI0_OFFSET 0x209000 /* Display Serial Interface */ +#define PWM_OFFSET 0x20c000 +#define PERM_OFFSET 0x20d000 +#define TEC_OFFSET 0x20e000 #define OTP_OFFSET 0x20f000 +#define SLIM_OFFSET 0x210000 /* SLIMbus */ +#define CPG_OFFSET 0x211000 #define THERMAL_OFFSET 0x212000 -#define BSC_SL_OFFSET 0x214000 /* SPI slave */ +#define AVSP_OFFSET 0x213000 +#define BSC_SL_OFFSET 0x214000 /* SPI slave (bootrom) */ #define AUX_OFFSET 0x215000 /* AUX: UART1/SPI1/SPI2 */ #define EMMC1_OFFSET 0x300000 +#define EMMC2_OFFSET 0x340000 +#define HVS_OFFSET 0x400000 #define SMI_OFFSET 0x600000 +#define DSI1_OFFSET 0x700000 +#define UCAM_OFFSET 0x800000 +#define CMI_OFFSET 0x802000 #define BSC1_OFFSET 0x804000 /* BSC1 I2C/TWI */ #define BSC2_OFFSET 0x805000 /* BSC2 I2C/TWI */ +#define VECA_OFFSET 0x806000 +#define PIXV2_OFFSET 0x807000 +#define HDMI_OFFSET 0x808000 +#define HDCP_OFFSET 0x809000 +#define ARBR0_OFFSET 0x80a000 #define DBUS_OFFSET 0x900000 #define AVE0_OFFSET 0x910000 #define USB_OTG_OFFSET 0x980000 /* DTC_OTG USB controller */ +#define V3D_OFFSET 0xc00000 #define SDRAMC_OFFSET 0xe00000 +#define L2CC_OFFSET 0xe01000 /* Level 2 Cache controller */ +#define L1CC_OFFSET 0xe02000 /* Level 1 Cache controller */ +#define ARBR1_OFFSET 0xe04000 #define DMA15_OFFSET 0xE05000 /* DMA controller, channel 15 */ +#define DCRC_OFFSET 0xe07000 +#define AXIP_OFFSET 0xe08000 =20 /* GPU interrupts */ #define INTERRUPT_TIMER0 0 --=20 2.20.1