From nobody Sun Feb 8 20:59:50 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1569493162; cv=none; d=zoho.com; s=zohoarc; b=ABV4/JEsDvVSNRPx9SZ+N0B0PIi+KUvZ6MkOuK5jDb3ctmlfnXmgTLthRl3OV1oK8npSaPDo2dqUQD2rzqLwUwm/clpzkcSinWECsaRUdpKxLoSAiCdb5Fq24p9cqY8wTzHP86bMfajY/c6RXs7mWbq4WX2gmh5BGV13hfBAXz8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569493162; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=vtJrvz8gPeOIt/c9guAN4QRz7UlitiZO81kR/HHN1+c=; b=FxHTE3wPwOLStn/pSieXLeecCOL2Eiio0QFOjxtFU0uWntsjUfqUI0wac5RGI4b5H1MrKcl2NdsVdEohkNUO7kwxrpc8mjAE9OTHoQKhMS86ulMJ9qdQGcB5fdkvxBYp75yVNHwYvpjpxD6qLLqZG/rF3jRCZb4XHqfzoEOUiaY= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1569493162689134.49141743417772; Thu, 26 Sep 2019 03:19:22 -0700 (PDT) Received: from localhost ([::1]:33320 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iDQrg-0005uj-Td for importer@patchew.org; Thu, 26 Sep 2019 06:19:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36063) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iDQpE-0004GL-I0 for qemu-devel@nongnu.org; Thu, 26 Sep 2019 06:16:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iDQpD-0007ga-6B for qemu-devel@nongnu.org; Thu, 26 Sep 2019 06:16:40 -0400 Received: from mx1.redhat.com ([209.132.183.28]:52874) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iDQpD-0007g9-0k; Thu, 26 Sep 2019 06:16:39 -0400 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 366E3301A3AE; Thu, 26 Sep 2019 10:16:38 +0000 (UTC) Received: from t460s.redhat.com (ovpn-116-65.ams2.redhat.com [10.36.116.65]) by smtp.corp.redhat.com (Postfix) with ESMTP id 5BD2C60920; Thu, 26 Sep 2019 10:16:36 +0000 (UTC) From: David Hildenbrand To: qemu-devel@nongnu.org Subject: [PATCH v1 2/5] s390x/mmu: Implement ESOP-2 and access-exception-fetch/store-indication facility Date: Thu, 26 Sep 2019 12:16:24 +0200 Message-Id: <20190926101627.23376-3-david@redhat.com> In-Reply-To: <20190926101627.23376-1-david@redhat.com> References: <20190926101627.23376-1-david@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.41]); Thu, 26 Sep 2019 10:16:38 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Janosch Frank , David Hildenbrand , Cornelia Huck , Halil Pasic , Christian Borntraeger , qemu-s390x@nongnu.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" We already implement ESOP-1. For ESOP-2, we only have to indicate all protection exceptions properly. Due to EDAT-1, we already indicate DAT exceptions properly. We don't trigger KCP/ALCP/IEP exceptions yet. So all we have to do is set the TEID (TEC) to the right values (bit 56, 60, 61) in case of LAP. We don't have any side-effects (e.g., no guarded-storage facility), therefore, bit 64 of the TEID (TEC) is always 0. We always have to indicate whether it is a fetch or a store for all access exceptions. This is only missing for LAP exceptions. Signed-off-by: David Hildenbrand Acked-by: Thomas Huth --- target/s390x/mmu_helper.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c index 54f54137ec..8abc5d31d8 100644 --- a/target/s390x/mmu_helper.c +++ b/target/s390x/mmu_helper.c @@ -384,7 +384,9 @@ int mmu_translate(CPUS390XState *env, target_ulong vadd= r, int rw, uint64_t asc, *flags |=3D PAGE_WRITE_INV; if (is_low_address(vaddr) && rw =3D=3D MMU_DATA_STORE) { if (exc) { - trigger_access_exception(env, PGM_PROTECTION, ILEN_AUTO, 0= ); + /* LAP sets bit 56 */ + tec |=3D 0x80; + trigger_access_exception(env, PGM_PROTECTION, ilen, tec); } return -EACCES; } @@ -540,6 +542,10 @@ void s390_cpu_virt_mem_handle_exc(S390CPU *cpu, uintpt= r_t ra) int mmu_translate_real(CPUS390XState *env, target_ulong raddr, int rw, target_ulong *addr, int *flags) { + /* Code accesses have an undefined ilc, let's use 2 bytes. */ + const int ilen =3D (rw =3D=3D MMU_INST_FETCH) ? 2 : ILEN_AUTO; + uint64_t tec =3D (raddr & TARGET_PAGE_MASK) | + (rw =3D=3D MMU_DATA_STORE ? FS_WRITE : FS_READ); const bool lowprot_enabled =3D env->cregs[0] & CR0_LOWPROT; =20 *flags =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; @@ -547,7 +553,9 @@ int mmu_translate_real(CPUS390XState *env, target_ulong= raddr, int rw, /* see comment in mmu_translate() how this works */ *flags |=3D PAGE_WRITE_INV; if (is_low_address(raddr) && rw =3D=3D MMU_DATA_STORE) { - trigger_access_exception(env, PGM_PROTECTION, ILEN_AUTO, 0); + /* LAP sets bit 56 */ + tec |=3D 0x80; + trigger_access_exception(env, PGM_PROTECTION, ilen, tec); return -EACCES; } } --=20 2.21.0