From nobody Mon Feb 9 00:31:04 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1569417076; cv=none; d=zoho.com; s=zohoarc; b=mHXe6NVxFkS+abZGu36z8j4gNad/pr8QWOJ0qKG09I+ZPJ/RQHOF6ZNexOdQ27GVGPQHiLqSxldaLZ+20F7FgJl0gn4k13U7zRWX/C6Y6Z4BBqX/kflfNxqq/5CZIcusF9DNeFlq/yB/weM8dzslyBLfEagM2guRF86gkx58aaM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569417076; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=rGFZqAHLxS5DtpbxDxflIrKOX5pePzFO5Pz4Qh1iYn4=; b=lNbdzrYUMZcAIsVVK2GOHpWC2VhntX7wMul7uscFlCPTP4SwVYug2vm/rYK2eAFh+o7dXgbsRDjL2VF2R6beXOKVxSbGrv0GsPDPL8RhxSYWb8Xw69jE2JE3wlQll6SQg0DTeF5PKoSIuklCg1qwJCAfx/5G8klM4TtJtlpMEw0= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1569417076777956.5506152463664; Wed, 25 Sep 2019 06:11:16 -0700 (PDT) Received: from localhost ([::1]:49756 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iD74d-0008RS-1r for importer@patchew.org; Wed, 25 Sep 2019 09:11:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58691) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iD6mq-0006Og-Qc for qemu-devel@nongnu.org; Wed, 25 Sep 2019 08:52:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iD6mp-00044y-Np for qemu-devel@nongnu.org; Wed, 25 Sep 2019 08:52:52 -0400 Received: from mx1.redhat.com ([209.132.183.28]:46000) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iD6mp-00044Y-GK; Wed, 25 Sep 2019 08:52:51 -0400 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id B0BD530860B9; Wed, 25 Sep 2019 12:52:50 +0000 (UTC) Received: from t460s.redhat.com (ovpn-117-14.ams2.redhat.com [10.36.117.14]) by smtp.corp.redhat.com (Postfix) with ESMTP id E963E600C8; Wed, 25 Sep 2019 12:52:48 +0000 (UTC) From: David Hildenbrand To: qemu-devel@nongnu.org Subject: [PATCH v2 2/7] s390x/mmu: Move DAT protection handling out of mmu_translate_asce() Date: Wed, 25 Sep 2019 14:52:31 +0200 Message-Id: <20190925125236.4043-3-david@redhat.com> In-Reply-To: <20190925125236.4043-1-david@redhat.com> References: <20190925125236.4043-1-david@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.44]); Wed, 25 Sep 2019 12:52:50 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Janosch Frank , David Hildenbrand , Cornelia Huck , Halil Pasic , Christian Borntraeger , qemu-s390x@nongnu.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" We'll reuse the ilen and tec definitions in mmu_translate soon also for all other DAT exceptions we inject. Move it to the caller, where we can later pair it up with other protection checks, like IEP. Signed-off-by: David Hildenbrand Reviewed-by: Richard Henderson Reviewed-by: Thomas Huth --- target/s390x/mmu_helper.c | 39 ++++++++++++++++----------------------- 1 file changed, 16 insertions(+), 23 deletions(-) diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c index 6a7ad33c4d..847fb240fb 100644 --- a/target/s390x/mmu_helper.c +++ b/target/s390x/mmu_helper.c @@ -48,20 +48,6 @@ static void trigger_access_exception(CPUS390XState *env,= uint32_t type, } } =20 -static void trigger_prot_fault(CPUS390XState *env, target_ulong vaddr, - uint64_t asc, int rw, bool exc) -{ - uint64_t tec; - - tec =3D vaddr | (rw =3D=3D MMU_DATA_STORE ? FS_WRITE : FS_READ) | 4 | = asc >> 46; - - if (!exc) { - return; - } - - trigger_access_exception(env, PGM_PROTECTION, ILEN_AUTO, tec); -} - static void trigger_page_fault(CPUS390XState *env, target_ulong vaddr, uint32_t type, uint64_t asc, int rw, bool e= xc) { @@ -229,7 +215,6 @@ static int mmu_translate_asce(CPUS390XState *env, targe= t_ulong vaddr, int *flags, int rw, bool exc) { int level; - int r; =20 if (asce & ASCE_REAL_SPACE) { /* direct mapping */ @@ -277,14 +262,8 @@ static int mmu_translate_asce(CPUS390XState *env, targ= et_ulong vaddr, break; } =20 - r =3D mmu_translate_region(env, vaddr, asc, asce, level, raddr, flags,= rw, - exc); - if (!r && rw =3D=3D MMU_DATA_STORE && !(*flags & PAGE_WRITE)) { - trigger_prot_fault(env, vaddr, asc, rw, exc); - return -1; - } - - return r; + return mmu_translate_region(env, vaddr, asc, asce, level, raddr, flags= , rw, + exc); } =20 static void mmu_handle_skey(target_ulong addr, int rw, int *flags) @@ -369,6 +348,10 @@ static void mmu_handle_skey(target_ulong addr, int rw,= int *flags) int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t= asc, target_ulong *raddr, int *flags, bool exc) { + /* Code accesses have an undefined ilc, let's use 2 bytes. */ + const int ilen =3D (rw =3D=3D MMU_INST_FETCH) ? 2 : ILEN_AUTO; + uint64_t tec =3D (vaddr & TARGET_PAGE_MASK) | (asc >> 46) | + (rw =3D=3D MMU_DATA_STORE ? FS_WRITE : FS_READ); uint64_t asce; int r; =20 @@ -421,6 +404,16 @@ int mmu_translate(CPUS390XState *env, target_ulong vad= dr, int rw, uint64_t asc, return r; } =20 + /* check for DAT protection */ + if (unlikely(rw =3D=3D MMU_DATA_STORE && !(*flags & PAGE_WRITE))) { + if (exc) { + /* DAT sets bit 61 only */ + tec |=3D 0x4; + trigger_access_exception(env, PGM_PROTECTION, ilen, tec); + } + return -1; + } + nodat: /* Convert real address -> absolute address */ *raddr =3D mmu_real2abs(env, *raddr); --=20 2.21.0