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Tue, 24 Sep 2019 14:01:09 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v3 03/33] target/alpha: Fix SWCR_TRAP_ENABLE_MASK Date: Tue, 24 Sep 2019 22:00:36 +0100 Message-Id: <20190924210106.27117-4-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190924210106.27117-1-alex.bennee@linaro.org> References: <20190924210106.27117-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , jsnow@redhat.com, f4bug@amsat.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Richard Henderson The CONFIG_USER_ONLY adjustment blindly mashed the swcr exception enable bits into the fpcr exception disable bits. However, fpcr_exc_enable has already converted the exception disable bits into the exception status bits in order to make it easier to mask status bits at runtime. Instead, merge the swcr enable bits with the fpcr before we convert to status bits. Signed-off-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e Message-Id: <20190921043256.4575-4-richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/alpha/helper.c | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/target/alpha/helper.c b/target/alpha/helper.c index 10602fb3394..e21c488aa32 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -46,34 +46,39 @@ void cpu_alpha_store_fpcr(CPUAlphaState *env, uint64_t = val) uint32_t fpcr =3D val >> 32; uint32_t t =3D 0; =20 + /* Record the raw value before adjusting for linux-user. */ + env->fpcr =3D fpcr; + +#ifdef CONFIG_USER_ONLY + /* + * Override some of these bits with the contents of ENV->SWCR. + * In system mode, some of these would trap to the kernel, at + * which point the kernel's handler would emulate and apply + * the software exception mask. + */ + uint32_t soft_fpcr =3D alpha_ieee_swcr_to_fpcr(env->swcr) >> 32; + fpcr |=3D soft_fpcr & FPCR_STATUS_MASK; +#endif + t |=3D CONVERT_BIT(fpcr, FPCR_INED, FPCR_INE); t |=3D CONVERT_BIT(fpcr, FPCR_UNFD, FPCR_UNF); t |=3D CONVERT_BIT(fpcr, FPCR_OVFD, FPCR_OVF); t |=3D CONVERT_BIT(fpcr, FPCR_DZED, FPCR_DZE); t |=3D CONVERT_BIT(fpcr, FPCR_INVD, FPCR_INV); =20 - env->fpcr =3D fpcr; env->fpcr_exc_enable =3D ~t & FPCR_STATUS_MASK; =20 env->fpcr_dyn_round =3D rm_map[(fpcr & FPCR_DYN_MASK) >> FPCR_DYN_SHIF= T]; =20 env->fpcr_flush_to_zero =3D (fpcr & FPCR_UNFD) && (fpcr & FPCR_UNDZ); env->fp_status.flush_inputs_to_zero =3D (fpcr & FPCR_DNZ) !=3D 0; - #ifdef CONFIG_USER_ONLY - /* - * Override some of these bits with the contents of ENV->SWCR. - * In system mode, some of these would trap to the kernel, at - * which point the kernel's handler would emulate and apply - * the software exception mask. - */ if (env->swcr & SWCR_MAP_DMZ) { env->fp_status.flush_inputs_to_zero =3D 1; } if (env->swcr & SWCR_MAP_UMZ) { env->fpcr_flush_to_zero =3D 1; } - env->fpcr_exc_enable &=3D ~(alpha_ieee_swcr_to_fpcr(env->swcr) >> 32); #endif } =20 --=20 2.20.1