From nobody Mon Feb 9 16:12:53 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1569324978; cv=none; d=zoho.com; s=zohoarc; b=BzuWLkKR31LIuObIeAbtN1NWsQpeSMbWAI9SdJkNvj7jJKvdV55aP1yztw++knW6UJx5t3/hBWlWGA7gfdIFdwM6w/2HxlrltnP+d9CYiYNmKyoVVfzFoitW3WlrPWVfzAsUuTLEyhcI3kre2eZG35EJraxOvbbqn5ucW120Q+I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569324978; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=dM7N7Go8AsjJONhUsJSPR9SwmS2F4xhh4cqQ7xnfvZA=; b=Jab43zty3Kz3MNqPClbvy+CJjkx26qCDFOJHuxg8t71wEiyCxZS5oQ0TdKDzFz8ou7NaRddbLmJk29Sq2zfX7CiK1phjgiMO+bipLeiPtsqVZpwZ8cN/mj0BzOgWycMYjv2+MqpCdZt0mC0i/RZOYv9kgPvm4uuWb8SNK66Jzdo= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1569324978636362.24515144358213; Tue, 24 Sep 2019 04:36:18 -0700 (PDT) Received: from localhost ([::1]:44268 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iCj72-0005Ee-4R for importer@patchew.org; Tue, 24 Sep 2019 07:36:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42364) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iCj2V-0002Ws-JD for qemu-devel@nongnu.org; Tue, 24 Sep 2019 07:31:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iCj2T-0005Mj-Rm for qemu-devel@nongnu.org; Tue, 24 Sep 2019 07:31:27 -0400 Received: from mx1.redhat.com ([209.132.183.28]:45752) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iCj2Q-0005KC-Am; Tue, 24 Sep 2019 07:31:22 -0400 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 8156310CC1F7; Tue, 24 Sep 2019 11:31:21 +0000 (UTC) Received: from kamzik.brq.redhat.com (unknown [10.43.2.160]) by smtp.corp.redhat.com (Postfix) with ESMTP id 65C0861F21; Tue, 24 Sep 2019 11:31:19 +0000 (UTC) From: Andrew Jones To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Subject: [PATCH v4 3/9] target/arm: Allow SVE to be disabled via a CPU property Date: Tue, 24 Sep 2019 13:30:59 +0200 Message-Id: <20190924113105.19076-4-drjones@redhat.com> In-Reply-To: <20190924113105.19076-1-drjones@redhat.com> References: <20190924113105.19076-1-drjones@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.6.2 (mx1.redhat.com [10.5.110.65]); Tue, 24 Sep 2019 11:31:21 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, richard.henderson@linaro.org, armbru@redhat.com, eric.auger@redhat.com, imammedo@redhat.com, alex.bennee@linaro.org, Dave.Martin@arm.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Since 97a28b0eeac14 ("target/arm: Allow VFP and Neon to be disabled via a CPU property") we can disable the 'max' cpu model's VFP and neon features, but there's no way to disable SVE. Add the 'sve=3Don|off' property to give it that flexibility. We also rename cpu_max_get/set_sve_vq to cpu_max_get/set_sve_max_vq in order for them to follow the typical *_get/set_ pattern. Signed-off-by: Andrew Jones Reviewed-by: Richard Henderson Reviewed-by: Eric Auger --- target/arm/cpu.c | 3 ++- target/arm/cpu64.c | 42 ++++++++++++++++++++++++++++++++++------ target/arm/monitor.c | 2 +- tests/arm-cpu-features.c | 1 + 4 files changed, 40 insertions(+), 8 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 2399c144718d..73be2ebfdd39 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -200,7 +200,8 @@ static void arm_cpu_reset(CPUState *s) env->cp15.cpacr_el1 =3D deposit64(env->cp15.cpacr_el1, 16, 2, 3); env->cp15.cptr_el[3] |=3D CPTR_EZ; /* with maximum vector length */ - env->vfp.zcr_el[1] =3D cpu->sve_max_vq - 1; + env->vfp.zcr_el[1] =3D cpu_isar_feature(aa64_sve, cpu) ? + cpu->sve_max_vq - 1 : 0; env->vfp.zcr_el[2] =3D env->vfp.zcr_el[1]; env->vfp.zcr_el[3] =3D env->vfp.zcr_el[1]; /* diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index d7f5bf610a7d..8cdb0c79fa7a 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -256,15 +256,15 @@ static void aarch64_a72_initfn(Object *obj) define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); } =20 -static void cpu_max_get_sve_vq(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) +static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *na= me, + void *opaque, Error **errp) { ARMCPU *cpu =3D ARM_CPU(obj); visit_type_uint32(v, name, &cpu->sve_max_vq, errp); } =20 -static void cpu_max_set_sve_vq(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) +static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *na= me, + void *opaque, Error **errp) { ARMCPU *cpu =3D ARM_CPU(obj); Error *err =3D NULL; @@ -279,6 +279,34 @@ static void cpu_max_set_sve_vq(Object *obj, Visitor *v= , const char *name, error_propagate(errp, err); } =20 +static void cpu_arm_get_sve(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + bool value =3D cpu_isar_feature(aa64_sve, cpu); + + visit_type_bool(v, name, &value, errp); +} + +static void cpu_arm_set_sve(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + Error *err =3D NULL; + bool value; + uint64_t t; + + visit_type_bool(v, name, &value, &err); + if (err) { + error_propagate(errp, err); + return; + } + + t =3D cpu->isar.id_aa64pfr0; + t =3D FIELD_DP64(t, ID_AA64PFR0, SVE, value); + cpu->isar.id_aa64pfr0 =3D t; +} + /* -cpu max: if KVM is enabled, like -cpu host (best possible with this ho= st); * otherwise, a CPU with as many features enabled as our emulation support= s. * The version of '-cpu max' for qemu-system-arm is defined in cpu.c; @@ -391,8 +419,10 @@ static void aarch64_max_initfn(Object *obj) #endif =20 cpu->sve_max_vq =3D ARM_MAX_VQ; - object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_v= q, - cpu_max_set_sve_vq, NULL, NULL, &error_fatal); + object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_m= ax_vq, + cpu_max_set_sve_max_vq, NULL, NULL, &error_fat= al); + object_property_add(obj, "sve", "bool", cpu_arm_get_sve, + cpu_arm_set_sve, NULL, NULL, &error_fatal); } } =20 diff --git a/target/arm/monitor.c b/target/arm/monitor.c index edca8aa885f0..4fddb6c252a3 100644 --- a/target/arm/monitor.c +++ b/target/arm/monitor.c @@ -97,7 +97,7 @@ GICCapabilityList *qmp_query_gic_capabilities(Error **err= p) * then the order that considers those dependencies must be used. */ static const char *cpu_model_advertised_features[] =3D { - "aarch64", "pmu", + "aarch64", "pmu", "sve", NULL }; =20 diff --git a/tests/arm-cpu-features.c b/tests/arm-cpu-features.c index 198ff6d6b495..202bc0e3e823 100644 --- a/tests/arm-cpu-features.c +++ b/tests/arm-cpu-features.c @@ -179,6 +179,7 @@ static void test_query_cpu_model_expansion(const void *= data) =20 if (g_str_equal(qtest_get_arch(), "aarch64")) { assert_has_feature(qts, "max", "aarch64"); + assert_has_feature(qts, "max", "sve"); assert_has_feature(qts, "cortex-a57", "pmu"); assert_has_feature(qts, "cortex-a57", "aarch64"); =20 --=20 2.20.1