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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id z4sm6452921pjt.17.2019.09.21.20.55.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 21 Sep 2019 20:55:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+uIocOn9VX/i7GnqHaWrqX+b4SaiUHijmC0FIzPROHE=; b=XLB7paZW8USoqtq1oG48bOcStD6Xn1S+IBwEQBm/3Bizq3L2PyopVXKxwM83lauig9 sE53dKobdVWE/PzTTzYOe9G1Yd72SzozRNavwyBYucz6aR8AlHOArXVRg7oSMjqb3hYa kS0QIwCHlAsiFpjp/YoJO9dyDbmOTZQcDOj/z3y+7y5/VhX/5x+q7n7s0dkxp+rIZD0X pk1b/quzQfnsgRVJKDHU5JnOE/rRxYneK7bOcH9uYZd6IaR1uqu2+Vl5JmvFkCdInF0e 8eVQo9Ot0S6z6BEvcBDt+vjr29PY5piA3sAamDFNeaYyet+wjevGU73oZvSsjb7ZkvOh 5Rxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+uIocOn9VX/i7GnqHaWrqX+b4SaiUHijmC0FIzPROHE=; b=pLgBmSrZR3HiyyVotfJfvHBvWK10mz6OD/nK5MC0bbiaTSouOBAGkyoH2qxl6YMj+o ib3/Ub8/wYfNH2K8Z2PGCWJTgzyP7bcFOwe91jLCivHcdZb8x3vSzoJn8sRe8jGIVd2r SfqdDpthkUlKufOqLLp3CfKoljyMepFKllZ5Hs8Ed9TyN/yqm0ooWllHCQUvh1zGdQ6q U4Q1nGniQfC6Ww9qw7GlojPuy3cI3j8rVQ1zDJG9ul6oVTTRi0ArEzRhSZ8Php2qRjU6 9sB0S30X1b9Yj9NgUxK9cbqxJDiq46jWYTwF5JjVbcrl4fUE6fCN4JuRTOqBbJ2MzPMS 5dig== X-Gm-Message-State: APjAAAXISB/Fi835aBYx8mkZFSORQrewLZ3661RNvAYc6gJ7Vb8tawX6 RBsgnBCAuzSe24elmONtfJVb2MAJJvQ= X-Google-Smtp-Source: APXvYqz05/gQGw7gkik7VN++tyucfLshev+aZ8O5g2aakphzfVDBoPHhhbaA4DXeCXqEPJcGdV6LAg== X-Received: by 2002:a17:90a:8d84:: with SMTP id d4mr13473928pjo.139.1569124515935; Sat, 21 Sep 2019 20:55:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 12/20] cputlb: Move ROM handling from I/O path to TLB path Date: Sat, 21 Sep 2019 20:54:50 -0700 Message-Id: <20190922035458.14879-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190922035458.14879-1-richard.henderson@linaro.org> References: <20190922035458.14879-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, alex.bennee@linaro.org, stefanha@redhat.com, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" It does not require going through the whole I/O path in order to discard a write. Signed-off-by: Richard Henderson Reviewed-by: David Hildenbrand --- include/exec/cpu-all.h | 5 ++++- include/exec/cpu-common.h | 1 - accel/tcg/cputlb.c | 35 +++++++++++++++++++-------------- exec.c | 41 +-------------------------------------- 4 files changed, 25 insertions(+), 57 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 1ebd1b59ab..9f0b17802e 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -348,12 +348,15 @@ CPUArchState *cpu_copy(CPUArchState *env); #define TLB_WATCHPOINT (1 << (TARGET_PAGE_BITS_MIN - 4)) /* Set if TLB entry requires byte swap. */ #define TLB_BSWAP (1 << (TARGET_PAGE_BITS_MIN - 5)) +/* Set if TLB entry writes ignored. */ +#define TLB_ROM (1 << (TARGET_PAGE_BITS_MIN - 6)) =20 /* Use this mask to check interception with an alignment mask * in a TCG backend. */ #define TLB_FLAGS_MASK \ - (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO | TLB_WATCHPOINT | TLB_BSW= AP) + (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO \ + | TLB_WATCHPOINT | TLB_BSWAP | TLB_ROM) =20 /** * tlb_hit_page: return true if page aligned @addr is a hit against the diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index f7dbe75fbc..1c0e03ddc2 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -100,7 +100,6 @@ void qemu_flush_coalesced_mmio_buffer(void); =20 void cpu_flush_icache_range(hwaddr start, hwaddr len); =20 -extern struct MemoryRegion io_mem_rom; extern struct MemoryRegion io_mem_notdirty; =20 typedef int (RAMBlockIterFunc)(RAMBlock *rb, void *opaque); diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index cb603917a2..7ab523d7ec 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -577,7 +577,7 @@ static void tlb_reset_dirty_range_locked(CPUTLBEntry *t= lb_entry, { uintptr_t addr =3D tlb_entry->addr_write; =20 - if ((addr & (TLB_INVALID_MASK | TLB_MMIO | TLB_NOTDIRTY)) =3D=3D 0) { + if ((addr & (TLB_INVALID_MASK | TLB_MMIO | TLB_ROM | TLB_NOTDIRTY)) = =3D=3D 0) { addr &=3D TARGET_PAGE_MASK; addr +=3D tlb_entry->addend; if ((addr - start) < length) { @@ -745,7 +745,6 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulon= g vaddr, address |=3D TLB_MMIO; addend =3D 0; } else { - /* TLB_MMIO for rom/romd handled below */ addend =3D (uintptr_t)memory_region_get_ram_ptr(section->mr) + xla= t; } =20 @@ -822,16 +821,17 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ul= ong vaddr, =20 tn.addr_write =3D -1; if (prot & PAGE_WRITE) { - if ((memory_region_is_ram(section->mr) && section->readonly) - || memory_region_is_romd(section->mr)) { - /* Write access calls the I/O callback. */ - tn.addr_write =3D address | TLB_MMIO; - } else if (memory_region_is_ram(section->mr) - && cpu_physical_memory_is_clean( - memory_region_get_ram_addr(section->mr) + xlat)) { - tn.addr_write =3D address | TLB_NOTDIRTY; - } else { - tn.addr_write =3D address; + tn.addr_write =3D address; + if (memory_region_is_romd(section->mr)) { + /* Use the MMIO path so that the device can switch states. */ + tn.addr_write |=3D TLB_MMIO; + } else if (memory_region_is_ram(section->mr)) { + if (section->readonly) { + tn.addr_write |=3D TLB_ROM; + } else if (cpu_physical_memory_is_clean( + memory_region_get_ram_addr(section->mr) + xlat)) { + tn.addr_write |=3D TLB_NOTDIRTY; + } } if (prot & PAGE_WRITE_INV) { tn.addr_write |=3D TLB_INVALID_MASK; @@ -904,7 +904,7 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEnt= ry *iotlbentry, mr =3D section->mr; mr_offset =3D (iotlbentry->addr & TARGET_PAGE_MASK) + addr; cpu->mem_io_pc =3D retaddr; - if (mr !=3D &io_mem_rom && mr !=3D &io_mem_notdirty && !cpu->can_do_io= ) { + if (mr !=3D &io_mem_notdirty && !cpu->can_do_io) { cpu_io_recompile(cpu, retaddr); } =20 @@ -945,7 +945,7 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry = *iotlbentry, section =3D iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs); mr =3D section->mr; mr_offset =3D (iotlbentry->addr & TARGET_PAGE_MASK) + addr; - if (mr !=3D &io_mem_rom && mr !=3D &io_mem_notdirty && !cpu->can_do_io= ) { + if (mr !=3D &io_mem_notdirty && !cpu->can_do_io) { cpu_io_recompile(cpu, retaddr); } cpu->mem_io_vaddr =3D addr; @@ -1125,7 +1125,7 @@ void *probe_access(CPUArchState *env, target_ulong ad= dr, int size, } =20 /* Reject I/O access, or other required slow-path. */ - if (tlb_addr & (TLB_NOTDIRTY | TLB_MMIO | TLB_BSWAP)) { + if (tlb_addr & (TLB_NOTDIRTY | TLB_MMIO | TLB_BSWAP | TLB_ROM)) { return NULL; } =20 @@ -1612,6 +1612,11 @@ store_helper(CPUArchState *env, target_ulong addr, u= int64_t val, return; } =20 + /* Ignore writes to ROM. */ + if (unlikely(tlb_addr & TLB_ROM)) { + return; + } + haddr =3D (void *)((uintptr_t)addr + entry->addend); =20 if (unlikely(tlb_addr & TLB_BSWAP)) { diff --git a/exec.c b/exec.c index 7ce0515635..e21e068535 100644 --- a/exec.c +++ b/exec.c @@ -88,7 +88,7 @@ static MemoryRegion *system_io; AddressSpace address_space_io; AddressSpace address_space_memory; =20 -MemoryRegion io_mem_rom, io_mem_notdirty; +MemoryRegion io_mem_notdirty; static MemoryRegion io_mem_unassigned; #endif =20 @@ -158,7 +158,6 @@ typedef struct subpage_t { =20 #define PHYS_SECTION_UNASSIGNED 0 #define PHYS_SECTION_NOTDIRTY 1 -#define PHYS_SECTION_ROM 2 =20 static void io_mem_init(void); static void memory_map_init(void); @@ -1441,8 +1440,6 @@ hwaddr memory_region_section_get_iotlb(CPUState *cpu, iotlb =3D memory_region_get_ram_addr(section->mr) + xlat; if (!section->readonly) { iotlb |=3D PHYS_SECTION_NOTDIRTY; - } else { - iotlb |=3D PHYS_SECTION_ROM; } } else { AddressSpaceDispatch *d; @@ -2968,38 +2965,6 @@ static uint16_t dummy_section(PhysPageMap *map, Flat= View *fv, MemoryRegion *mr) return phys_section_add(map, §ion); } =20 -static void readonly_mem_write(void *opaque, hwaddr addr, - uint64_t val, unsigned size) -{ - /* Ignore any write to ROM. */ -} - -static bool readonly_mem_accepts(void *opaque, hwaddr addr, - unsigned size, bool is_write, - MemTxAttrs attrs) -{ - return is_write; -} - -/* This will only be used for writes, because reads are special cased - * to directly access the underlying host ram. - */ -static const MemoryRegionOps readonly_mem_ops =3D { - .write =3D readonly_mem_write, - .valid.accepts =3D readonly_mem_accepts, - .endianness =3D DEVICE_NATIVE_ENDIAN, - .valid =3D { - .min_access_size =3D 1, - .max_access_size =3D 8, - .unaligned =3D false, - }, - .impl =3D { - .min_access_size =3D 1, - .max_access_size =3D 8, - .unaligned =3D false, - }, -}; - MemoryRegionSection *iotlb_to_section(CPUState *cpu, hwaddr index, MemTxAttrs attrs) { @@ -3013,8 +2978,6 @@ MemoryRegionSection *iotlb_to_section(CPUState *cpu, =20 static void io_mem_init(void) { - memory_region_init_io(&io_mem_rom, NULL, &readonly_mem_ops, - NULL, NULL, UINT64_MAX); memory_region_init_io(&io_mem_unassigned, NULL, &unassigned_mem_ops, N= ULL, NULL, UINT64_MAX); =20 @@ -3035,8 +2998,6 @@ AddressSpaceDispatch *address_space_dispatch_new(Flat= View *fv) assert(n =3D=3D PHYS_SECTION_UNASSIGNED); n =3D dummy_section(&d->map, fv, &io_mem_notdirty); assert(n =3D=3D PHYS_SECTION_NOTDIRTY); - n =3D dummy_section(&d->map, fv, &io_mem_rom); - assert(n =3D=3D PHYS_SECTION_ROM); =20 d->phys_map =3D (PhysPageEntry) { .ptr =3D PHYS_MAP_NODE_NIL, .skip = =3D 1 }; =20 --=20 2.17.1