From nobody Mon Feb 9 15:08:47 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1569078487; cv=none; d=zoho.com; s=zohoarc; b=SkH5T49rbQ7rSsr9jR2uG9xf4UZrBydR5sExiWPAIC+kUgK0VT4P8PeXiQQ8Vet87SqQa1EXJw5yhnfeJyz1clbK/BboggSPKAlpAnq8M03JMM++dhvuk+vGKBQQs7U3tgILmlNhfhBfwu2+hMkgA9XdnN29zXxE7vZVRMtzw3s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569078487; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=oiHNvJR7X1kEypcvSBBUBnrFEMIbCkZesi3eZOAI9VY=; b=oaibI00/O7dZQMtzmTScjKn1TPx6zh38JqKYIYHQweIM8jins1m4abs7tHlepAppMX0a/fYf49b6zK6UC8EHP4BYNoYhWZegvOQIFxITFmTptVwJh53/cMYJOzhDTv5g+KmUwjDOG4ExiZ2q1TAiN710zTr13yM5axo5plquWXw= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 15690784873241000.2502443022443; Sat, 21 Sep 2019 08:08:07 -0700 (PDT) Received: from localhost ([::1]:42320 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iBgzU-0007wd-57 for importer@patchew.org; Sat, 21 Sep 2019 11:08:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39843) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iBgwC-0004PT-J4 for qemu-devel@nongnu.org; Sat, 21 Sep 2019 11:04:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iBgwA-0003FV-KZ for qemu-devel@nongnu.org; Sat, 21 Sep 2019 11:04:40 -0400 Received: from mx1.redhat.com ([209.132.183.28]:40500) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iBgw6-0003Du-4H; Sat, 21 Sep 2019 11:04:34 -0400 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 6C4D03082B45; Sat, 21 Sep 2019 15:04:33 +0000 (UTC) Received: from thuth.com (ovpn-116-27.ams2.redhat.com [10.36.116.27]) by smtp.corp.redhat.com (Postfix) with ESMTP id F188560920; Sat, 21 Sep 2019 15:04:31 +0000 (UTC) From: Thomas Huth To: qemu-devel@nongnu.org, Peter Maydell Subject: [PATCH 3/4] hw/arm: Move armv7m_nvic.c to hw/arm/ and always enable it for arm builds Date: Sat, 21 Sep 2019 17:04:19 +0200 Message-Id: <20190921150420.30743-4-thuth@redhat.com> In-Reply-To: <20190921150420.30743-1-thuth@redhat.com> References: <20190921150420.30743-1-thuth@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.45]); Sat, 21 Sep 2019 15:04:33 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" qemu-system-arm/-aarch64 currently can't be built without setting the switch CONFIG_ARM_V7M=3Dy - which we currently always do in the config file default-configs/arm-softmmu.mak. This is because the code in target/arm/ calls many functions from this armv7m_nvic.c, and thus linking fails without this file. So armv7m_nvic.c should not be under the CONFIG_ARM_V7M switch, but always compiled for arm builds. Since we can not simply do this in hw/intc/ (with "obj-y +=3D ..." it would get compiled for all other architectures, too), let's move the file to hw/arm/ instead and always enable it there. Signed-off-by: Thomas Huth --- hw/arm/Makefile.objs | 2 ++ hw/{intc =3D> arm}/armv7m_nvic.c | 0 hw/arm/trace-events | 17 +++++++++++++++++ hw/intc/Makefile.objs | 1 - hw/intc/trace-events | 17 ----------------- 5 files changed, 19 insertions(+), 18 deletions(-) rename hw/{intc =3D> arm}/armv7m_nvic.c (100%) diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs index 43ce8d5b19..3c94d383a0 100644 --- a/hw/arm/Makefile.objs +++ b/hw/arm/Makefile.objs @@ -27,6 +27,8 @@ obj-$(CONFIG_VEXPRESS) +=3D vexpress.o obj-$(CONFIG_ZYNQ) +=3D xilinx_zynq.o obj-$(CONFIG_SABRELITE) +=3D sabrelite.o =20 +# Note: armv7m_nvic.o is currently always required for linking +obj-y +=3D armv7m_nvic.o obj-$(CONFIG_ARM_V7M) +=3D armv7m.o obj-$(CONFIG_EXYNOS4) +=3D exynos4210.o obj-$(CONFIG_PXA2XX) +=3D pxa2xx.o pxa2xx_gpio.o pxa2xx_pic.o diff --git a/hw/intc/armv7m_nvic.c b/hw/arm/armv7m_nvic.c similarity index 100% rename from hw/intc/armv7m_nvic.c rename to hw/arm/armv7m_nvic.c diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 0acedcedc6..3068202a4c 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -1,5 +1,22 @@ # See docs/devel/tracing.txt for syntax documentation. =20 +# armv7m_nvic.c +nvic_recompute_state(int vectpending, int vectpending_prio, int exception_= prio) "NVIC state recomputed: vectpending %d vectpending_prio %d exception_= prio %d" +nvic_recompute_state_secure(int vectpending, bool vectpending_is_s_banked,= int vectpending_prio, int exception_prio) "NVIC state recomputed: vectpend= ing %d is_s_banked %d vectpending_prio %d exception_prio %d" +nvic_set_prio(int irq, bool secure, uint8_t prio) "NVIC set irq %d secure-= bank %d priority %d" +nvic_irq_update(int vectpending, int pendprio, int exception_prio, int lev= el) "NVIC vectpending %d pending prio %d exception_prio %d: setting irq lin= e to %d" +nvic_escalate_prio(int irq, int irqprio, int runprio) "NVIC escalating irq= %d to HardFault: insufficient priority %d >=3D %d" +nvic_escalate_disabled(int irq) "NVIC escalating irq %d to HardFault: disa= bled" +nvic_set_pending(int irq, bool secure, bool targets_secure, bool derived, = int en, int prio) "NVIC set pending irq %d secure-bank %d targets_secure %d= derived %d (enabled: %d priority %d)" +nvic_clear_pending(int irq, bool secure, int en, int prio) "NVIC clear pen= ding irq %d secure-bank %d (enabled: %d priority %d)" +nvic_acknowledge_irq(int irq, int prio) "NVIC acknowledge IRQ: %d now acti= ve (prio %d)" +nvic_get_pending_irq_info(int irq, bool secure) "NVIC next IRQ %d: targets= _secure: %d" +nvic_complete_irq(int irq, bool secure) "NVIC complete IRQ %d (secure %d)" +nvic_set_irq_level(int irq, int level) "NVIC external irq %d level set to = %d" +nvic_set_nmi_level(int level) "NVIC external NMI level set to %d" +nvic_sysreg_read(uint64_t addr, uint32_t value, unsigned size) "NVIC sysre= g read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u" +nvic_sysreg_write(uint64_t addr, uint32_t value, unsigned size) "NVIC sysr= eg write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u" + # virt-acpi-build.c virt_acpi_setup(void) "No fw cfg or ACPI disabled. Bailing out." =20 diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs index f726d87532..2d981abb4e 100644 --- a/hw/intc/Makefile.objs +++ b/hw/intc/Makefile.objs @@ -26,7 +26,6 @@ obj-$(CONFIG_APIC) +=3D apic.o apic_common.o obj-$(CONFIG_ARM_GIC_KVM) +=3D arm_gic_kvm.o obj-$(call land,$(CONFIG_ARM_GIC_KVM),$(TARGET_AARCH64)) +=3D arm_gicv3_kv= m.o obj-$(call land,$(CONFIG_ARM_GIC_KVM),$(TARGET_AARCH64)) +=3D arm_gicv3_it= s_kvm.o -obj-$(CONFIG_ARM_V7M) +=3D armv7m_nvic.o obj-$(CONFIG_EXYNOS4) +=3D exynos4210_gic.o exynos4210_combiner.o obj-$(CONFIG_GRLIB) +=3D grlib_irqmp.o obj-$(CONFIG_IOAPIC) +=3D ioapic.o diff --git a/hw/intc/trace-events b/hw/intc/trace-events index 90c9d07c1a..09a7fedee8 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -179,23 +179,6 @@ gicv3_redist_badwrite(uint32_t cpu, uint64_t offset, u= int64_t data, unsigned siz gicv3_redist_set_irq(uint32_t cpu, int irq, int level) "GICv3 redistributo= r 0x%x interrupt %d level changed to %d" gicv3_redist_send_sgi(uint32_t cpu, int irq) "GICv3 redistributor 0x%x pen= ding SGI %d" =20 -# armv7m_nvic.c -nvic_recompute_state(int vectpending, int vectpending_prio, int exception_= prio) "NVIC state recomputed: vectpending %d vectpending_prio %d exception_= prio %d" -nvic_recompute_state_secure(int vectpending, bool vectpending_is_s_banked,= int vectpending_prio, int exception_prio) "NVIC state recomputed: vectpend= ing %d is_s_banked %d vectpending_prio %d exception_prio %d" -nvic_set_prio(int irq, bool secure, uint8_t prio) "NVIC set irq %d secure-= bank %d priority %d" -nvic_irq_update(int vectpending, int pendprio, int exception_prio, int lev= el) "NVIC vectpending %d pending prio %d exception_prio %d: setting irq lin= e to %d" -nvic_escalate_prio(int irq, int irqprio, int runprio) "NVIC escalating irq= %d to HardFault: insufficient priority %d >=3D %d" -nvic_escalate_disabled(int irq) "NVIC escalating irq %d to HardFault: disa= bled" -nvic_set_pending(int irq, bool secure, bool targets_secure, bool derived, = int en, int prio) "NVIC set pending irq %d secure-bank %d targets_secure %d= derived %d (enabled: %d priority %d)" -nvic_clear_pending(int irq, bool secure, int en, int prio) "NVIC clear pen= ding irq %d secure-bank %d (enabled: %d priority %d)" -nvic_acknowledge_irq(int irq, int prio) "NVIC acknowledge IRQ: %d now acti= ve (prio %d)" -nvic_get_pending_irq_info(int irq, bool secure) "NVIC next IRQ %d: targets= _secure: %d" -nvic_complete_irq(int irq, bool secure) "NVIC complete IRQ %d (secure %d)" -nvic_set_irq_level(int irq, int level) "NVIC external irq %d level set to = %d" -nvic_set_nmi_level(int level) "NVIC external NMI level set to %d" -nvic_sysreg_read(uint64_t addr, uint32_t value, unsigned size) "NVIC sysre= g read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u" -nvic_sysreg_write(uint64_t addr, uint32_t value, unsigned size) "NVIC sysr= eg write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u" - # heathrow_pic.c heathrow_write(uint64_t addr, unsigned int n, uint64_t value) "0x%"PRIx64"= %u: 0x%"PRIx64 heathrow_read(uint64_t addr, unsigned int n, uint64_t value) "0x%"PRIx64" = %u: 0x%"PRIx64 --=20 2.18.1