From nobody Mon Feb 9 00:01:34 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1569078584; cv=none; d=zoho.com; s=zohoarc; b=obncoiK00dNXOFy5AhZntGqMCSLm/26vpZUlabc4kQo0QGD4TiUweLlFnR4/aBWIcKU0dMXRsxOQ8KNjI7j+EeCJSnGCONQzDqdDNMLVt8Jq+FJsHv/OiVM9+T9eU/N5K4fogoeYrzdjWGJ9TmuOZfQCOIrWLBfW7MX3xhcep4o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569078584; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=Oyu+O+KVcY9QsH00NI/rn/ZSP5IEfDZgn4HAWyGugfc=; b=aCUA43OtBL06MA+YkVYCXvIwswl/AIgahe5wnF+Jkq+K9ZM/s/QFLnioT55iALfzb5nQ5DLpFZmz9k8fOQwoktsWRH85rM1vqqy3Axpb5Gbtppmuj4Aiqo+zHkEhWWujq7Rwt3whTSATr5KhAwqFFwTCTMY2hQlabQ+h2LHh6is= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1569078584364867.2814592849462; Sat, 21 Sep 2019 08:09:44 -0700 (PDT) Received: from localhost ([::1]:42356 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iBh14-0001KX-V7 for importer@patchew.org; Sat, 21 Sep 2019 11:09:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39831) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iBgwB-0004PM-D5 for qemu-devel@nongnu.org; Sat, 21 Sep 2019 11:04:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iBgw8-0003Ep-H9 for qemu-devel@nongnu.org; Sat, 21 Sep 2019 11:04:38 -0400 Received: from mx1.redhat.com ([209.132.183.28]:48922) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iBgw4-0003DL-Bj; Sat, 21 Sep 2019 11:04:32 -0400 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 93FAE8980FA; Sat, 21 Sep 2019 15:04:31 +0000 (UTC) Received: from thuth.com (ovpn-116-27.ams2.redhat.com [10.36.116.27]) by smtp.corp.redhat.com (Postfix) with ESMTP id E4930608A5; Sat, 21 Sep 2019 15:04:29 +0000 (UTC) From: Thomas Huth To: qemu-devel@nongnu.org, Peter Maydell Subject: [PATCH 2/4] target/arm: Move cortex-m related functions to new file v7m.c Date: Sat, 21 Sep 2019 17:04:18 +0200 Message-Id: <20190921150420.30743-3-thuth@redhat.com> In-Reply-To: <20190921150420.30743-1-thuth@redhat.com> References: <20190921150420.30743-1-thuth@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.6.2 (mx1.redhat.com [10.5.110.67]); Sat, 21 Sep 2019 15:04:31 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We are going to make CONFIG_ARM_V7M optional, so the related cortex-m CPUs should only be created if the switch is enabled. This can best be done if the code resides in a separate file, thus move the related functions to a new file v7m.c which only gets compiled if CONFIG_ARM_V7M is enabled. Signed-off-by: Thomas Huth --- target/arm/Makefile.objs | 1 + target/arm/cpu.c | 146 ----------------------------- target/arm/v7m.c | 193 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 194 insertions(+), 146 deletions(-) create mode 100644 target/arm/v7m.c diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index cf26c16f5f..16b9417a8b 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -61,6 +61,7 @@ obj-y +=3D translate.o op_helper.o obj-y +=3D crypto_helper.o obj-y +=3D iwmmxt_helper.o vec_helper.o neon_helper.o obj-y +=3D m_helper.o +obj-$(CONFIG_ARM_V7M) +=3D v7m.o =20 obj-$(CONFIG_SOFTMMU) +=3D psci.o =20 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index f1f9eecdc8..d5f0d4af61 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -462,31 +462,6 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrup= t_request) return ret; } =20 -#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) -static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) -{ - CPUClass *cc =3D CPU_GET_CLASS(cs); - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - bool ret =3D false; - - /* ARMv7-M interrupt masking works differently than -A or -R. - * There is no FIQ/IRQ distinction. Instead of I and F bits - * masking FIQ and IRQ interrupts, an exception is taken only - * if it is higher priority than the current execution priority - * (which depends on state like BASEPRI, FAULTMASK and the - * currently active exception). - */ - if (interrupt_request & CPU_INTERRUPT_HARD - && (armv7m_nvic_can_take_pending_exception(env->nvic))) { - cs->exception_index =3D EXCP_IRQ; - cc->do_interrupt(cs); - ret =3D true; - } - return ret; -} -#endif - void arm_cpu_update_virq(ARMCPU *cpu) { /* @@ -1881,119 +1856,6 @@ static void arm11mpcore_initfn(Object *obj) cpu->reset_auxcr =3D 1; } =20 -static void cortex_m0_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - set_feature(&cpu->env, ARM_FEATURE_V6); - set_feature(&cpu->env, ARM_FEATURE_M); - - cpu->midr =3D 0x410cc200; -} - -static void cortex_m3_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - set_feature(&cpu->env, ARM_FEATURE_V7); - set_feature(&cpu->env, ARM_FEATURE_M); - set_feature(&cpu->env, ARM_FEATURE_M_MAIN); - cpu->midr =3D 0x410fc231; - cpu->pmsav7_dregion =3D 8; - cpu->id_pfr0 =3D 0x00000030; - cpu->id_pfr1 =3D 0x00000200; - cpu->id_dfr0 =3D 0x00100000; - cpu->id_afr0 =3D 0x00000000; - cpu->id_mmfr0 =3D 0x00000030; - cpu->id_mmfr1 =3D 0x00000000; - cpu->id_mmfr2 =3D 0x00000000; - cpu->id_mmfr3 =3D 0x00000000; - cpu->isar.id_isar0 =3D 0x01141110; - cpu->isar.id_isar1 =3D 0x02111000; - cpu->isar.id_isar2 =3D 0x21112231; - cpu->isar.id_isar3 =3D 0x01111110; - cpu->isar.id_isar4 =3D 0x01310102; - cpu->isar.id_isar5 =3D 0x00000000; - cpu->isar.id_isar6 =3D 0x00000000; -} - -static void cortex_m4_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - set_feature(&cpu->env, ARM_FEATURE_V7); - set_feature(&cpu->env, ARM_FEATURE_M); - set_feature(&cpu->env, ARM_FEATURE_M_MAIN); - set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); - set_feature(&cpu->env, ARM_FEATURE_VFP4); - cpu->midr =3D 0x410fc240; /* r0p0 */ - cpu->pmsav7_dregion =3D 8; - cpu->isar.mvfr0 =3D 0x10110021; - cpu->isar.mvfr1 =3D 0x11000011; - cpu->isar.mvfr2 =3D 0x00000000; - cpu->id_pfr0 =3D 0x00000030; - cpu->id_pfr1 =3D 0x00000200; - cpu->id_dfr0 =3D 0x00100000; - cpu->id_afr0 =3D 0x00000000; - cpu->id_mmfr0 =3D 0x00000030; - cpu->id_mmfr1 =3D 0x00000000; - cpu->id_mmfr2 =3D 0x00000000; - cpu->id_mmfr3 =3D 0x00000000; - cpu->isar.id_isar0 =3D 0x01141110; - cpu->isar.id_isar1 =3D 0x02111000; - cpu->isar.id_isar2 =3D 0x21112231; - cpu->isar.id_isar3 =3D 0x01111110; - cpu->isar.id_isar4 =3D 0x01310102; - cpu->isar.id_isar5 =3D 0x00000000; - cpu->isar.id_isar6 =3D 0x00000000; -} - -static void cortex_m33_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - set_feature(&cpu->env, ARM_FEATURE_V8); - set_feature(&cpu->env, ARM_FEATURE_M); - set_feature(&cpu->env, ARM_FEATURE_M_MAIN); - set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); - set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); - set_feature(&cpu->env, ARM_FEATURE_VFP4); - cpu->midr =3D 0x410fd213; /* r0p3 */ - cpu->pmsav7_dregion =3D 16; - cpu->sau_sregion =3D 8; - cpu->isar.mvfr0 =3D 0x10110021; - cpu->isar.mvfr1 =3D 0x11000011; - cpu->isar.mvfr2 =3D 0x00000040; - cpu->id_pfr0 =3D 0x00000030; - cpu->id_pfr1 =3D 0x00000210; - cpu->id_dfr0 =3D 0x00200000; - cpu->id_afr0 =3D 0x00000000; - cpu->id_mmfr0 =3D 0x00101F40; - cpu->id_mmfr1 =3D 0x00000000; - cpu->id_mmfr2 =3D 0x01000000; - cpu->id_mmfr3 =3D 0x00000000; - cpu->isar.id_isar0 =3D 0x01101110; - cpu->isar.id_isar1 =3D 0x02212000; - cpu->isar.id_isar2 =3D 0x20232232; - cpu->isar.id_isar3 =3D 0x01111131; - cpu->isar.id_isar4 =3D 0x01310132; - cpu->isar.id_isar5 =3D 0x00000000; - cpu->isar.id_isar6 =3D 0x00000000; - cpu->clidr =3D 0x00000000; - cpu->ctr =3D 0x8000c000; -} - -static void arm_v7m_class_init(ObjectClass *oc, void *data) -{ - ARMCPUClass *acc =3D ARM_CPU_CLASS(oc); - CPUClass *cc =3D CPU_CLASS(oc); - - acc->info =3D data; -#ifndef CONFIG_USER_ONLY - cc->do_interrupt =3D arm_v7m_cpu_do_interrupt; -#endif - - cc->cpu_exec_interrupt =3D arm_v7m_cpu_exec_interrupt; -} - static const ARMCPRegInfo cortexr5_cp_reginfo[] =3D { /* Dummy the TCM region regs for the moment */ { .name =3D "ATCM", .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 1, .= opc2 =3D 0, @@ -2518,14 +2380,6 @@ static const ARMCPUInfo arm_cpus[] =3D { { .name =3D "arm1136", .initfn =3D arm1136_initfn }, { .name =3D "arm1176", .initfn =3D arm1176_initfn }, { .name =3D "arm11mpcore", .initfn =3D arm11mpcore_initfn }, - { .name =3D "cortex-m0", .initfn =3D cortex_m0_initfn, - .class_init =3D arm_v7m_class_init }, - { .name =3D "cortex-m3", .initfn =3D cortex_m3_initfn, - .class_init =3D arm_v7m_class_init }, - { .name =3D "cortex-m4", .initfn =3D cortex_m4_initfn, - .class_init =3D arm_v7m_class_init }, - { .name =3D "cortex-m33", .initfn =3D cortex_m33_initfn, - .class_init =3D arm_v7m_class_init }, { .name =3D "cortex-r5", .initfn =3D cortex_r5_initfn }, { .name =3D "cortex-r5f", .initfn =3D cortex_r5f_initfn }, { .name =3D "cortex-a7", .initfn =3D cortex_a7_initfn }, diff --git a/target/arm/v7m.c b/target/arm/v7m.c new file mode 100644 index 0000000000..505043febe --- /dev/null +++ b/target/arm/v7m.c @@ -0,0 +1,193 @@ +/* + * ARM v7m helpers. + * + * This code is licensed under the GNU GPL v2 or later. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/qemu-print.h" +#include "qemu-common.h" +#include "target/arm/idau.h" +#include "qemu/module.h" +#include "qapi/error.h" +#include "qapi/visitor.h" +#include "cpu.h" +#include "internals.h" +#include "exec/exec-all.h" +#include "hw/qdev-properties.h" +#if !defined(CONFIG_USER_ONLY) +#include "hw/loader.h" +#include "hw/boards.h" +#endif +#include "sysemu/sysemu.h" +#include "sysemu/tcg.h" +#include "sysemu/hw_accel.h" +#include "disas/capstone.h" +#include "fpu/softfloat.h" + +#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) + +static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ + CPUClass *cc =3D CPU_GET_CLASS(cs); + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + bool ret =3D false; + + /* + * ARMv7-M interrupt masking works differently than -A or -R. + * There is no FIQ/IRQ distinction. Instead of I and F bits + * masking FIQ and IRQ interrupts, an exception is taken only + * if it is higher priority than the current execution priority + * (which depends on state like BASEPRI, FAULTMASK and the + * currently active exception). + */ + if (interrupt_request & CPU_INTERRUPT_HARD + && (armv7m_nvic_can_take_pending_exception(env->nvic))) { + cs->exception_index =3D EXCP_IRQ; + cc->do_interrupt(cs); + ret =3D true; + } + return ret; +} + +static void cortex_m0_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + set_feature(&cpu->env, ARM_FEATURE_V6); + set_feature(&cpu->env, ARM_FEATURE_M); + + cpu->midr =3D 0x410cc200; +} + +static void cortex_m3_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + set_feature(&cpu->env, ARM_FEATURE_V7); + set_feature(&cpu->env, ARM_FEATURE_M); + set_feature(&cpu->env, ARM_FEATURE_M_MAIN); + cpu->midr =3D 0x410fc231; + cpu->pmsav7_dregion =3D 8; + cpu->id_pfr0 =3D 0x00000030; + cpu->id_pfr1 =3D 0x00000200; + cpu->id_dfr0 =3D 0x00100000; + cpu->id_afr0 =3D 0x00000000; + cpu->id_mmfr0 =3D 0x00000030; + cpu->id_mmfr1 =3D 0x00000000; + cpu->id_mmfr2 =3D 0x00000000; + cpu->id_mmfr3 =3D 0x00000000; + cpu->isar.id_isar0 =3D 0x01141110; + cpu->isar.id_isar1 =3D 0x02111000; + cpu->isar.id_isar2 =3D 0x21112231; + cpu->isar.id_isar3 =3D 0x01111110; + cpu->isar.id_isar4 =3D 0x01310102; + cpu->isar.id_isar5 =3D 0x00000000; + cpu->isar.id_isar6 =3D 0x00000000; +} + +static void cortex_m4_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + set_feature(&cpu->env, ARM_FEATURE_V7); + set_feature(&cpu->env, ARM_FEATURE_M); + set_feature(&cpu->env, ARM_FEATURE_M_MAIN); + set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); + set_feature(&cpu->env, ARM_FEATURE_VFP4); + cpu->midr =3D 0x410fc240; /* r0p0 */ + cpu->pmsav7_dregion =3D 8; + cpu->isar.mvfr0 =3D 0x10110021; + cpu->isar.mvfr1 =3D 0x11000011; + cpu->isar.mvfr2 =3D 0x00000000; + cpu->id_pfr0 =3D 0x00000030; + cpu->id_pfr1 =3D 0x00000200; + cpu->id_dfr0 =3D 0x00100000; + cpu->id_afr0 =3D 0x00000000; + cpu->id_mmfr0 =3D 0x00000030; + cpu->id_mmfr1 =3D 0x00000000; + cpu->id_mmfr2 =3D 0x00000000; + cpu->id_mmfr3 =3D 0x00000000; + cpu->isar.id_isar0 =3D 0x01141110; + cpu->isar.id_isar1 =3D 0x02111000; + cpu->isar.id_isar2 =3D 0x21112231; + cpu->isar.id_isar3 =3D 0x01111110; + cpu->isar.id_isar4 =3D 0x01310102; + cpu->isar.id_isar5 =3D 0x00000000; + cpu->isar.id_isar6 =3D 0x00000000; +} + +static void cortex_m33_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_M); + set_feature(&cpu->env, ARM_FEATURE_M_MAIN); + set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); + set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); + set_feature(&cpu->env, ARM_FEATURE_VFP4); + cpu->midr =3D 0x410fd213; /* r0p3 */ + cpu->pmsav7_dregion =3D 16; + cpu->sau_sregion =3D 8; + cpu->isar.mvfr0 =3D 0x10110021; + cpu->isar.mvfr1 =3D 0x11000011; + cpu->isar.mvfr2 =3D 0x00000040; + cpu->id_pfr0 =3D 0x00000030; + cpu->id_pfr1 =3D 0x00000210; + cpu->id_dfr0 =3D 0x00200000; + cpu->id_afr0 =3D 0x00000000; + cpu->id_mmfr0 =3D 0x00101F40; + cpu->id_mmfr1 =3D 0x00000000; + cpu->id_mmfr2 =3D 0x01000000; + cpu->id_mmfr3 =3D 0x00000000; + cpu->isar.id_isar0 =3D 0x01101110; + cpu->isar.id_isar1 =3D 0x02212000; + cpu->isar.id_isar2 =3D 0x20232232; + cpu->isar.id_isar3 =3D 0x01111131; + cpu->isar.id_isar4 =3D 0x01310132; + cpu->isar.id_isar5 =3D 0x00000000; + cpu->isar.id_isar6 =3D 0x00000000; + cpu->clidr =3D 0x00000000; + cpu->ctr =3D 0x8000c000; +} + +static void arm_v7m_class_init(ObjectClass *oc, void *data) +{ + ARMCPUClass *acc =3D ARM_CPU_CLASS(oc); + CPUClass *cc =3D CPU_CLASS(oc); + + acc->info =3D data; +#ifndef CONFIG_USER_ONLY + cc->do_interrupt =3D arm_v7m_cpu_do_interrupt; +#endif + + cc->cpu_exec_interrupt =3D arm_v7m_cpu_exec_interrupt; +} + +static const ARMCPUInfo arm_v7m_cpus[] =3D { + { .name =3D "cortex-m0", .initfn =3D cortex_m0_initfn, + .class_init =3D arm_v7m_class_init }, + { .name =3D "cortex-m3", .initfn =3D cortex_m3_initfn, + .class_init =3D arm_v7m_class_init }, + { .name =3D "cortex-m4", .initfn =3D cortex_m4_initfn, + .class_init =3D arm_v7m_class_init }, + { .name =3D "cortex-m33", .initfn =3D cortex_m33_initfn, + .class_init =3D arm_v7m_class_init }, + { .name =3D NULL } +}; + +static void arm_v7m_cpu_register_types(void) +{ + const ARMCPUInfo *info =3D arm_v7m_cpus; + + while (info->name) { + arm_cpu_register(info); + info++; + } +} + +type_init(arm_v7m_cpu_register_types) + +#endif --=20 2.18.1