From nobody Thu May 2 05:25:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1569078480; cv=none; d=zoho.com; s=zohoarc; b=UzHxEtZoybNem30wIEcvF4gWABIFdsQ6QhdfDRBYiblDsjs8Zgng/7TnfVVGv99Mg6MYEdSTiygN7lLDU7rPi0bn4iszJ21c22Hnd68GF1Rnv6DmgmBp1hcUJb25wwPN26UQCvk7F/hpwoPus4R/MRDsL+zjksVmYROCc/DyF2I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569078480; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=1Ord4hq0McIiSyIY/RPxMwmTzmN/Tl35umNHpn/Wb/Q=; b=NsoyIfbaUXDAzlC896I1jXr9yjpG1qjAA36uXL3ZyKC5Pjrd5O44q788+SagjvzfQSmHZW61MEiubgrxLptgFgkfRukCbKlZiW6m0N75uVdu9G9vna2IZy/k/U20UEL/ehlIxthQhHN5n+itrlSE73lRGHFLaG+WTzcHEkws+Jk= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1569078480823173.9314586085652; Sat, 21 Sep 2019 08:08:00 -0700 (PDT) Received: from localhost ([::1]:42318 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iBgzN-0007p1-0Q for importer@patchew.org; Sat, 21 Sep 2019 11:07:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39780) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iBgw6-0004L1-2l for qemu-devel@nongnu.org; Sat, 21 Sep 2019 11:04:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iBgw4-0003Dm-UM for qemu-devel@nongnu.org; Sat, 21 Sep 2019 11:04:34 -0400 Received: from mx1.redhat.com ([209.132.183.28]:40496) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iBgw2-0003Cr-A5; Sat, 21 Sep 2019 11:04:30 -0400 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 87CF23082B45; Sat, 21 Sep 2019 15:04:29 +0000 (UTC) Received: from thuth.com (ovpn-116-27.ams2.redhat.com [10.36.116.27]) by smtp.corp.redhat.com (Postfix) with ESMTP id 16C1160920; Sat, 21 Sep 2019 15:04:27 +0000 (UTC) From: Thomas Huth To: qemu-devel@nongnu.org, Peter Maydell Subject: [PATCH 1/4] target/arm: Make cpu_register() and set_feature() available for other files Date: Sat, 21 Sep 2019 17:04:17 +0200 Message-Id: <20190921150420.30743-2-thuth@redhat.com> In-Reply-To: <20190921150420.30743-1-thuth@redhat.com> References: <20190921150420.30743-1-thuth@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.45]); Sat, 21 Sep 2019 15:04:29 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Move the common set_feature() and unset_feature() functions from cpu.c and cpu64.c to internals.h, and make cpu_register() (renamed to arm_cpu_registe= r()) available from there, too, so we can register CPUs also from other files in the future. Signed-off-by: Thomas Huth Reviewed-by: Eric Auger --- target/arm/cpu.c | 20 ++------------------ target/arm/cpu64.c | 17 +---------------- target/arm/internals.h | 18 ++++++++++++++++++ 3 files changed, 21 insertions(+), 34 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 2399c14471..f1f9eecdc8 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -614,16 +614,6 @@ static bool arm_cpu_virtio_is_big_endian(CPUState *cs) =20 #endif =20 -static inline void set_feature(CPUARMState *env, int feature) -{ - env->features |=3D 1ULL << feature; -} - -static inline void unset_feature(CPUARMState *env, int feature) -{ - env->features &=3D ~(1ULL << feature); -} - static int print_insn_thumb1(bfd_vma pc, disassemble_info *info) { @@ -2515,12 +2505,6 @@ static void arm_max_initfn(Object *obj) =20 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ =20 -struct ARMCPUInfo { - const char *name; - void (*initfn)(Object *obj); - void (*class_init)(ObjectClass *oc, void *data); -}; - static const ARMCPUInfo arm_cpus[] =3D { #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) { .name =3D "arm926", .initfn =3D arm926_initfn }, @@ -2681,7 +2665,7 @@ static void cpu_register_class_init(ObjectClass *oc, = void *data) acc->info =3D data; } =20 -static void cpu_register(const ARMCPUInfo *info) +void arm_cpu_register(const ARMCPUInfo *info) { TypeInfo type_info =3D { .parent =3D TYPE_ARM_CPU, @@ -2722,7 +2706,7 @@ static void arm_cpu_register_types(void) type_register_static(&idau_interface_type_info); =20 while (info->name) { - cpu_register(info); + arm_cpu_register(info); info++; } =20 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index d7f5bf610a..5239ba5529 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -21,6 +21,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "cpu.h" +#include "internals.h" #include "qemu/module.h" #if !defined(CONFIG_USER_ONLY) #include "hw/loader.h" @@ -29,16 +30,6 @@ #include "kvm_arm.h" #include "qapi/visitor.h" =20 -static inline void set_feature(CPUARMState *env, int feature) -{ - env->features |=3D 1ULL << feature; -} - -static inline void unset_feature(CPUARMState *env, int feature) -{ - env->features &=3D ~(1ULL << feature); -} - #ifndef CONFIG_USER_ONLY static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *= ri) { @@ -396,12 +387,6 @@ static void aarch64_max_initfn(Object *obj) } } =20 -struct ARMCPUInfo { - const char *name; - void (*initfn)(Object *obj); - void (*class_init)(ObjectClass *oc, void *data); -}; - static const ARMCPUInfo aarch64_cpus[] =3D { { .name =3D "cortex-a57", .initfn =3D aarch64_a57_initfn }, { .name =3D "cortex-a53", .initfn =3D aarch64_a53_initfn }, diff --git a/target/arm/internals.h b/target/arm/internals.h index 232d963875..e71196ed5f 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1046,4 +1046,22 @@ void arm_log_exception(int idx); =20 #endif /* !CONFIG_USER_ONLY */ =20 +static inline void set_feature(CPUARMState *env, int feature) +{ + env->features |=3D 1ULL << feature; +} + +static inline void unset_feature(CPUARMState *env, int feature) +{ + env->features &=3D ~(1ULL << feature); +} + +struct ARMCPUInfo { + const char *name; + void (*initfn)(Object *obj); + void (*class_init)(ObjectClass *oc, void *data); +}; + +void arm_cpu_register(const ARMCPUInfo *info); + #endif --=20 2.18.1 From nobody Thu May 2 05:25:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1569078584; cv=none; d=zoho.com; s=zohoarc; b=obncoiK00dNXOFy5AhZntGqMCSLm/26vpZUlabc4kQo0QGD4TiUweLlFnR4/aBWIcKU0dMXRsxOQ8KNjI7j+EeCJSnGCONQzDqdDNMLVt8Jq+FJsHv/OiVM9+T9eU/N5K4fogoeYrzdjWGJ9TmuOZfQCOIrWLBfW7MX3xhcep4o= ARC-Message-Signature: i=1; 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Sat, 21 Sep 2019 15:04:29 +0000 (UTC) From: Thomas Huth To: qemu-devel@nongnu.org, Peter Maydell Subject: [PATCH 2/4] target/arm: Move cortex-m related functions to new file v7m.c Date: Sat, 21 Sep 2019 17:04:18 +0200 Message-Id: <20190921150420.30743-3-thuth@redhat.com> In-Reply-To: <20190921150420.30743-1-thuth@redhat.com> References: <20190921150420.30743-1-thuth@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.6.2 (mx1.redhat.com [10.5.110.67]); Sat, 21 Sep 2019 15:04:31 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We are going to make CONFIG_ARM_V7M optional, so the related cortex-m CPUs should only be created if the switch is enabled. This can best be done if the code resides in a separate file, thus move the related functions to a new file v7m.c which only gets compiled if CONFIG_ARM_V7M is enabled. Signed-off-by: Thomas Huth --- target/arm/Makefile.objs | 1 + target/arm/cpu.c | 146 ----------------------------- target/arm/v7m.c | 193 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 194 insertions(+), 146 deletions(-) create mode 100644 target/arm/v7m.c diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index cf26c16f5f..16b9417a8b 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -61,6 +61,7 @@ obj-y +=3D translate.o op_helper.o obj-y +=3D crypto_helper.o obj-y +=3D iwmmxt_helper.o vec_helper.o neon_helper.o obj-y +=3D m_helper.o +obj-$(CONFIG_ARM_V7M) +=3D v7m.o =20 obj-$(CONFIG_SOFTMMU) +=3D psci.o =20 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index f1f9eecdc8..d5f0d4af61 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -462,31 +462,6 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrup= t_request) return ret; } =20 -#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) -static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) -{ - CPUClass *cc =3D CPU_GET_CLASS(cs); - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - bool ret =3D false; - - /* ARMv7-M interrupt masking works differently than -A or -R. - * There is no FIQ/IRQ distinction. Instead of I and F bits - * masking FIQ and IRQ interrupts, an exception is taken only - * if it is higher priority than the current execution priority - * (which depends on state like BASEPRI, FAULTMASK and the - * currently active exception). - */ - if (interrupt_request & CPU_INTERRUPT_HARD - && (armv7m_nvic_can_take_pending_exception(env->nvic))) { - cs->exception_index =3D EXCP_IRQ; - cc->do_interrupt(cs); - ret =3D true; - } - return ret; -} -#endif - void arm_cpu_update_virq(ARMCPU *cpu) { /* @@ -1881,119 +1856,6 @@ static void arm11mpcore_initfn(Object *obj) cpu->reset_auxcr =3D 1; } =20 -static void cortex_m0_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - set_feature(&cpu->env, ARM_FEATURE_V6); - set_feature(&cpu->env, ARM_FEATURE_M); - - cpu->midr =3D 0x410cc200; -} - -static void cortex_m3_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - set_feature(&cpu->env, ARM_FEATURE_V7); - set_feature(&cpu->env, ARM_FEATURE_M); - set_feature(&cpu->env, ARM_FEATURE_M_MAIN); - cpu->midr =3D 0x410fc231; - cpu->pmsav7_dregion =3D 8; - cpu->id_pfr0 =3D 0x00000030; - cpu->id_pfr1 =3D 0x00000200; - cpu->id_dfr0 =3D 0x00100000; - cpu->id_afr0 =3D 0x00000000; - cpu->id_mmfr0 =3D 0x00000030; - cpu->id_mmfr1 =3D 0x00000000; - cpu->id_mmfr2 =3D 0x00000000; - cpu->id_mmfr3 =3D 0x00000000; - cpu->isar.id_isar0 =3D 0x01141110; - cpu->isar.id_isar1 =3D 0x02111000; - cpu->isar.id_isar2 =3D 0x21112231; - cpu->isar.id_isar3 =3D 0x01111110; - cpu->isar.id_isar4 =3D 0x01310102; - cpu->isar.id_isar5 =3D 0x00000000; - cpu->isar.id_isar6 =3D 0x00000000; -} - -static void cortex_m4_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - set_feature(&cpu->env, ARM_FEATURE_V7); - set_feature(&cpu->env, ARM_FEATURE_M); - set_feature(&cpu->env, ARM_FEATURE_M_MAIN); - set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); - set_feature(&cpu->env, ARM_FEATURE_VFP4); - cpu->midr =3D 0x410fc240; /* r0p0 */ - cpu->pmsav7_dregion =3D 8; - cpu->isar.mvfr0 =3D 0x10110021; - cpu->isar.mvfr1 =3D 0x11000011; - cpu->isar.mvfr2 =3D 0x00000000; - cpu->id_pfr0 =3D 0x00000030; - cpu->id_pfr1 =3D 0x00000200; - cpu->id_dfr0 =3D 0x00100000; - cpu->id_afr0 =3D 0x00000000; - cpu->id_mmfr0 =3D 0x00000030; - cpu->id_mmfr1 =3D 0x00000000; - cpu->id_mmfr2 =3D 0x00000000; - cpu->id_mmfr3 =3D 0x00000000; - cpu->isar.id_isar0 =3D 0x01141110; - cpu->isar.id_isar1 =3D 0x02111000; - cpu->isar.id_isar2 =3D 0x21112231; - cpu->isar.id_isar3 =3D 0x01111110; - cpu->isar.id_isar4 =3D 0x01310102; - cpu->isar.id_isar5 =3D 0x00000000; - cpu->isar.id_isar6 =3D 0x00000000; -} - -static void cortex_m33_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - set_feature(&cpu->env, ARM_FEATURE_V8); - set_feature(&cpu->env, ARM_FEATURE_M); - set_feature(&cpu->env, ARM_FEATURE_M_MAIN); - set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); - set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); - set_feature(&cpu->env, ARM_FEATURE_VFP4); - cpu->midr =3D 0x410fd213; /* r0p3 */ - cpu->pmsav7_dregion =3D 16; - cpu->sau_sregion =3D 8; - cpu->isar.mvfr0 =3D 0x10110021; - cpu->isar.mvfr1 =3D 0x11000011; - cpu->isar.mvfr2 =3D 0x00000040; - cpu->id_pfr0 =3D 0x00000030; - cpu->id_pfr1 =3D 0x00000210; - cpu->id_dfr0 =3D 0x00200000; - cpu->id_afr0 =3D 0x00000000; - cpu->id_mmfr0 =3D 0x00101F40; - cpu->id_mmfr1 =3D 0x00000000; - cpu->id_mmfr2 =3D 0x01000000; - cpu->id_mmfr3 =3D 0x00000000; - cpu->isar.id_isar0 =3D 0x01101110; - cpu->isar.id_isar1 =3D 0x02212000; - cpu->isar.id_isar2 =3D 0x20232232; - cpu->isar.id_isar3 =3D 0x01111131; - cpu->isar.id_isar4 =3D 0x01310132; - cpu->isar.id_isar5 =3D 0x00000000; - cpu->isar.id_isar6 =3D 0x00000000; - cpu->clidr =3D 0x00000000; - cpu->ctr =3D 0x8000c000; -} - -static void arm_v7m_class_init(ObjectClass *oc, void *data) -{ - ARMCPUClass *acc =3D ARM_CPU_CLASS(oc); - CPUClass *cc =3D CPU_CLASS(oc); - - acc->info =3D data; -#ifndef CONFIG_USER_ONLY - cc->do_interrupt =3D arm_v7m_cpu_do_interrupt; -#endif - - cc->cpu_exec_interrupt =3D arm_v7m_cpu_exec_interrupt; -} - static const ARMCPRegInfo cortexr5_cp_reginfo[] =3D { /* Dummy the TCM region regs for the moment */ { .name =3D "ATCM", .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 1, .= opc2 =3D 0, @@ -2518,14 +2380,6 @@ static const ARMCPUInfo arm_cpus[] =3D { { .name =3D "arm1136", .initfn =3D arm1136_initfn }, { .name =3D "arm1176", .initfn =3D arm1176_initfn }, { .name =3D "arm11mpcore", .initfn =3D arm11mpcore_initfn }, - { .name =3D "cortex-m0", .initfn =3D cortex_m0_initfn, - .class_init =3D arm_v7m_class_init }, - { .name =3D "cortex-m3", .initfn =3D cortex_m3_initfn, - .class_init =3D arm_v7m_class_init }, - { .name =3D "cortex-m4", .initfn =3D cortex_m4_initfn, - .class_init =3D arm_v7m_class_init }, - { .name =3D "cortex-m33", .initfn =3D cortex_m33_initfn, - .class_init =3D arm_v7m_class_init }, { .name =3D "cortex-r5", .initfn =3D cortex_r5_initfn }, { .name =3D "cortex-r5f", .initfn =3D cortex_r5f_initfn }, { .name =3D "cortex-a7", .initfn =3D cortex_a7_initfn }, diff --git a/target/arm/v7m.c b/target/arm/v7m.c new file mode 100644 index 0000000000..505043febe --- /dev/null +++ b/target/arm/v7m.c @@ -0,0 +1,193 @@ +/* + * ARM v7m helpers. + * + * This code is licensed under the GNU GPL v2 or later. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/qemu-print.h" +#include "qemu-common.h" +#include "target/arm/idau.h" +#include "qemu/module.h" +#include "qapi/error.h" +#include "qapi/visitor.h" +#include "cpu.h" +#include "internals.h" +#include "exec/exec-all.h" +#include "hw/qdev-properties.h" +#if !defined(CONFIG_USER_ONLY) +#include "hw/loader.h" +#include "hw/boards.h" +#endif +#include "sysemu/sysemu.h" +#include "sysemu/tcg.h" +#include "sysemu/hw_accel.h" +#include "disas/capstone.h" +#include "fpu/softfloat.h" + +#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) + +static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ + CPUClass *cc =3D CPU_GET_CLASS(cs); + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + bool ret =3D false; + + /* + * ARMv7-M interrupt masking works differently than -A or -R. + * There is no FIQ/IRQ distinction. Instead of I and F bits + * masking FIQ and IRQ interrupts, an exception is taken only + * if it is higher priority than the current execution priority + * (which depends on state like BASEPRI, FAULTMASK and the + * currently active exception). + */ + if (interrupt_request & CPU_INTERRUPT_HARD + && (armv7m_nvic_can_take_pending_exception(env->nvic))) { + cs->exception_index =3D EXCP_IRQ; + cc->do_interrupt(cs); + ret =3D true; + } + return ret; +} + +static void cortex_m0_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + set_feature(&cpu->env, ARM_FEATURE_V6); + set_feature(&cpu->env, ARM_FEATURE_M); + + cpu->midr =3D 0x410cc200; +} + +static void cortex_m3_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + set_feature(&cpu->env, ARM_FEATURE_V7); + set_feature(&cpu->env, ARM_FEATURE_M); + set_feature(&cpu->env, ARM_FEATURE_M_MAIN); + cpu->midr =3D 0x410fc231; + cpu->pmsav7_dregion =3D 8; + cpu->id_pfr0 =3D 0x00000030; + cpu->id_pfr1 =3D 0x00000200; + cpu->id_dfr0 =3D 0x00100000; + cpu->id_afr0 =3D 0x00000000; + cpu->id_mmfr0 =3D 0x00000030; + cpu->id_mmfr1 =3D 0x00000000; + cpu->id_mmfr2 =3D 0x00000000; + cpu->id_mmfr3 =3D 0x00000000; + cpu->isar.id_isar0 =3D 0x01141110; + cpu->isar.id_isar1 =3D 0x02111000; + cpu->isar.id_isar2 =3D 0x21112231; + cpu->isar.id_isar3 =3D 0x01111110; + cpu->isar.id_isar4 =3D 0x01310102; + cpu->isar.id_isar5 =3D 0x00000000; + cpu->isar.id_isar6 =3D 0x00000000; +} + +static void cortex_m4_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + set_feature(&cpu->env, ARM_FEATURE_V7); + set_feature(&cpu->env, ARM_FEATURE_M); + set_feature(&cpu->env, ARM_FEATURE_M_MAIN); + set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); + set_feature(&cpu->env, ARM_FEATURE_VFP4); + cpu->midr =3D 0x410fc240; /* r0p0 */ + cpu->pmsav7_dregion =3D 8; + cpu->isar.mvfr0 =3D 0x10110021; + cpu->isar.mvfr1 =3D 0x11000011; + cpu->isar.mvfr2 =3D 0x00000000; + cpu->id_pfr0 =3D 0x00000030; + cpu->id_pfr1 =3D 0x00000200; + cpu->id_dfr0 =3D 0x00100000; + cpu->id_afr0 =3D 0x00000000; + cpu->id_mmfr0 =3D 0x00000030; + cpu->id_mmfr1 =3D 0x00000000; + cpu->id_mmfr2 =3D 0x00000000; + cpu->id_mmfr3 =3D 0x00000000; + cpu->isar.id_isar0 =3D 0x01141110; + cpu->isar.id_isar1 =3D 0x02111000; + cpu->isar.id_isar2 =3D 0x21112231; + cpu->isar.id_isar3 =3D 0x01111110; + cpu->isar.id_isar4 =3D 0x01310102; + cpu->isar.id_isar5 =3D 0x00000000; + cpu->isar.id_isar6 =3D 0x00000000; +} + +static void cortex_m33_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_M); + set_feature(&cpu->env, ARM_FEATURE_M_MAIN); + set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); + set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); + set_feature(&cpu->env, ARM_FEATURE_VFP4); + cpu->midr =3D 0x410fd213; /* r0p3 */ + cpu->pmsav7_dregion =3D 16; + cpu->sau_sregion =3D 8; + cpu->isar.mvfr0 =3D 0x10110021; + cpu->isar.mvfr1 =3D 0x11000011; + cpu->isar.mvfr2 =3D 0x00000040; + cpu->id_pfr0 =3D 0x00000030; + cpu->id_pfr1 =3D 0x00000210; + cpu->id_dfr0 =3D 0x00200000; + cpu->id_afr0 =3D 0x00000000; + cpu->id_mmfr0 =3D 0x00101F40; + cpu->id_mmfr1 =3D 0x00000000; + cpu->id_mmfr2 =3D 0x01000000; + cpu->id_mmfr3 =3D 0x00000000; + cpu->isar.id_isar0 =3D 0x01101110; + cpu->isar.id_isar1 =3D 0x02212000; + cpu->isar.id_isar2 =3D 0x20232232; + cpu->isar.id_isar3 =3D 0x01111131; + cpu->isar.id_isar4 =3D 0x01310132; + cpu->isar.id_isar5 =3D 0x00000000; + cpu->isar.id_isar6 =3D 0x00000000; + cpu->clidr =3D 0x00000000; + cpu->ctr =3D 0x8000c000; +} + +static void arm_v7m_class_init(ObjectClass *oc, void *data) +{ + ARMCPUClass *acc =3D ARM_CPU_CLASS(oc); + CPUClass *cc =3D CPU_CLASS(oc); + + acc->info =3D data; +#ifndef CONFIG_USER_ONLY + cc->do_interrupt =3D arm_v7m_cpu_do_interrupt; +#endif + + cc->cpu_exec_interrupt =3D arm_v7m_cpu_exec_interrupt; +} + +static const ARMCPUInfo arm_v7m_cpus[] =3D { + { .name =3D "cortex-m0", .initfn =3D cortex_m0_initfn, + .class_init =3D arm_v7m_class_init }, + { .name =3D "cortex-m3", .initfn =3D cortex_m3_initfn, + .class_init =3D arm_v7m_class_init }, + { .name =3D "cortex-m4", .initfn =3D cortex_m4_initfn, + .class_init =3D arm_v7m_class_init }, + { .name =3D "cortex-m33", .initfn =3D cortex_m33_initfn, + .class_init =3D arm_v7m_class_init }, + { .name =3D NULL } +}; + +static void arm_v7m_cpu_register_types(void) +{ + const ARMCPUInfo *info =3D arm_v7m_cpus; + + while (info->name) { + arm_cpu_register(info); + info++; + } +} + +type_init(arm_v7m_cpu_register_types) + +#endif --=20 2.18.1 From nobody Thu May 2 05:25:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1569078487; cv=none; d=zoho.com; s=zohoarc; b=SkH5T49rbQ7rSsr9jR2uG9xf4UZrBydR5sExiWPAIC+kUgK0VT4P8PeXiQQ8Vet87SqQa1EXJw5yhnfeJyz1clbK/BboggSPKAlpAnq8M03JMM++dhvuk+vGKBQQs7U3tgILmlNhfhBfwu2+hMkgA9XdnN29zXxE7vZVRMtzw3s= ARC-Message-Signature: i=1; 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Sat, 21 Sep 2019 15:04:31 +0000 (UTC) From: Thomas Huth To: qemu-devel@nongnu.org, Peter Maydell Subject: [PATCH 3/4] hw/arm: Move armv7m_nvic.c to hw/arm/ and always enable it for arm builds Date: Sat, 21 Sep 2019 17:04:19 +0200 Message-Id: <20190921150420.30743-4-thuth@redhat.com> In-Reply-To: <20190921150420.30743-1-thuth@redhat.com> References: <20190921150420.30743-1-thuth@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.45]); Sat, 21 Sep 2019 15:04:33 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" qemu-system-arm/-aarch64 currently can't be built without setting the switch CONFIG_ARM_V7M=3Dy - which we currently always do in the config file default-configs/arm-softmmu.mak. This is because the code in target/arm/ calls many functions from this armv7m_nvic.c, and thus linking fails without this file. So armv7m_nvic.c should not be under the CONFIG_ARM_V7M switch, but always compiled for arm builds. Since we can not simply do this in hw/intc/ (with "obj-y +=3D ..." it would get compiled for all other architectures, too), let's move the file to hw/arm/ instead and always enable it there. Signed-off-by: Thomas Huth --- hw/arm/Makefile.objs | 2 ++ hw/{intc =3D> arm}/armv7m_nvic.c | 0 hw/arm/trace-events | 17 +++++++++++++++++ hw/intc/Makefile.objs | 1 - hw/intc/trace-events | 17 ----------------- 5 files changed, 19 insertions(+), 18 deletions(-) rename hw/{intc =3D> arm}/armv7m_nvic.c (100%) diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs index 43ce8d5b19..3c94d383a0 100644 --- a/hw/arm/Makefile.objs +++ b/hw/arm/Makefile.objs @@ -27,6 +27,8 @@ obj-$(CONFIG_VEXPRESS) +=3D vexpress.o obj-$(CONFIG_ZYNQ) +=3D xilinx_zynq.o obj-$(CONFIG_SABRELITE) +=3D sabrelite.o =20 +# Note: armv7m_nvic.o is currently always required for linking +obj-y +=3D armv7m_nvic.o obj-$(CONFIG_ARM_V7M) +=3D armv7m.o obj-$(CONFIG_EXYNOS4) +=3D exynos4210.o obj-$(CONFIG_PXA2XX) +=3D pxa2xx.o pxa2xx_gpio.o pxa2xx_pic.o diff --git a/hw/intc/armv7m_nvic.c b/hw/arm/armv7m_nvic.c similarity index 100% rename from hw/intc/armv7m_nvic.c rename to hw/arm/armv7m_nvic.c diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 0acedcedc6..3068202a4c 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -1,5 +1,22 @@ # See docs/devel/tracing.txt for syntax documentation. =20 +# armv7m_nvic.c +nvic_recompute_state(int vectpending, int vectpending_prio, int exception_= prio) "NVIC state recomputed: vectpending %d vectpending_prio %d exception_= prio %d" +nvic_recompute_state_secure(int vectpending, bool vectpending_is_s_banked,= int vectpending_prio, int exception_prio) "NVIC state recomputed: vectpend= ing %d is_s_banked %d vectpending_prio %d exception_prio %d" +nvic_set_prio(int irq, bool secure, uint8_t prio) "NVIC set irq %d secure-= bank %d priority %d" +nvic_irq_update(int vectpending, int pendprio, int exception_prio, int lev= el) "NVIC vectpending %d pending prio %d exception_prio %d: setting irq lin= e to %d" +nvic_escalate_prio(int irq, int irqprio, int runprio) "NVIC escalating irq= %d to HardFault: insufficient priority %d >=3D %d" +nvic_escalate_disabled(int irq) "NVIC escalating irq %d to HardFault: disa= bled" +nvic_set_pending(int irq, bool secure, bool targets_secure, bool derived, = int en, int prio) "NVIC set pending irq %d secure-bank %d targets_secure %d= derived %d (enabled: %d priority %d)" +nvic_clear_pending(int irq, bool secure, int en, int prio) "NVIC clear pen= ding irq %d secure-bank %d (enabled: %d priority %d)" +nvic_acknowledge_irq(int irq, int prio) "NVIC acknowledge IRQ: %d now acti= ve (prio %d)" +nvic_get_pending_irq_info(int irq, bool secure) "NVIC next IRQ %d: targets= _secure: %d" +nvic_complete_irq(int irq, bool secure) "NVIC complete IRQ %d (secure %d)" +nvic_set_irq_level(int irq, int level) "NVIC external irq %d level set to = %d" +nvic_set_nmi_level(int level) "NVIC external NMI level set to %d" +nvic_sysreg_read(uint64_t addr, uint32_t value, unsigned size) "NVIC sysre= g read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u" +nvic_sysreg_write(uint64_t addr, uint32_t value, unsigned size) "NVIC sysr= eg write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u" + # virt-acpi-build.c virt_acpi_setup(void) "No fw cfg or ACPI disabled. Bailing out." =20 diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs index f726d87532..2d981abb4e 100644 --- a/hw/intc/Makefile.objs +++ b/hw/intc/Makefile.objs @@ -26,7 +26,6 @@ obj-$(CONFIG_APIC) +=3D apic.o apic_common.o obj-$(CONFIG_ARM_GIC_KVM) +=3D arm_gic_kvm.o obj-$(call land,$(CONFIG_ARM_GIC_KVM),$(TARGET_AARCH64)) +=3D arm_gicv3_kv= m.o obj-$(call land,$(CONFIG_ARM_GIC_KVM),$(TARGET_AARCH64)) +=3D arm_gicv3_it= s_kvm.o -obj-$(CONFIG_ARM_V7M) +=3D armv7m_nvic.o obj-$(CONFIG_EXYNOS4) +=3D exynos4210_gic.o exynos4210_combiner.o obj-$(CONFIG_GRLIB) +=3D grlib_irqmp.o obj-$(CONFIG_IOAPIC) +=3D ioapic.o diff --git a/hw/intc/trace-events b/hw/intc/trace-events index 90c9d07c1a..09a7fedee8 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -179,23 +179,6 @@ gicv3_redist_badwrite(uint32_t cpu, uint64_t offset, u= int64_t data, unsigned siz gicv3_redist_set_irq(uint32_t cpu, int irq, int level) "GICv3 redistributo= r 0x%x interrupt %d level changed to %d" gicv3_redist_send_sgi(uint32_t cpu, int irq) "GICv3 redistributor 0x%x pen= ding SGI %d" =20 -# armv7m_nvic.c -nvic_recompute_state(int vectpending, int vectpending_prio, int exception_= prio) "NVIC state recomputed: vectpending %d vectpending_prio %d exception_= prio %d" -nvic_recompute_state_secure(int vectpending, bool vectpending_is_s_banked,= int vectpending_prio, int exception_prio) "NVIC state recomputed: vectpend= ing %d is_s_banked %d vectpending_prio %d exception_prio %d" -nvic_set_prio(int irq, bool secure, uint8_t prio) "NVIC set irq %d secure-= bank %d priority %d" -nvic_irq_update(int vectpending, int pendprio, int exception_prio, int lev= el) "NVIC vectpending %d pending prio %d exception_prio %d: setting irq lin= e to %d" -nvic_escalate_prio(int irq, int irqprio, int runprio) "NVIC escalating irq= %d to HardFault: insufficient priority %d >=3D %d" -nvic_escalate_disabled(int irq) "NVIC escalating irq %d to HardFault: disa= bled" -nvic_set_pending(int irq, bool secure, bool targets_secure, bool derived, = int en, int prio) "NVIC set pending irq %d secure-bank %d targets_secure %d= derived %d (enabled: %d priority %d)" -nvic_clear_pending(int irq, bool secure, int en, int prio) "NVIC clear pen= ding irq %d secure-bank %d (enabled: %d priority %d)" -nvic_acknowledge_irq(int irq, int prio) "NVIC acknowledge IRQ: %d now acti= ve (prio %d)" -nvic_get_pending_irq_info(int irq, bool secure) "NVIC next IRQ %d: targets= _secure: %d" -nvic_complete_irq(int irq, bool secure) "NVIC complete IRQ %d (secure %d)" -nvic_set_irq_level(int irq, int level) "NVIC external irq %d level set to = %d" -nvic_set_nmi_level(int level) "NVIC external NMI level set to %d" -nvic_sysreg_read(uint64_t addr, uint32_t value, unsigned size) "NVIC sysre= g read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u" -nvic_sysreg_write(uint64_t addr, uint32_t value, unsigned size) "NVIC sysr= eg write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u" - # heathrow_pic.c heathrow_write(uint64_t addr, unsigned int n, uint64_t value) "0x%"PRIx64"= %u: 0x%"PRIx64 heathrow_read(uint64_t addr, unsigned int n, uint64_t value) "0x%"PRIx64" = %u: 0x%"PRIx64 --=20 2.18.1 From nobody Thu May 2 05:25:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Sat, 21 Sep 2019 11:04:36 -0400 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 455F9882FB; Sat, 21 Sep 2019 15:04:35 +0000 (UTC) Received: from thuth.com (ovpn-116-27.ams2.redhat.com [10.36.116.27]) by smtp.corp.redhat.com (Postfix) with ESMTP id CA237608A5; Sat, 21 Sep 2019 15:04:33 +0000 (UTC) From: Thomas Huth To: qemu-devel@nongnu.org, Peter Maydell Subject: [PATCH 4/4] default-configs: Do not enforce CONFIG_ARM_V7M anymore Date: Sat, 21 Sep 2019 17:04:20 +0200 Message-Id: <20190921150420.30743-5-thuth@redhat.com> In-Reply-To: <20190921150420.30743-1-thuth@redhat.com> References: <20190921150420.30743-1-thuth@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.28]); Sat, 21 Sep 2019 15:04:35 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The arm builds can now be done without CONFIG_ARM_V7M, so do not enforce this config switch anymore, it's getting selected in hw/arm/Kconfig automatically if needed. Signed-off-by: Thomas Huth --- default-configs/arm-softmmu.mak | 3 --- 1 file changed, 3 deletions(-) diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.= mak index 1f2e0e7fde..64f5ac24bf 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -1,8 +1,5 @@ # Default configuration for arm-softmmu =20 -# TODO: ARM_V7M is currently always required - make this more flexible! -CONFIG_ARM_V7M=3Dy - # CONFIG_PCI_DEVICES=3Dn # CONFIG_TEST_DEVICES=3Dn =20 --=20 2.18.1