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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id b144sm2710547wmb.3.2019.09.20.10.40.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Sep 2019 10:40:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:mime-version :content-transfer-encoding; bh=pd1d+il4V+KkThmMTERSYGXdeHgQGOjSI8wZb/+55zM=; b=dZAYsfq3BnTXrhPNXwWj5FbwPIBkonMcemnzkmg4/rgJAoO630LTjjjv3kwwa2qH51 suIC05jyge/GygtOfpnFLSikuGu5SbOERB5N2DFSkkRXNHrAhVM9t6dAlYyg7wtl4Ogh y7MkRvoNK3aeDK7E5bftNOV/UmlBoWAauKelqK3lwf93q+bClN0g0PH7A7hb5ugC3lhh yMfqw4JPUtfSqBCsEUkNGwuNbHzO8+C0HyNckz6sLhacbYzoLikm9t5dWoHOt/uYgw2g cdBkibvaM8E3VWfUBQybbtlNYLnE21+a9BpPI8Mt/hGDCMrBEC6K46kSy/X3YAj0YKHw M2lg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:mime-version :content-transfer-encoding; bh=pd1d+il4V+KkThmMTERSYGXdeHgQGOjSI8wZb/+55zM=; b=etXXaOHE+sGL0UvILHaEyfN6Ug2655duUR5QAB7QII9f8hpjnszXE8rtODWgZRFJMP +PpNBNx7m+K16+Ol4Z2m/qKdg0RMN5H91g4cuA3gi5TbWK9eXsPoktdo5sOC9ALxB0TS W4hcEVJaAzcAH8GtTq8GD03J2/K4AdGffVt9BaTBmR43wnL30NFeG/LuFhtcs/Tz+Nmb 0IT1QN/MQu5d96C55gWqLkU/6mywi5L2Zbia8Ruej6dDG98LG4bbMjJQRW9OO/S9JdA3 //YkpuW2XSa1skBBzLoX0mHiuzzvFPvOOkd+iixUNCc4H/2l6DVFvugVBDMwTsV+3b3A 6VMA== X-Gm-Message-State: APjAAAVc7lNVBedzpqtexVvvrxurikGW+GSjpIispiQHCaINdlvsxeba Gd8+WJ19jjwWGMiGtibUxiO0mQ== X-Google-Smtp-Source: APXvYqyMFMR4rs5pk6xG8O7id19l7PsfwdPQOS4PO5bxKErk0S5EPVHI68IkwxeXyRVmLZkwuzIbfQ== X-Received: by 2002:adf:a350:: with SMTP id d16mr12503364wrb.326.1569001241540; Fri, 20 Sep 2019 10:40:41 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH] hw/arm/boot.c: Set NSACR.{CP11,CP10} for NS kernel boots Date: Fri, 20 Sep 2019 18:40:39 +0100 Message-Id: <20190920174039.3916-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" If we're booting a Linux kernel directly into Non-Secure state on a CPU which has Secure state, then make sure we set the NSACR CP11 and CP10 bits, so that Non-Secure is allowed to access the FPU. Otherwise an AArch32 kernel will UNDEF as soon as it tries to use the FPU. It used to not matter that we didn't do this until commit fc1120a7f5f2d4b6, where we implemented actually honouring these NSACR bits. The problem only exists for CPUs where EL3 is AArch32; the equivalent AArch64 trap bits are in CPTR_EL3 and are "0 to not trap, 1 to trap", so the reset value of the register permits NS access, unlike NSACR. Fixes: fc1120a7f5 Fixes: https://bugs.launchpad.net/qemu/+bug/1844597 Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/arm/boot.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/arm/boot.c b/hw/arm/boot.c index bf97ef3e339..25422660545 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -754,6 +754,8 @@ static void do_cpu_reset(void *opaque) (cs !=3D first_cpu || !info->secure_board_setup)) { /* Linux expects non-secure state */ env->cp15.scr_el3 |=3D SCR_NS; + /* Set NSACR.{CP11,CP10} so NS can access the FPU */ + env->cp15.nsacr |=3D 3 << 10; } } =20 --=20 2.20.1