From nobody Fri May 3 08:51:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1568826985; cv=none; d=zoho.com; s=zohoarc; b=KoffnA0cc/q04MSWgm5527zNgUc/j+0SLQYDLwvXaKPZlCX+tw3OjAdxBhXJi9LfdU2j4s0tZFKo8U7pKmIGC9mbWxp6rb35tKzhS+IcOj/v11IE6rwhSzmcWsSBa60SC2ZnL8NFh0WCCaOgLeqygRDMIULlzAQnzcn9JpjnlFs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1568826985; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=1vVINMOzR9a6uGOP0uM0p93XfPe/nZxu/DkjhubMYHE=; b=cKSlw9O3ulUN6CqUy/dCgBZvw7rf1Cgy4MtqwMEQYkOT21ixizIIeaYAh0DpbCoZtZguDDLkK43NYGsIvo4Fso5VgVFXwaN2nFBaIipnTRjMSUs90Kuh1B9iAly0lWBFJlxHhsk3JLsHCY5wPv2JL26o8y3Uz5en8IBtIzIm1qk= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1568826985116718.1284681117662; Wed, 18 Sep 2019 10:16:25 -0700 (PDT) Received: from localhost ([::1]:33198 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iAdYz-0003g1-2Z for importer@patchew.org; Wed, 18 Sep 2019 13:16:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55396) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iAcTw-0002oT-11 for qemu-devel@nongnu.org; Wed, 18 Sep 2019 12:07:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iAcTu-0002ZH-Ln for qemu-devel@nongnu.org; Wed, 18 Sep 2019 12:07:03 -0400 Received: from 5.mo178.mail-out.ovh.net ([46.105.51.53]:42419) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iAcTu-0002YX-G8 for qemu-devel@nongnu.org; Wed, 18 Sep 2019 12:07:02 -0400 Received: from player799.ha.ovh.net (unknown [10.109.159.68]) by mo178.mail-out.ovh.net (Postfix) with ESMTP id 04D677951E for ; Wed, 18 Sep 2019 18:07:00 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player799.ha.ovh.net (Postfix) with ESMTPSA id B6E919F0E345; Wed, 18 Sep 2019 16:06:54 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 18 Sep 2019 18:06:21 +0200 Message-Id: <20190918160645.25126-2-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190918160645.25126-1-clg@kaod.org> References: <20190918160645.25126-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 6207086187017243622 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrudekgdeljecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.105.51.53 Subject: [Qemu-devel] [PATCH v4 01/25] ppc/xive: Introduce a XivePresenter interface X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Greg Kurz Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" When the XIVE IVRE sub-engine (XiveRouter) looks for a Notification Virtual Target (NVT) to notify, it broadcasts a message on the PowerBUS to find an XIVE IVPE sub-engine (Presenter) with the NVT dispatched on one of its HW threads, and then forwards the notification if any response was received. The current XIVE presenter model is sufficient for the pseries machine because it has a single interrupt controller device, but the PowerNV machine can have multiple chips each having its own interrupt controller. In this case, the XIVE presenter model is too simple and the CAM line matching should scan all chips of the system. To start fixing this issue, we first extend the XIVE Router model with a new XivePresenter QOM interface representing the XIVE IVPE sub-engine. This interface exposes a 'match_nvt' handler which the sPAPR and PowerNV XIVE Router models will need to implement to perform the CAM line matching. Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/xive.h | 32 ++++++++++++++++++++++++++++++++ hw/intc/xive.c | 26 +++++++++++++++++--------- 2 files changed, 49 insertions(+), 9 deletions(-) diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index 6d38755f8459..39de45b87cb9 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -367,6 +367,38 @@ int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nv= t_blk, uint32_t nvt_idx, XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs); void xive_router_notify(XiveNotifier *xn, uint32_t lisn); =20 +/* + * XIVE Presenter + */ + +typedef struct XiveTCTXMatch { + XiveTCTX *tctx; + uint8_t ring; +} XiveTCTXMatch; + +typedef struct XivePresenter XivePresenter; + +#define TYPE_XIVE_PRESENTER "xive-presenter" +#define XIVE_PRESENTER(obj) \ + INTERFACE_CHECK(XivePresenter, (obj), TYPE_XIVE_PRESENTER) +#define XIVE_PRESENTER_CLASS(klass) \ + OBJECT_CLASS_CHECK(XivePresenterClass, (klass), TYPE_XIVE_PRESENTER) +#define XIVE_PRESENTER_GET_CLASS(obj) \ + OBJECT_GET_CLASS(XivePresenterClass, (obj), TYPE_XIVE_PRESENTER) + +typedef struct XivePresenterClass { + InterfaceClass parent; + int (*match_nvt)(XivePresenter *xptr, uint8_t format, + uint8_t nvt_blk, uint32_t nvt_idx, + bool cam_ignore, uint8_t priority, + uint32_t logic_serv, XiveTCTXMatch *match); +} XivePresenterClass; + +int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx, + uint8_t format, + uint8_t nvt_blk, uint32_t nvt_idx, + bool cam_ignore, uint32_t logic_serv); + /* * XIVE END ESBs */ diff --git a/hw/intc/xive.c b/hw/intc/xive.c index b7417210d817..aa45ac2e06cb 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -1316,9 +1316,10 @@ static uint32_t xive_tctx_hw_cam_line(XiveTCTX *tctx) /* * The thread context register words are in big-endian format. */ -static int xive_presenter_tctx_match(XiveTCTX *tctx, uint8_t format, - uint8_t nvt_blk, uint32_t nvt_idx, - bool cam_ignore, uint32_t logic_serv) +int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx, + uint8_t format, + uint8_t nvt_blk, uint32_t nvt_idx, + bool cam_ignore, uint32_t logic_serv) { uint32_t cam =3D xive_nvt_cam_line(nvt_blk, nvt_idx); uint32_t qw3w2 =3D xive_tctx_word2(&tctx->regs[TM_QW3_HV_PHYS]); @@ -1375,11 +1376,6 @@ static int xive_presenter_tctx_match(XiveTCTX *tctx,= uint8_t format, return -1; } =20 -typedef struct XiveTCTXMatch { - XiveTCTX *tctx; - uint8_t ring; -} XiveTCTXMatch; - static bool xive_presenter_match(XiveRouter *xrtr, uint8_t format, uint8_t nvt_blk, uint32_t nvt_idx, bool cam_ignore, uint8_t priority, @@ -1405,7 +1401,8 @@ static bool xive_presenter_match(XiveRouter *xrtr, ui= nt8_t format, * Check the thread context CAM lines and record matches. We * will handle CPU exception delivery later */ - ring =3D xive_presenter_tctx_match(tctx, format, nvt_blk, nvt_idx, + ring =3D xive_presenter_tctx_match(XIVE_PRESENTER(xrtr), tctx, for= mat, + nvt_blk, nvt_idx, cam_ignore, logic_serv); /* * Save the context and follow on to catch duplicates, that we @@ -1692,6 +1689,7 @@ static const TypeInfo xive_router_info =3D { .class_init =3D xive_router_class_init, .interfaces =3D (InterfaceInfo[]) { { TYPE_XIVE_NOTIFIER }, + { TYPE_XIVE_PRESENTER }, { } } }; @@ -1863,10 +1861,20 @@ static const TypeInfo xive_notifier_info =3D { .class_size =3D sizeof(XiveNotifierClass), }; =20 +/* + * XIVE Presenter + */ +static const TypeInfo xive_presenter_info =3D { + .name =3D TYPE_XIVE_PRESENTER, + .parent =3D TYPE_INTERFACE, + .class_size =3D sizeof(XivePresenterClass), +}; + static void xive_register_types(void) { type_register_static(&xive_source_info); type_register_static(&xive_notifier_info); + type_register_static(&xive_presenter_info); type_register_static(&xive_router_info); type_register_static(&xive_end_source_info); type_register_static(&xive_tctx_info); --=20 2.21.0 From nobody Fri May 3 08:51:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1568825451; cv=none; d=zoho.com; s=zohoarc; b=J+FOfXkThZ0xMmwO46H0Ovf7wUVzAobZyNJf21ArrS0L3xXdV0wn2Bubd8PPgJw4CityNsZhR32lKOK84PXg89Y87hRYYG00wsVV1b3mGYhHr4N350l9R86/DShQRMmcilKigxu1BPnAKoqEeasI0WUTNSpNZYhLdnBco0CPvlI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1568825451; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; 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Wed, 18 Sep 2019 12:07:09 -0400 Received: from 5.mo2.mail-out.ovh.net ([87.98.181.248]:32989) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iAcU0-0002bD-8Q for qemu-devel@nongnu.org; Wed, 18 Sep 2019 12:07:08 -0400 Received: from player799.ha.ovh.net (unknown [10.108.35.185]) by mo2.mail-out.ovh.net (Postfix) with ESMTP id 916F21AD385 for ; Wed, 18 Sep 2019 18:07:06 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player799.ha.ovh.net (Postfix) with ESMTPSA id C2DBD9F0E37F; Wed, 18 Sep 2019 16:07:00 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 18 Sep 2019 18:06:22 +0200 Message-Id: <20190918160645.25126-3-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190918160645.25126-1-clg@kaod.org> References: <20190918160645.25126-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 6208775040059739110 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrudekgdeljecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 87.98.181.248 Subject: [Qemu-devel] [PATCH v4 02/25] ppc/xive: Implement the XivePresenter interface X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Greg Kurz Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Each XIVE Router model, sPAPR and PowerNV, now implements the 'match_nvt' handler of the XivePresenter QOM interface. This is simply moving code and taking into account the new API. To be noted that the xive_router_get_tctx() helper is not used anymore when doing CAM matching and will be removed later on after other changes. The XIVE presenter model is still too simple for the PowerNV machine and the CAM matching algo is not correct on multichip system. Subsequent patches will introduce more changes to scan all chips of the system. Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/pnv_xive.c | 41 +++++++++++++++++++++++++++++++++++++++++ hw/intc/spapr_xive.c | 41 +++++++++++++++++++++++++++++++++++++++++ hw/intc/xive.c | 43 +++++++------------------------------------ 3 files changed, 89 insertions(+), 36 deletions(-) diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index ed6e9d71bbfa..ae449aa1119b 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -392,6 +392,45 @@ static int pnv_xive_get_eas(XiveRouter *xrtr, uint8_t = blk, uint32_t idx, return pnv_xive_vst_read(xive, VST_TSEL_IVT, blk, idx, eas); } =20 +static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t format, + uint8_t nvt_blk, uint32_t nvt_idx, + bool cam_ignore, uint8_t priority, + uint32_t logic_serv, XiveTCTXMatch *match) +{ + CPUState *cs; + int count =3D 0; + + CPU_FOREACH(cs) { + PowerPCCPU *cpu =3D POWERPC_CPU(cs); + XiveTCTX *tctx =3D XIVE_TCTX(pnv_cpu_state(cpu)->intc); + int ring; + + /* + * Check the thread context CAM lines and record matches. + */ + ring =3D xive_presenter_tctx_match(xptr, tctx, format, nvt_blk, nv= t_idx, + cam_ignore, logic_serv); + /* + * Save the context and follow on to catch duplicates, that we + * don't support yet. + */ + if (ring !=3D -1) { + if (match->tctx) { + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a " + "thread context NVT %x/%x\n", + nvt_blk, nvt_idx); + return -1; + } + + match->ring =3D ring; + match->tctx =3D tctx; + count++; + } + } + + return count; +} + static XiveTCTX *pnv_xive_get_tctx(XiveRouter *xrtr, CPUState *cs) { PowerPCCPU *cpu =3D POWERPC_CPU(cs); @@ -1797,6 +1836,7 @@ static void pnv_xive_class_init(ObjectClass *klass, v= oid *data) PnvXScomInterfaceClass *xdc =3D PNV_XSCOM_INTERFACE_CLASS(klass); XiveRouterClass *xrc =3D XIVE_ROUTER_CLASS(klass); XiveNotifierClass *xnc =3D XIVE_NOTIFIER_CLASS(klass); + XivePresenterClass *xpc =3D XIVE_PRESENTER_CLASS(klass); =20 xdc->dt_xscom =3D pnv_xive_dt_xscom; =20 @@ -1812,6 +1852,7 @@ static void pnv_xive_class_init(ObjectClass *klass, v= oid *data) xrc->get_tctx =3D pnv_xive_get_tctx; =20 xnc->notify =3D pnv_xive_notify; + xpc->match_nvt =3D pnv_xive_match_nvt; }; =20 static const TypeInfo pnv_xive_info =3D { diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c index c1c97192a7d2..eefc0d4c36b9 100644 --- a/hw/intc/spapr_xive.c +++ b/hw/intc/spapr_xive.c @@ -422,6 +422,44 @@ static XiveTCTX *spapr_xive_get_tctx(XiveRouter *xrtr,= CPUState *cs) return spapr_cpu_state(cpu)->tctx; } =20 +static int spapr_xive_match_nvt(XivePresenter *xptr, uint8_t format, + uint8_t nvt_blk, uint32_t nvt_idx, + bool cam_ignore, uint8_t priority, + uint32_t logic_serv, XiveTCTXMatch *match) +{ + CPUState *cs; + int count =3D 0; + + CPU_FOREACH(cs) { + PowerPCCPU *cpu =3D POWERPC_CPU(cs); + XiveTCTX *tctx =3D spapr_cpu_state(cpu)->tctx; + int ring; + + /* + * Check the thread context CAM lines and record matches. + */ + ring =3D xive_presenter_tctx_match(xptr, tctx, format, nvt_blk, nv= t_idx, + cam_ignore, logic_serv); + /* + * Save the matching thread interrupt context and follow on to + * check for duplicates which are invalid. + */ + if (ring !=3D -1) { + if (match->tctx) { + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a thre= ad " + "context NVT %x/%x\n", nvt_blk, nvt_idx); + return -1; + } + + match->ring =3D ring; + match->tctx =3D tctx; + count++; + } + } + + return count; +} + static const VMStateDescription vmstate_spapr_xive_end =3D { .name =3D TYPE_SPAPR_XIVE "/end", .version_id =3D 1, @@ -499,6 +537,7 @@ static void spapr_xive_class_init(ObjectClass *klass, v= oid *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); XiveRouterClass *xrc =3D XIVE_ROUTER_CLASS(klass); + XivePresenterClass *xpc =3D XIVE_PRESENTER_CLASS(klass); =20 dc->desc =3D "sPAPR XIVE Interrupt Controller"; dc->props =3D spapr_xive_properties; @@ -511,6 +550,8 @@ static void spapr_xive_class_init(ObjectClass *klass, v= oid *data) xrc->get_nvt =3D spapr_xive_get_nvt; xrc->write_nvt =3D spapr_xive_write_nvt; xrc->get_tctx =3D spapr_xive_get_tctx; + + xpc->match_nvt =3D spapr_xive_match_nvt; } =20 static const TypeInfo spapr_xive_info =3D { diff --git a/hw/intc/xive.c b/hw/intc/xive.c index aa45ac2e06cb..fff50429f8ac 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -1381,43 +1381,14 @@ static bool xive_presenter_match(XiveRouter *xrtr, = uint8_t format, bool cam_ignore, uint8_t priority, uint32_t logic_serv, XiveTCTXMatch *match) { - CPUState *cs; + XivePresenter *xptr =3D XIVE_PRESENTER(xrtr); + XivePresenterClass *xpc =3D XIVE_PRESENTER_GET_CLASS(xptr); + int count; =20 - /* - * TODO (PowerNV): handle chip_id overwrite of block field for - * hardwired CAM compares - */ - - CPU_FOREACH(cs) { - XiveTCTX *tctx =3D xive_router_get_tctx(xrtr, cs); - int ring; - - /* - * HW checks that the CPU is enabled in the Physical Thread - * Enable Register (PTER). - */ - - /* - * Check the thread context CAM lines and record matches. We - * will handle CPU exception delivery later - */ - ring =3D xive_presenter_tctx_match(XIVE_PRESENTER(xrtr), tctx, for= mat, - nvt_blk, nvt_idx, - cam_ignore, logic_serv); - /* - * Save the context and follow on to catch duplicates, that we - * don't support yet. - */ - if (ring !=3D -1) { - if (match->tctx) { - qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a thre= ad " - "context NVT %x/%x\n", nvt_blk, nvt_idx); - return false; - } - - match->ring =3D ring; - match->tctx =3D tctx; - } + count =3D xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, + priority, logic_serv, match); + if (count < 0) { + return false; } =20 if (!match->tctx) { --=20 2.21.0 From nobody Fri May 3 08:51:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1568826796; cv=none; d=zoho.com; s=zohoarc; b=nLyBRhldZheBclU5GZhKkrSPDXrJP/i/p2NRgFaeSUBhXMzYAhh/x8+imqX7RncMvBMboZHH4G/XKj7wRrqUOsJ/pznogEcdE0/vZWHX6Iq7vXUKsVrykMfcUPPjRml9fpoNym+uitSGuLlDvPa6Zz68JMrOohnZhXQlo+Pfc7U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1568826796; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=NyS8WXi2InZlZMbp04hstuMjXTYP2UMxjPT6s2LiUN0=; b=R2rb0UiMD5aKMg5YJEnhnuQ6/XTI/5qxGAa4R8LEzbcQDkvH+WWTnxfTeOCv74a4thz2EnEZLg9SP9vTEuQNBrxxoMCAwXJAsQ9tP2C544lr7d4o57hQr0/TlOXbOCF9puVF/SrlM8Whk99NERZgsbgnEG2XsXsfYhZgByb3DaA= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 156882679601741.2530007714214; Wed, 18 Sep 2019 10:13:16 -0700 (PDT) Received: from localhost ([::1]:33156 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iAdVw-0000JD-FL for importer@patchew.org; Wed, 18 Sep 2019 13:13:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55454) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iAcU6-00033v-W6 for qemu-devel@nongnu.org; Wed, 18 Sep 2019 12:07:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iAcU5-0002dp-PO for qemu-devel@nongnu.org; Wed, 18 Sep 2019 12:07:14 -0400 Received: from 7.mo2.mail-out.ovh.net ([188.165.48.182]:56539) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iAcU5-0002dM-Jq for qemu-devel@nongnu.org; Wed, 18 Sep 2019 12:07:13 -0400 Received: from player799.ha.ovh.net (unknown [10.108.54.87]) by mo2.mail-out.ovh.net (Postfix) with ESMTP id 42AAC1AD3AC for ; Wed, 18 Sep 2019 18:07:12 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player799.ha.ovh.net (Postfix) with ESMTPSA id 4E7869F0E3C3; Wed, 18 Sep 2019 16:07:06 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 18 Sep 2019 18:06:23 +0200 Message-Id: <20190918160645.25126-4-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190918160645.25126-1-clg@kaod.org> References: <20190918160645.25126-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 6210463888279636966 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrudekgdeljecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 188.165.48.182 Subject: [Qemu-devel] [PATCH v4 03/25] ppc/pnv: Introduce a PNV_CHIP_CPU_FOREACH() helper X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Greg Kurz Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" As there is now easy way to loop on the CPUs belonging to a chip, add a helper to filter out external CPUs. Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/pnv_xive.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index ae449aa1119b..e1c15b6b5b71 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -392,15 +392,36 @@ static int pnv_xive_get_eas(XiveRouter *xrtr, uint8_t= blk, uint32_t idx, return pnv_xive_vst_read(xive, VST_TSEL_IVT, blk, idx, eas); } =20 +static int cpu_pir(PowerPCCPU *cpu) +{ + CPUPPCState *env =3D &cpu->env; + return env->spr_cb[SPR_PIR].default_value; +} + +static int cpu_chip_id(PowerPCCPU *cpu) +{ + int pir =3D cpu_pir(cpu); + return (pir >> 8) & 0x7f; +} + +#define PNV_CHIP_CPU_FOREACH(chip, cs) \ + CPU_FOREACH(cs) \ + if (chip->chip_id !=3D cpu_chip_id(POWERPC_CPU(cs))) {} else + static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t format, uint8_t nvt_blk, uint32_t nvt_idx, bool cam_ignore, uint8_t priority, uint32_t logic_serv, XiveTCTXMatch *match) { + PnvXive *xive =3D PNV_XIVE(xptr); CPUState *cs; int count =3D 0; =20 - CPU_FOREACH(cs) { + /* + * Loop on all CPUs of the machine and filter out the CPUs + * belonging to another chip. + */ + PNV_CHIP_CPU_FOREACH(xive->chip, cs) { PowerPCCPU *cpu =3D POWERPC_CPU(cs); XiveTCTX *tctx =3D XIVE_TCTX(pnv_cpu_state(cpu)->intc); int ring; --=20 2.21.0 From nobody Fri May 3 08:51:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1568827014; cv=none; d=zoho.com; s=zohoarc; b=X9mYSTm17vNABVSpkmHOb3L2Hyh5VKGfecjsEieKS1DqE7kO4wqUo5IfdN5O1oIf8+ZPpYeNkREfNSYwVJZ+xfG+E2pPmevPFDkUh1CuJHhUAabypdLiZcX/HodB1+6baSuojG0EjDcNXC2dKArXc3lZtM8jgvKXwgRqFwJYkKc= ARC-Message-Signature: i=1; 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Wed, 18 Sep 2019 13:16:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55476) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iAcUC-0003BB-8E for qemu-devel@nongnu.org; Wed, 18 Sep 2019 12:07:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iAcUB-0002hF-7s for qemu-devel@nongnu.org; Wed, 18 Sep 2019 12:07:20 -0400 Received: from 17.mo5.mail-out.ovh.net ([46.105.56.132]:50293) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iAcUB-0002gC-2O for qemu-devel@nongnu.org; Wed, 18 Sep 2019 12:07:19 -0400 Received: from player799.ha.ovh.net (unknown [10.109.143.201]) by mo5.mail-out.ovh.net (Postfix) with ESMTP id C57AF24EF87 for ; Wed, 18 Sep 2019 18:07:17 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player799.ha.ovh.net (Postfix) with ESMTPSA id 3CF3E9F0E44F; Wed, 18 Sep 2019 16:07:12 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 18 Sep 2019 18:06:24 +0200 Message-Id: <20190918160645.25126-5-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190918160645.25126-1-clg@kaod.org> References: <20190918160645.25126-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 6211871264849103846 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrudekgdeliecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.105.56.132 Subject: [Qemu-devel] [PATCH v4 04/25] ppc/pnv: Introduce a pnv_xive_is_cpu_enabled() helper X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Greg Kurz Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" and use this helper to exclude CPUs which were not enabled by the XIVE controller. Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: David Gibson --- hw/intc/pnv_xive.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index e1c15b6b5b71..5c97ccda1cad 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -408,6 +408,14 @@ static int cpu_chip_id(PowerPCCPU *cpu) CPU_FOREACH(cs) \ if (chip->chip_id !=3D cpu_chip_id(POWERPC_CPU(cs))) {} else =20 +static bool pnv_xive_is_cpu_enabled(PnvXive *xive, PowerPCCPU *cpu) +{ + int pir =3D cpu_pir(cpu); + int thrd_id =3D pir & 0x7f; + + return xive->regs[PC_THREAD_EN_REG0 >> 3] & PPC_BIT(thrd_id); +} + static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t format, uint8_t nvt_blk, uint32_t nvt_idx, bool cam_ignore, uint8_t priority, @@ -426,6 +434,10 @@ static int pnv_xive_match_nvt(XivePresenter *xptr, uin= t8_t format, XiveTCTX *tctx =3D XIVE_TCTX(pnv_cpu_state(cpu)->intc); int ring; =20 + if (!pnv_xive_is_cpu_enabled(xive, cpu)) { + continue; + } + /* * Check the thread context CAM lines and record matches. */ --=20 2.21.0 From nobody Fri May 3 08:51:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Wed, 18 Sep 2019 12:07:25 -0400 Received: from player799.ha.ovh.net (unknown [10.109.160.46]) by mo4.mail-out.ovh.net (Postfix) with ESMTP id E63A6207926 for ; Wed, 18 Sep 2019 18:07:23 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player799.ha.ovh.net (Postfix) with ESMTPSA id C96B49F0E4CD; Wed, 18 Sep 2019 16:07:17 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 18 Sep 2019 18:06:25 +0200 Message-Id: <20190918160645.25126-6-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190918160645.25126-1-clg@kaod.org> References: <20190918160645.25126-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 6213560114297998310 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrudekgdeljecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 188.165.36.253 Subject: [Qemu-devel] [PATCH v4 05/25] ppc/xive: Introduce a XiveFabric interface X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Greg Kurz Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The XiveFabric QOM interface should be implemented by the machine. It acts as the PowerBUS interface between the interrupt controller and the system. On HW, the XIVE sub-engine is responsible for the communication with the other chip is the Common Queue (CQ) bridge unit. This interface offers a 'match_nvt' handler to perform the CAM line matching when looking for a XIVE Presenter with a dispatched NVT. Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/xive.h | 22 ++++++++++++++++++++++ hw/intc/xive.c | 10 ++++++++++ 2 files changed, 32 insertions(+) diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index 39de45b87cb9..3c2910e10e25 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -399,6 +399,28 @@ int xive_presenter_tctx_match(XivePresenter *xptr, Xiv= eTCTX *tctx, uint8_t nvt_blk, uint32_t nvt_idx, bool cam_ignore, uint32_t logic_serv); =20 +/* + * XIVE Fabric (Interface between Interrupt Controller and Machine) + */ + +typedef struct XiveFabric XiveFabric; + +#define TYPE_XIVE_FABRIC "xive-fabric" +#define XIVE_FABRIC(obj) \ + INTERFACE_CHECK(XiveFabric, (obj), TYPE_XIVE_FABRIC) +#define XIVE_FABRIC_CLASS(klass) \ + OBJECT_CLASS_CHECK(XiveFabricClass, (klass), TYPE_XIVE_FABRIC) +#define XIVE_FABRIC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(XiveFabricClass, (obj), TYPE_XIVE_FABRIC) + +typedef struct XiveFabricClass { + InterfaceClass parent; + int (*match_nvt)(XiveFabric *xfb, uint8_t format, + uint8_t nvt_blk, uint32_t nvt_idx, + bool cam_ignore, uint8_t priority, + uint32_t logic_serv, XiveTCTXMatch *match); +} XiveFabricClass; + /* * XIVE END ESBs */ diff --git a/hw/intc/xive.c b/hw/intc/xive.c index fff50429f8ac..7a15a64ed7fe 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -1841,8 +1841,18 @@ static const TypeInfo xive_presenter_info =3D { .class_size =3D sizeof(XivePresenterClass), }; =20 +/* + * XIVE Fabric + */ +static const TypeInfo xive_fabric_info =3D { + .name =3D TYPE_XIVE_FABRIC, + .parent =3D TYPE_INTERFACE, + .class_size =3D sizeof(XiveFabricClass), +}; + static void xive_register_types(void) { + type_register_static(&xive_fabric_info); type_register_static(&xive_source_info); type_register_static(&xive_notifier_info); type_register_static(&xive_presenter_info); --=20 2.21.0 From nobody Fri May 3 08:51:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; 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Wed, 18 Sep 2019 16:07:23 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 18 Sep 2019 18:06:26 +0200 Message-Id: <20190918160645.25126-7-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190918160645.25126-1-clg@kaod.org> References: <20190918160645.25126-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 6215248964917955558 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrudekgdeliecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.105.36.149 Subject: [Qemu-devel] [PATCH v4 06/25] ppc/pnv: Implement the XiveFabric interface X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Greg Kurz Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The CAM line matching on the PowerNV machine now scans all chips of the system and all CPUs of a chip to find a dispatched NVT in the thread contexts. Signed-off-by: C=C3=A9dric Le Goater --- hw/ppc/pnv.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 77a86c6a2301..ca24dd62df23 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1378,6 +1378,35 @@ static void pnv_pic_print_info(InterruptStatsProvide= r *obj, } } =20 +static int pnv_xive_match_nvt(XiveFabric *xfb, uint8_t format, + uint8_t nvt_blk, uint32_t nvt_idx, + bool cam_ignore, uint8_t priority, + uint32_t logic_serv, + XiveTCTXMatch *match) +{ + PnvMachineState *pnv =3D PNV_MACHINE(xfb); + int total_count =3D 0; + int i; + + for (i =3D 0; i < pnv->num_chips; i++) { + Pnv9Chip *chip9 =3D PNV9_CHIP(pnv->chips[i]); + XivePresenter *xptr =3D XIVE_PRESENTER(&chip9->xive); + XivePresenterClass *xpc =3D XIVE_PRESENTER_GET_CLASS(xptr); + int count; + + count =3D xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignor= e, + priority, logic_serv, match); + + if (count < 0) { + return count; + } + + total_count +=3D count; + } + + return total_count; +} + static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { @@ -1441,9 +1470,11 @@ static void pnv_machine_power8_class_init(ObjectClas= s *oc, void *data) static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) { MachineClass *mc =3D MACHINE_CLASS(oc); + XiveFabricClass *xfc =3D XIVE_FABRIC_CLASS(oc); =20 mc->desc =3D "IBM PowerNV (Non-Virtualized) POWER9"; mc->default_cpu_type =3D POWERPC_CPU_TYPE_NAME("power9_v2.0"); + xfc->match_nvt =3D pnv_xive_match_nvt; =20 mc->alias =3D "powernv"; } @@ -1495,6 +1526,7 @@ static void pnv_machine_class_init(ObjectClass *oc, v= oid *data) .interfaces =3D (InterfaceInfo[]) { \ { TYPE_XICS_FABRIC }, \ { TYPE_INTERRUPT_STATS_PROVIDER }, \ + { TYPE_XIVE_FABRIC }, \ { }, \ }, \ } --=20 2.21.0 From nobody Fri May 3 08:51:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Wed, 18 Sep 2019 12:07:36 -0400 Received: from player799.ha.ovh.net (unknown [10.108.54.72]) by mo7.mail-out.ovh.net (Postfix) with ESMTP id AD0CC13378F for ; Wed, 18 Sep 2019 18:07:34 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player799.ha.ovh.net (Postfix) with ESMTPSA id 3F6E69F0E598; Wed, 18 Sep 2019 16:07:29 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 18 Sep 2019 18:06:27 +0200 Message-Id: <20190918160645.25126-8-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190918160645.25126-1-clg@kaod.org> References: <20190918160645.25126-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 6216656339133041638 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrudekgdeliecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.105.34.113 Subject: [Qemu-devel] [PATCH v4 07/25] ppc/spapr: Implement the XiveFabric interface X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Greg Kurz Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The CAM line matching sequence in the pseries machine does not change much apart from the use of the new QOM interfaces. There is an extra indirection because of the sPAPR IRQ backend of the machine. Only the XIVE backend implements the new 'match_nvt' handler. Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/spapr_irq.h | 6 ++++++ hw/ppc/spapr.c | 34 ++++++++++++++++++++++++++++++++++ hw/ppc/spapr_irq.c | 25 +++++++++++++++++++++++++ 3 files changed, 65 insertions(+) diff --git a/include/hw/ppc/spapr_irq.h b/include/hw/ppc/spapr_irq.h index 5db305165ce2..859780efaf95 100644 --- a/include/hw/ppc/spapr_irq.h +++ b/include/hw/ppc/spapr_irq.h @@ -31,6 +31,8 @@ int spapr_irq_msi_alloc(SpaprMachineState *spapr, uint32_= t num, bool align, Error **errp); void spapr_irq_msi_free(SpaprMachineState *spapr, int irq, uint32_t num); =20 +struct XiveTCTXMatch; + typedef struct SpaprIrq { uint32_t nr_irqs; uint32_t nr_msis; @@ -50,6 +52,10 @@ typedef struct SpaprIrq { void (*set_irq)(void *opaque, int srcno, int val); const char *(*get_nodename)(SpaprMachineState *spapr); void (*init_kvm)(SpaprMachineState *spapr, Error **errp); + int (*match_nvt)(SpaprMachineState *spapr, uint8_t format, + uint8_t nvt_blk, uint32_t nvt_idx, + bool cam_ignore, uint8_t priority, + uint32_t logic_serv, struct XiveTCTXMatch *match); } SpaprIrq; =20 extern SpaprIrq spapr_irq_xics; diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 2725b139a7f0..90f6f5fb9536 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -4360,6 +4360,37 @@ static void spapr_pic_print_info(InterruptStatsProvi= der *obj, kvm_irqchip_in_kernel() ? "in-kernel" : "emulated"); } =20 +static int spapr_xive_match_nvt(XiveFabric *xfb, uint8_t format, + uint8_t nvt_blk, uint32_t nvt_idx, + bool cam_ignore, uint8_t priority, + uint32_t logic_serv, XiveTCTXMatch *match) +{ + SpaprMachineState *spapr =3D SPAPR_MACHINE(xfb); + int count; + + count =3D spapr->irq->match_nvt(spapr, format, nvt_blk, nvt_idx, cam_i= gnore, + priority, logic_serv, match); + if (count < 0) { + return count; + } + + /* + * When we implement the save and restore of the thread interrupt + * contexts in the enter/exit CPU handlers of the machine and the + * escalations in QEMU, we should be able to handle non dispatched + * vCPUs. + * + * Until this is done, the sPAPR machine should find at least one + * matching context always. + */ + if (count =3D=3D 0) { + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is not dispatched\= n", + nvt_blk, nvt_idx); + } + + return count; +} + int spapr_get_vcpu_id(PowerPCCPU *cpu) { return cpu->vcpu_id; @@ -4456,6 +4487,7 @@ static void spapr_machine_class_init(ObjectClass *oc,= void *data) PPCVirtualHypervisorClass *vhc =3D PPC_VIRTUAL_HYPERVISOR_CLASS(oc); XICSFabricClass *xic =3D XICS_FABRIC_CLASS(oc); InterruptStatsProviderClass *ispc =3D INTERRUPT_STATS_PROVIDER_CLASS(o= c); + XiveFabricClass *xfc =3D XIVE_FABRIC_CLASS(oc); =20 mc->desc =3D "pSeries Logical Partition (PAPR compliant)"; mc->ignore_boot_device_suffixes =3D true; @@ -4514,6 +4546,7 @@ static void spapr_machine_class_init(ObjectClass *oc,= void *data) */ mc->numa_mem_align_shift =3D 28; mc->numa_mem_supported =3D true; + xfc->match_nvt =3D spapr_xive_match_nvt; =20 smc->default_caps.caps[SPAPR_CAP_HTM] =3D SPAPR_CAP_OFF; smc->default_caps.caps[SPAPR_CAP_VSX] =3D SPAPR_CAP_ON; @@ -4547,6 +4580,7 @@ static const TypeInfo spapr_machine_info =3D { { TYPE_PPC_VIRTUAL_HYPERVISOR }, { TYPE_XICS_FABRIC }, { TYPE_INTERRUPT_STATS_PROVIDER }, + { TYPE_XIVE_FABRIC }, { } }, }; diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c index d8f46b6797f8..8a6d79a59af2 100644 --- a/hw/ppc/spapr_irq.c +++ b/hw/ppc/spapr_irq.c @@ -257,6 +257,7 @@ SpaprIrq spapr_irq_xics =3D { .set_irq =3D spapr_irq_set_irq_xics, .get_nodename =3D spapr_irq_get_nodename_xics, .init_kvm =3D spapr_irq_init_kvm_xics, + .match_nvt =3D NULL, /* should not be used */ }; =20 /* @@ -406,6 +407,18 @@ static void spapr_irq_init_kvm_xive(SpaprMachineState = *spapr, Error **errp) } } =20 +static int spapr_irq_match_nvt_xive(SpaprMachineState *spapr, uint8_t form= at, + uint8_t nvt_blk, uint32_t nvt_idx, + bool cam_ignore, uint8_t priority, + uint32_t logic_serv, XiveTCTXMatch *ma= tch) +{ + XivePresenter *xptr =3D XIVE_PRESENTER(spapr->xive); + XivePresenterClass *xpc =3D XIVE_PRESENTER_GET_CLASS(xptr); + + return xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, + priority, logic_serv, match); +} + /* * XIVE uses the full IRQ number space. Set it to 8K to be compatible * with XICS. @@ -431,6 +444,7 @@ SpaprIrq spapr_irq_xive =3D { .set_irq =3D spapr_irq_set_irq_xive, .get_nodename =3D spapr_irq_get_nodename_xive, .init_kvm =3D spapr_irq_init_kvm_xive, + .match_nvt =3D spapr_irq_match_nvt_xive, }; =20 /* @@ -585,6 +599,15 @@ static const char *spapr_irq_get_nodename_dual(SpaprMa= chineState *spapr) return spapr_irq_current(spapr)->get_nodename(spapr); } =20 +static int spapr_irq_match_nvt_dual(SpaprMachineState *spapr, uint8_t form= at, + uint8_t nvt_blk, uint32_t nvt_idx, + bool cam_ignore, uint8_t priority, + uint32_t logic_serv, XiveTCTXMatch *ma= tch) +{ + return spapr_irq_current(spapr)->match_nvt(spapr, format, nvt_blk, nvt= _idx, + cam_ignore, priority, logic_serv, mat= ch); +} + /* * Define values in sync with the XIVE and XICS backend */ @@ -608,6 +631,7 @@ SpaprIrq spapr_irq_dual =3D { .set_irq =3D spapr_irq_set_irq_dual, .get_nodename =3D spapr_irq_get_nodename_dual, .init_kvm =3D NULL, /* should not be used */ + .match_nvt =3D spapr_irq_match_nvt_dual, }; =20 =20 @@ -825,4 +849,5 @@ SpaprIrq spapr_irq_xics_legacy =3D { .set_irq =3D spapr_irq_set_irq_xics, .get_nodename =3D spapr_irq_get_nodename_xics, .init_kvm =3D spapr_irq_init_kvm_xics, + .match_nvt =3D NULL, /* should not be used */ }; --=20 2.21.0 From nobody Fri May 3 08:51:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1568827635; cv=none; d=zoho.com; s=zohoarc; b=X5Rb9AXS63StckCBN+N/bboHcDDN9Z184I40gb/cV7RjWaAkgl6v9rkADvzasdH7hR03GKf0nob9TPcgzErR7Yny2Q82SWq9Zy8rWAdL7pM7Zsa/DbMD4IYV1Psnr3sWDW/PvDbFVSPVd350/RCDhFgCwflGAwNo8AivhOWXqJw= ARC-Message-Signature: i=1; a=rsa-sha256; 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Wed, 18 Sep 2019 13:27:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55604) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iAcUZ-0003ln-HG for qemu-devel@nongnu.org; Wed, 18 Sep 2019 12:07:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iAcUY-00033I-6e for qemu-devel@nongnu.org; Wed, 18 Sep 2019 12:07:43 -0400 Received: from 2.mo1.mail-out.ovh.net ([178.32.119.250]:51040) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iAcUY-000321-0c for qemu-devel@nongnu.org; Wed, 18 Sep 2019 12:07:42 -0400 Received: from player799.ha.ovh.net (unknown [10.109.160.11]) by mo1.mail-out.ovh.net (Postfix) with ESMTP id 330451901F4 for ; Wed, 18 Sep 2019 18:07:40 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player799.ha.ovh.net (Postfix) with ESMTPSA id A82B79F0E5EE; Wed, 18 Sep 2019 16:07:34 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 18 Sep 2019 18:06:28 +0200 Message-Id: <20190918160645.25126-9-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190918160645.25126-1-clg@kaod.org> References: <20190918160645.25126-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 6218345189355129830 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrudekgdeliecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 178.32.119.250 Subject: [Qemu-devel] [PATCH v4 08/25] ppc/xive: Use the XiveFabric and XivePresenter interfaces X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Greg Kurz Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Now that the machines have handlers implementing the XiveFabric and XivePresenter interfaces, remove xive_presenter_match() and make use of the 'match_nvt' handler of the machine. Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive.c | 48 +++++++++++++++++------------------------------- 1 file changed, 17 insertions(+), 31 deletions(-) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 7a15a64ed7fe..f951ad8cb08d 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -1376,30 +1376,6 @@ int xive_presenter_tctx_match(XivePresenter *xptr, X= iveTCTX *tctx, return -1; } =20 -static bool xive_presenter_match(XiveRouter *xrtr, uint8_t format, - uint8_t nvt_blk, uint32_t nvt_idx, - bool cam_ignore, uint8_t priority, - uint32_t logic_serv, XiveTCTXMatch *match) -{ - XivePresenter *xptr =3D XIVE_PRESENTER(xrtr); - XivePresenterClass *xpc =3D XIVE_PRESENTER_GET_CLASS(xptr); - int count; - - count =3D xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, - priority, logic_serv, match); - if (count < 0) { - return false; - } - - if (!match->tctx) { - qemu_log_mask(LOG_UNIMP, "XIVE: NVT %x/%x is not dispatched\n", - nvt_blk, nvt_idx); - return false; - } - - return true; -} - /* * This is our simple Xive Presenter Engine model. It is merged in the * Router as it does not require an extra object. @@ -1415,22 +1391,32 @@ static bool xive_presenter_match(XiveRouter *xrtr, = uint8_t format, * * The parameters represent what is sent on the PowerBus */ -static bool xive_presenter_notify(XiveRouter *xrtr, uint8_t format, +static bool xive_presenter_notify(uint8_t format, uint8_t nvt_blk, uint32_t nvt_idx, bool cam_ignore, uint8_t priority, uint32_t logic_serv) { + XiveFabric *xfb =3D XIVE_FABRIC(qdev_get_machine()); + XiveFabricClass *xfc =3D XIVE_FABRIC_GET_CLASS(xfb); XiveTCTXMatch match =3D { .tctx =3D NULL, .ring =3D 0 }; - bool found; + int count; =20 - found =3D xive_presenter_match(xrtr, format, nvt_blk, nvt_idx, cam_ign= ore, - priority, logic_serv, &match); - if (found) { + /* + * Ask the machine to scan the interrupt controllers for a match + */ + count =3D xfc->match_nvt(xfb, format, nvt_blk, nvt_idx, cam_ignore, + priority, logic_serv, &match); + if (count < 0) { + return false; + } + + /* handle CPU exception delivery */ + if (count) { ipb_update(&match.tctx->regs[match.ring], priority); xive_tctx_notify(match.tctx, match.ring); } =20 - return found; + return count; } =20 /* @@ -1543,7 +1529,7 @@ static void xive_router_end_notify(XiveRouter *xrtr, = uint8_t end_blk, return; } =20 - found =3D xive_presenter_notify(xrtr, format, nvt_blk, nvt_idx, + found =3D xive_presenter_notify(format, nvt_blk, nvt_idx, xive_get_field32(END_W7_F0_IGNORE, end.w7), priority, xive_get_field32(END_W7_F1_LOG_SERVER_ID, end.w7= )); --=20 2.21.0 From nobody Fri May 3 08:51:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1568827320; cv=none; d=zoho.com; s=zohoarc; b=JFbEMXqtvDEbOyVgGBPm3JUHBEvzqLhGn/bCVbHc/zYdPvoD0Vs4ZgwzJ+FTbDOfBSin2h1GQ+j9/oa+St3hEiC2E2+VKG+03HAYQWS6P4mIgXXEHPXGnqLHQNtGw6KcQwdRrDhnPkpXaWKBKdKoVYKEt/xaqbjUNl4MmYjMj7A= ARC-Message-Signature: i=1; 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Wed, 18 Sep 2019 13:21:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55634) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iAcUf-0003tA-2m for qemu-devel@nongnu.org; Wed, 18 Sep 2019 12:07:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iAcUd-00037b-DY for qemu-devel@nongnu.org; Wed, 18 Sep 2019 12:07:48 -0400 Received: from 8.mo3.mail-out.ovh.net ([87.98.172.249]:36773) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iAcUd-00036M-5D for qemu-devel@nongnu.org; Wed, 18 Sep 2019 12:07:47 -0400 Received: from player799.ha.ovh.net (unknown [10.109.143.208]) by mo3.mail-out.ovh.net (Postfix) with ESMTP id D0E4F2281BF for ; Wed, 18 Sep 2019 18:07:45 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player799.ha.ovh.net (Postfix) with ESMTPSA id 373599F0E637; Wed, 18 Sep 2019 16:07:40 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 18 Sep 2019 18:06:29 +0200 Message-Id: <20190918160645.25126-10-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190918160645.25126-1-clg@kaod.org> References: <20190918160645.25126-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 6219752560858860518 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrudekgdeljecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 87.98.172.249 Subject: [Qemu-devel] [PATCH v4 09/25] ppc/xive: Extend the TIMA operation with a XivePresenter parameter X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Greg Kurz Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The TIMA operations are performed on behalf of the XIVE IVPE sub-engine (Presenter) on the thread interrupt context registers. The current operations the model supports are simple and do not require access to the controller but more complex operations will need access to the controller NVT table and to its configuration. Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/xive.h | 7 +++--- hw/intc/pnv_xive.c | 4 +-- hw/intc/xive.c | 58 ++++++++++++++++++++++++------------------- 3 files changed, 38 insertions(+), 31 deletions(-) diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index 3c2910e10e25..536deea8c622 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -463,9 +463,10 @@ typedef struct XiveENDSource { #define XIVE_TM_USER_PAGE 0x3 =20 extern const MemoryRegionOps xive_tm_ops; -void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset, uint64_t value, - unsigned size); -uint64_t xive_tctx_tm_read(XiveTCTX *tctx, hwaddr offset, unsigned size); +void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, + uint64_t value, unsigned size); +uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCTX *tctx, hwaddr off= set, + unsigned size); =20 void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon); Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp); diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index 5c97ccda1cad..5c9483b394ab 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -1444,7 +1444,7 @@ static void xive_tm_indirect_write(void *opaque, hwad= dr offset, { XiveTCTX *tctx =3D pnv_xive_get_indirect_tctx(PNV_XIVE(opaque)); =20 - xive_tctx_tm_write(tctx, offset, value, size); + xive_tctx_tm_write(XIVE_PRESENTER(opaque), tctx, offset, value, size); } =20 static uint64_t xive_tm_indirect_read(void *opaque, hwaddr offset, @@ -1452,7 +1452,7 @@ static uint64_t xive_tm_indirect_read(void *opaque, h= waddr offset, { XiveTCTX *tctx =3D pnv_xive_get_indirect_tctx(PNV_XIVE(opaque)); =20 - return xive_tctx_tm_read(tctx, offset, size); + return xive_tctx_tm_read(XIVE_PRESENTER(opaque), tctx, offset, size); } =20 static const MemoryRegionOps xive_tm_indirect_ops =3D { diff --git a/hw/intc/xive.c b/hw/intc/xive.c index f951ad8cb08d..9bb09ed6ee7b 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -144,19 +144,20 @@ static inline uint32_t xive_tctx_word2(uint8_t *ring) * XIVE Thread Interrupt Management Area (TIMA) */ =20 -static void xive_tm_set_hv_cppr(XiveTCTX *tctx, hwaddr offset, - uint64_t value, unsigned size) +static void xive_tm_set_hv_cppr(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, uint64_t value, unsigned si= ze) { xive_tctx_set_cppr(tctx, TM_QW3_HV_PHYS, value & 0xff); } =20 -static uint64_t xive_tm_ack_hv_reg(XiveTCTX *tctx, hwaddr offset, unsigned= size) +static uint64_t xive_tm_ack_hv_reg(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, unsigned size) { return xive_tctx_accept(tctx, TM_QW3_HV_PHYS); } =20 -static uint64_t xive_tm_pull_pool_ctx(XiveTCTX *tctx, hwaddr offset, - unsigned size) +static uint64_t xive_tm_pull_pool_ctx(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, unsigned size) { uint32_t qw2w2_prev =3D xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); uint32_t qw2w2; @@ -166,13 +167,14 @@ static uint64_t xive_tm_pull_pool_ctx(XiveTCTX *tctx,= hwaddr offset, return qw2w2; } =20 -static void xive_tm_vt_push(XiveTCTX *tctx, hwaddr offset, +static void xive_tm_vt_push(XivePresenter *xptr, XiveTCTX *tctx, hwaddr of= fset, uint64_t value, unsigned size) { tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] =3D value & 0xff; } =20 -static uint64_t xive_tm_vt_poll(XiveTCTX *tctx, hwaddr offset, unsigned si= ze) +static uint64_t xive_tm_vt_poll(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, unsigned size) { return tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] & 0xff; } @@ -315,13 +317,14 @@ static uint64_t xive_tm_raw_read(XiveTCTX *tctx, hwad= dr offset, unsigned size) * state changes (side effects) in addition to setting/returning the * interrupt management area context of the processor thread. */ -static uint64_t xive_tm_ack_os_reg(XiveTCTX *tctx, hwaddr offset, unsigned= size) +static uint64_t xive_tm_ack_os_reg(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, unsigned size) { return xive_tctx_accept(tctx, TM_QW1_OS); } =20 -static void xive_tm_set_os_cppr(XiveTCTX *tctx, hwaddr offset, - uint64_t value, unsigned size) +static void xive_tm_set_os_cppr(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, uint64_t value, unsigned si= ze) { xive_tctx_set_cppr(tctx, TM_QW1_OS, value & 0xff); } @@ -330,15 +333,15 @@ static void xive_tm_set_os_cppr(XiveTCTX *tctx, hwadd= r offset, * Adjust the IPB to allow a CPU to process event queues of other * priorities during one physical interrupt cycle. */ -static void xive_tm_set_os_pending(XiveTCTX *tctx, hwaddr offset, - uint64_t value, unsigned size) +static void xive_tm_set_os_pending(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, uint64_t value, unsigned= size) { ipb_update(&tctx->regs[TM_QW1_OS], value & 0xff); xive_tctx_notify(tctx, TM_QW1_OS); } =20 -static uint64_t xive_tm_pull_os_ctx(XiveTCTX *tctx, hwaddr offset, - unsigned size) +static uint64_t xive_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, unsigned size) { uint32_t qw1w2_prev =3D xive_tctx_word2(&tctx->regs[TM_QW1_OS]); uint32_t qw1w2; @@ -356,9 +359,11 @@ typedef struct XiveTmOp { uint8_t page_offset; uint32_t op_offset; unsigned size; - void (*write_handler)(XiveTCTX *tctx, hwaddr offset, uint64_t valu= e, - unsigned size); - uint64_t (*read_handler)(XiveTCTX *tctx, hwaddr offset, unsigned size); + void (*write_handler)(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, + uint64_t value, unsigned size); + uint64_t (*read_handler)(XivePresenter *xptr, XiveTCTX *tctx, hwaddr o= ffset, + unsigned size); } XiveTmOp; =20 static const XiveTmOp xive_tm_operations[] =3D { @@ -404,8 +409,8 @@ static const XiveTmOp *xive_tm_find_op(hwaddr offset, u= nsigned size, bool write) /* * TIMA MMIO handlers */ -void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset, uint64_t value, - unsigned size) +void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, + uint64_t value, unsigned size) { const XiveTmOp *xto; =20 @@ -422,7 +427,7 @@ void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset, = uint64_t value, qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at = TIMA " "@%"HWADDR_PRIx"\n", offset); } else { - xto->write_handler(tctx, offset, value, size); + xto->write_handler(xptr, tctx, offset, value, size); } return; } @@ -432,7 +437,7 @@ void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset, = uint64_t value, */ xto =3D xive_tm_find_op(offset, size, true); if (xto) { - xto->write_handler(tctx, offset, value, size); + xto->write_handler(xptr, tctx, offset, value, size); return; } =20 @@ -442,7 +447,8 @@ void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset, = uint64_t value, xive_tm_raw_write(tctx, offset, value, size); } =20 -uint64_t xive_tctx_tm_read(XiveTCTX *tctx, hwaddr offset, unsigned size) +uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCTX *tctx, hwaddr off= set, + unsigned size) { const XiveTmOp *xto; =20 @@ -460,7 +466,7 @@ uint64_t xive_tctx_tm_read(XiveTCTX *tctx, hwaddr offse= t, unsigned size) "@%"HWADDR_PRIx"\n", offset); return -1; } - return xto->read_handler(tctx, offset, size); + return xto->read_handler(xptr, tctx, offset, size); } =20 /* @@ -468,7 +474,7 @@ uint64_t xive_tctx_tm_read(XiveTCTX *tctx, hwaddr offse= t, unsigned size) */ xto =3D xive_tm_find_op(offset, size, false); if (xto) { - return xto->read_handler(tctx, offset, size); + return xto->read_handler(xptr, tctx, offset, size); } =20 /* @@ -482,14 +488,14 @@ static void xive_tm_write(void *opaque, hwaddr offset, { XiveTCTX *tctx =3D xive_router_get_tctx(XIVE_ROUTER(opaque), current_c= pu); =20 - xive_tctx_tm_write(tctx, offset, value, size); + xive_tctx_tm_write(XIVE_PRESENTER(opaque), tctx, offset, value, size); } =20 static uint64_t xive_tm_read(void *opaque, hwaddr offset, unsigned size) { XiveTCTX *tctx =3D xive_router_get_tctx(XIVE_ROUTER(opaque), current_c= pu); =20 - return xive_tctx_tm_read(tctx, offset, size); + return xive_tctx_tm_read(XIVE_PRESENTER(opaque), tctx, offset, size); } =20 const MemoryRegionOps xive_tm_ops =3D { --=20 2.21.0 From nobody Fri May 3 08:51:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Wed, 18 Sep 2019 12:07:53 -0400 Received: from player799.ha.ovh.net (unknown [10.109.160.253]) by mo173.mail-out.ovh.net (Postfix) with ESMTP id 67D5C119FF0 for ; Wed, 18 Sep 2019 18:07:51 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player799.ha.ovh.net (Postfix) with ESMTPSA id CC2B39F0E68D; Wed, 18 Sep 2019 16:07:45 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 18 Sep 2019 18:06:30 +0200 Message-Id: <20190918160645.25126-11-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190918160645.25126-1-clg@kaod.org> References: <20190918160645.25126-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 6221441411813182438 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrudekgdeliecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 178.33.251.49 Subject: [Qemu-devel] [PATCH v4 10/25] ppc/pnv: Clarify how the TIMA is accessed on a multichip system X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Greg Kurz Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The TIMA MMIO space is shared among the chips. To identify the chip from which the access is being done, the PowerBUS uses a 'chip' field in the load/store messages. QEMU does not model these messages, instead, we extract the chip id from the CPU PIR and do a lookup at the machine level to fetch the targeted interrupt controller. Introduce pnv_get_chip() and pnv_xive_tm_get_xive() helpers to clarify this process in pnv_xive_get_tctx(). The latter will be removed in the subsequent patches but the same principle will be kept. Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/pnv.h | 13 +++++++++++++ hw/intc/pnv_xive.c | 40 +++++++++++++++++++++++----------------- 2 files changed, 36 insertions(+), 17 deletions(-) diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 1cdbe55bf86c..5e01a9f3df95 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -185,6 +185,19 @@ static inline bool pnv_is_power9(PnvMachineState *pnv) return pnv_chip_is_power9(pnv->chips[0]); } =20 +static inline PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id) +{ + int i; + + for (i =3D 0; i < pnv->num_chips; i++) { + PnvChip *chip =3D pnv->chips[i]; + if (chip->chip_id =3D=3D chip_id) { + return chip; + } + } + return NULL; +} + #define PNV_FDT_ADDR 0x01000000 #define PNV_TIMEBASE_FREQ 512000000ULL =20 diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index 5c9483b394ab..3d6fcf9ac139 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -464,31 +464,37 @@ static int pnv_xive_match_nvt(XivePresenter *xptr, ui= nt8_t format, return count; } =20 +/* + * The TIMA MMIO space is shared among the chips and to identify the + * chip from which the access is being done, we extract the chip id + * from the PIR. + */ +static PnvXive *pnv_xive_tm_get_xive(PowerPCCPU *cpu) +{ + PnvMachineState *pnv =3D PNV_MACHINE(qdev_get_machine()); + PnvChip *chip; + PnvXive *xive; + + chip =3D pnv_get_chip(pnv, cpu_chip_id(cpu)); + assert(chip); + xive =3D &PNV9_CHIP(chip)->xive; + + if (!pnv_xive_is_cpu_enabled(xive, cpu)) { + xive_error(xive, "IC: CPU %x is not enabled", cpu_pir(cpu)); + } + return xive; +} + static XiveTCTX *pnv_xive_get_tctx(XiveRouter *xrtr, CPUState *cs) { PowerPCCPU *cpu =3D POWERPC_CPU(cs); - XiveTCTX *tctx =3D XIVE_TCTX(pnv_cpu_state(cpu)->intc); - PnvXive *xive =3D NULL; - CPUPPCState *env =3D &cpu->env; - int pir =3D env->spr_cb[SPR_PIR].default_value; + PnvXive *xive =3D pnv_xive_tm_get_xive(cpu); =20 - /* - * Perform an extra check on the HW thread enablement. - * - * The TIMA is shared among the chips and to identify the chip - * from which the access is being done, we extract the chip id - * from the PIR. - */ - xive =3D pnv_xive_get_ic((pir >> 8) & 0xf); if (!xive) { return NULL; } =20 - if (!(xive->regs[PC_THREAD_EN_REG0 >> 3] & PPC_BIT(pir & 0x3f))) { - xive_error(PNV_XIVE(xrtr), "IC: CPU %x is not enabled", pir); - } - - return tctx; + return XIVE_TCTX(pnv_cpu_state(cpu)->intc); } =20 /* --=20 2.21.0 From nobody Fri May 3 08:51:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1568827837; cv=none; d=zoho.com; s=zohoarc; b=EhimEXsL+QXnfbOjufdRqh0iLVCYjd4A65JhMWMQvD29c+UYPMu1+aRPGCQtcyVv9Sp9CfngzTdpV+ysCtJawMx4RtDXSrOdhgxEowI/xQOUUbhqMVSISFnosAjlQWEQqroLqlrAcN9c+J+BAflaOx7a+dc+gL9Zu7Cg848o+wg= ARC-Message-Signature: i=1; a=rsa-sha256; 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charset="utf-8" This also removes the need of the get_tctx() XiveRouter handler in the core XIVE framework. Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/xive.h | 1 - hw/intc/pnv_xive.c | 35 ++++++++++++++++++++++++++++++++++- hw/intc/spapr_xive.c | 33 +++++++++++++++++++++++++++++++-- hw/intc/xive.c | 29 ----------------------------- 4 files changed, 65 insertions(+), 33 deletions(-) diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index 536deea8c622..9d9cd88dd17e 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -462,7 +462,6 @@ typedef struct XiveENDSource { #define XIVE_TM_OS_PAGE 0x2 #define XIVE_TM_USER_PAGE 0x3 =20 -extern const MemoryRegionOps xive_tm_ops; void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, uint64_t value, unsigned size); uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCTX *tctx, hwaddr off= set, diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index 3d6fcf9ac139..40e18fb44811 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -1475,6 +1475,39 @@ static const MemoryRegionOps xive_tm_indirect_ops = =3D { }, }; =20 +static void pnv_xive_tm_write(void *opaque, hwaddr offset, + uint64_t value, unsigned size) +{ + PowerPCCPU *cpu =3D POWERPC_CPU(current_cpu); + PnvXive *xive =3D pnv_xive_tm_get_xive(cpu); + XiveTCTX *tctx =3D XIVE_TCTX(pnv_cpu_state(cpu)->intc); + + xive_tctx_tm_write(XIVE_PRESENTER(xive), tctx, offset, value, size); +} + +static uint64_t pnv_xive_tm_read(void *opaque, hwaddr offset, unsigned siz= e) +{ + PowerPCCPU *cpu =3D POWERPC_CPU(current_cpu); + PnvXive *xive =3D pnv_xive_tm_get_xive(cpu); + XiveTCTX *tctx =3D XIVE_TCTX(pnv_cpu_state(cpu)->intc); + + return xive_tctx_tm_read(XIVE_PRESENTER(xive), tctx, offset, size); +} + +const MemoryRegionOps pnv_xive_tm_ops =3D { + .read =3D pnv_xive_tm_read, + .write =3D pnv_xive_tm_write, + .endianness =3D DEVICE_BIG_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 8, + }, + .impl =3D { + .min_access_size =3D 1, + .max_access_size =3D 8, + }, +}; + /* * Interrupt controller XSCOM region. */ @@ -1832,7 +1865,7 @@ static void pnv_xive_realize(DeviceState *dev, Error = **errp) "xive-pc", PNV9_XIVE_PC_SIZE); =20 /* Thread Interrupt Management Area (Direct) */ - memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &xive_tm_ops, + memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &pnv_xive_tm_ops, xive, "xive-tima", PNV9_XIVE_TM_SIZE); =20 qemu_register_reset(pnv_xive_reset, dev); diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c index eefc0d4c36b9..e00a9bdd901b 100644 --- a/hw/intc/spapr_xive.c +++ b/hw/intc/spapr_xive.c @@ -222,6 +222,35 @@ void spapr_xive_set_tctx_os_cam(XiveTCTX *tctx) memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &nvt_cam, 4); } =20 +static void spapr_xive_tm_write(void *opaque, hwaddr offset, + uint64_t value, unsigned size) +{ + XiveTCTX *tctx =3D spapr_cpu_state(POWERPC_CPU(current_cpu))->tctx; + + xive_tctx_tm_write(XIVE_PRESENTER(opaque), tctx, offset, value, size); +} + +static uint64_t spapr_xive_tm_read(void *opaque, hwaddr offset, unsigned s= ize) +{ + XiveTCTX *tctx =3D spapr_cpu_state(POWERPC_CPU(current_cpu))->tctx; + + return xive_tctx_tm_read(XIVE_PRESENTER(opaque), tctx, offset, size); +} + +const MemoryRegionOps spapr_xive_tm_ops =3D { + .read =3D spapr_xive_tm_read, + .write =3D spapr_xive_tm_write, + .endianness =3D DEVICE_BIG_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 8, + }, + .impl =3D { + .min_access_size =3D 1, + .max_access_size =3D 8, + }, +}; + static void spapr_xive_end_reset(XiveEND *end) { memset(end, 0, sizeof(*end)); @@ -331,8 +360,8 @@ static void spapr_xive_realize(DeviceState *dev, Error = **errp) qemu_register_reset(spapr_xive_reset, dev); =20 /* TIMA initialization */ - memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &xive_tm_ops, xive, - "xive.tima", 4ull << TM_SHIFT); + memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &spapr_xive_tm_ops, + xive, "xive.tima", 4ull << TM_SHIFT); sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xive->tm_mmio); =20 /* diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 9bb09ed6ee7b..11432f04f5c3 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -483,35 +483,6 @@ uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTC= TX *tctx, hwaddr offset, return xive_tm_raw_read(tctx, offset, size); } =20 -static void xive_tm_write(void *opaque, hwaddr offset, - uint64_t value, unsigned size) -{ - XiveTCTX *tctx =3D xive_router_get_tctx(XIVE_ROUTER(opaque), current_c= pu); - - xive_tctx_tm_write(XIVE_PRESENTER(opaque), tctx, offset, value, size); -} - -static uint64_t xive_tm_read(void *opaque, hwaddr offset, unsigned size) -{ - XiveTCTX *tctx =3D xive_router_get_tctx(XIVE_ROUTER(opaque), current_c= pu); - - return xive_tctx_tm_read(XIVE_PRESENTER(opaque), tctx, offset, size); -} - -const MemoryRegionOps xive_tm_ops =3D { - .read =3D xive_tm_read, - .write =3D xive_tm_write, - .endianness =3D DEVICE_BIG_ENDIAN, - .valid =3D { - .min_access_size =3D 1, - .max_access_size =3D 8, - }, - .impl =3D { - .min_access_size =3D 1, - .max_access_size =3D 8, - }, -}; - static char *xive_tctx_ring_print(uint8_t *ring) { uint32_t w2 =3D xive_tctx_word2(ring); --=20 2.21.0 From nobody Fri May 3 08:51:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Wed, 18 Sep 2019 12:08:04 -0400 Received: from player799.ha.ovh.net (unknown [10.109.146.76]) by mo7.mail-out.ovh.net (Postfix) with ESMTP id B18D6131337 for ; Wed, 18 Sep 2019 18:08:02 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player799.ha.ovh.net (Postfix) with ESMTPSA id B788F9F0E715; Wed, 18 Sep 2019 16:07:56 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 18 Sep 2019 18:06:32 +0200 Message-Id: <20190918160645.25126-13-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190918160645.25126-1-clg@kaod.org> References: <20190918160645.25126-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 6224537639010339814 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrudekgdeliecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 178.32.122.254 Subject: [Qemu-devel] [PATCH v4 12/25] ppc/xive: Remove the get_tctx() XiveRouter handler X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Greg Kurz Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/xive.h | 2 -- hw/intc/pnv_xive.c | 13 ------------- hw/intc/spapr_xive.c | 8 -------- hw/intc/xive.c | 7 ------- 4 files changed, 30 deletions(-) diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index 9d9cd88dd17e..f35ff3b64791 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -351,7 +351,6 @@ typedef struct XiveRouterClass { XiveNVT *nvt); int (*write_nvt)(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, XiveNVT *nvt, uint8_t word_number); - XiveTCTX *(*get_tctx)(XiveRouter *xrtr, CPUState *cs); } XiveRouterClass; =20 int xive_router_get_eas(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_id= x, @@ -364,7 +363,6 @@ int xive_router_get_nvt(XiveRouter *xrtr, uint8_t nvt_b= lk, uint32_t nvt_idx, XiveNVT *nvt); int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_= idx, XiveNVT *nvt, uint8_t word_number); -XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs); void xive_router_notify(XiveNotifier *xn, uint32_t lisn); =20 /* diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index 40e18fb44811..74d6ccbea3d6 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -485,18 +485,6 @@ static PnvXive *pnv_xive_tm_get_xive(PowerPCCPU *cpu) return xive; } =20 -static XiveTCTX *pnv_xive_get_tctx(XiveRouter *xrtr, CPUState *cs) -{ - PowerPCCPU *cpu =3D POWERPC_CPU(cs); - PnvXive *xive =3D pnv_xive_tm_get_xive(cpu); - - if (!xive) { - return NULL; - } - - return XIVE_TCTX(pnv_cpu_state(cpu)->intc); -} - /* * The internal sources (IPIs) of the interrupt controller have no * knowledge of the XIVE chip on which they reside. Encode the block @@ -1921,7 +1909,6 @@ static void pnv_xive_class_init(ObjectClass *klass, v= oid *data) xrc->write_end =3D pnv_xive_write_end; xrc->get_nvt =3D pnv_xive_get_nvt; xrc->write_nvt =3D pnv_xive_write_nvt; - xrc->get_tctx =3D pnv_xive_get_tctx; =20 xnc->notify =3D pnv_xive_notify; xpc->match_nvt =3D pnv_xive_match_nvt; diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c index e00a9bdd901b..864f50167c65 100644 --- a/hw/intc/spapr_xive.c +++ b/hw/intc/spapr_xive.c @@ -444,13 +444,6 @@ static int spapr_xive_write_nvt(XiveRouter *xrtr, uint= 8_t nvt_blk, g_assert_not_reached(); } =20 -static XiveTCTX *spapr_xive_get_tctx(XiveRouter *xrtr, CPUState *cs) -{ - PowerPCCPU *cpu =3D POWERPC_CPU(cs); - - return spapr_cpu_state(cpu)->tctx; -} - static int spapr_xive_match_nvt(XivePresenter *xptr, uint8_t format, uint8_t nvt_blk, uint32_t nvt_idx, bool cam_ignore, uint8_t priority, @@ -578,7 +571,6 @@ static void spapr_xive_class_init(ObjectClass *klass, v= oid *data) xrc->write_end =3D spapr_xive_write_end; xrc->get_nvt =3D spapr_xive_get_nvt; xrc->write_nvt =3D spapr_xive_write_nvt; - xrc->get_tctx =3D spapr_xive_get_tctx; =20 xpc->match_nvt =3D spapr_xive_match_nvt; } diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 11432f04f5c3..68d3361d1c3f 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -1270,13 +1270,6 @@ int xive_router_write_nvt(XiveRouter *xrtr, uint8_t = nvt_blk, uint32_t nvt_idx, return xrc->write_nvt(xrtr, nvt_blk, nvt_idx, nvt, word_number); } =20 -XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs) -{ - XiveRouterClass *xrc =3D XIVE_ROUTER_GET_CLASS(xrtr); - - return xrc->get_tctx(xrtr, cs); -} - /* * Encode the HW CAM line in the block group mode format : * --=20 2.21.0 From nobody Fri May 3 08:51:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; 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Wed, 18 Sep 2019 16:08:02 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 18 Sep 2019 18:06:33 +0200 Message-Id: <20190918160645.25126-14-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190918160645.25126-1-clg@kaod.org> References: <20190918160645.25126-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 6226226486908324838 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrudekgdeliecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 178.33.109.80 Subject: [Qemu-devel] [PATCH v4 13/25] ppc/xive: Introduce a xive_tctx_ipb_update() helper X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Greg Kurz Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" We will use it to resend missed interrupts when a vCPU context is pushed a HW thread. Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/xive.h | 1 + hw/intc/xive.c | 15 +++++++++++---- 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index f35ff3b64791..a461753f5da5 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -467,6 +467,7 @@ uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCT= X *tctx, hwaddr offset, =20 void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon); Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp); +void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring, uint8_t ipb); =20 static inline uint32_t xive_nvt_cam_line(uint8_t nvt_blk, uint32_t nvt_idx) { diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 68d3361d1c3f..5f7c37b091a7 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -135,6 +135,15 @@ static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t= ring, uint8_t cppr) xive_tctx_notify(tctx, ring); } =20 +void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring, uint8_t ipb) +{ + uint8_t *regs =3D &tctx->regs[ring]; + + regs[TM_IPB] |=3D ipb; + regs[TM_PIPR] =3D ipb_to_pipr(regs[TM_IPB]); + xive_tctx_notify(tctx, ring); +} + static inline uint32_t xive_tctx_word2(uint8_t *ring) { return *((uint32_t *) &ring[TM_WORD2]); @@ -336,8 +345,7 @@ static void xive_tm_set_os_cppr(XivePresenter *xptr, Xi= veTCTX *tctx, static void xive_tm_set_os_pending(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, uint64_t value, unsigned= size) { - ipb_update(&tctx->regs[TM_QW1_OS], value & 0xff); - xive_tctx_notify(tctx, TM_QW1_OS); + xive_tctx_ipb_update(tctx, TM_QW1_OS, priority_to_ipb(value & 0xff)); } =20 static uint64_t xive_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, @@ -1382,8 +1390,7 @@ static bool xive_presenter_notify(uint8_t format, =20 /* handle CPU exception delivery */ if (count) { - ipb_update(&match.tctx->regs[match.ring], priority); - xive_tctx_notify(match.tctx, match.ring); + xive_tctx_ipb_update(match.tctx, match.ring, priority_to_ipb(prior= ity)); } =20 return count; --=20 2.21.0 From nobody Fri May 3 08:51:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Wed, 18 Sep 2019 12:08:15 -0400 Received: from player799.ha.ovh.net (unknown [10.108.54.74]) by mo178.mail-out.ovh.net (Postfix) with ESMTP id A442D793D6 for ; Wed, 18 Sep 2019 18:08:13 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player799.ha.ovh.net (Postfix) with ESMTPSA id 1B65C9F0E7A3; Wed, 18 Sep 2019 16:08:08 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 18 Sep 2019 18:06:34 +0200 Message-Id: <20190918160645.25126-15-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190918160645.25126-1-clg@kaod.org> References: <20190918160645.25126-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 6227633862887771110 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrudekgdeljecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.105.53.132 Subject: [Qemu-devel] [PATCH v4 14/25] ppc/xive: Introduce helpers for the NVT id X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Greg Kurz Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The NVT space is 19 bits wide, giving a maximum of 512K per chip. When dispatched on a HW thread, the NVT identifier of a vCPU is pushed/stored in the CAM line (word2) of the thread interrupt context. Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/xive.h | 5 ----- include/hw/ppc/xive_regs.h | 21 +++++++++++++++++++++ 2 files changed, 21 insertions(+), 5 deletions(-) diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index a461753f5da5..794dfcaae0f8 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -469,11 +469,6 @@ void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor = *mon); Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp); void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring, uint8_t ipb); =20 -static inline uint32_t xive_nvt_cam_line(uint8_t nvt_blk, uint32_t nvt_idx) -{ - return (nvt_blk << 19) | nvt_idx; -} - /* * KVM XIVE device helpers */ diff --git a/include/hw/ppc/xive_regs.h b/include/hw/ppc/xive_regs.h index 08c8bf7172e2..3d7b6fd09664 100644 --- a/include/hw/ppc/xive_regs.h +++ b/include/hw/ppc/xive_regs.h @@ -251,4 +251,25 @@ typedef struct XiveNVT { =20 #define xive_nvt_is_valid(nvt) (be32_to_cpu((nvt)->w0) & NVT_W0_VALID) =20 +/* + * The VP number space in a block is defined by the END_W6_NVT_INDEX + * field of the XIVE END + */ +#define XIVE_NVT_SHIFT 19 + +static inline uint32_t xive_nvt_cam_line(uint8_t nvt_blk, uint32_t nvt_idx) +{ + return (nvt_blk << XIVE_NVT_SHIFT) | nvt_idx; +} + +static inline uint32_t xive_nvt_idx(uint32_t cam_line) +{ + return cam_line & ((1 << XIVE_NVT_SHIFT) - 1); +} + +static inline uint32_t xive_nvt_blk(uint32_t cam_line) +{ + return (cam_line >> XIVE_NVT_SHIFT) & 0xf; +} + #endif /* PPC_XIVE_REGS_H */ --=20 2.21.0 From nobody Fri May 3 08:51:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1568828198; cv=none; d=zoho.com; s=zohoarc; b=jnz7fw+fCxu5UrcbyCopd+FlwPtLM9MAGQ7bvhKbLv9tJqBgNaTCID007BuJ5awaZdClwc6njAPz9qud+svZVTRcQT0s46MRK0dG6s/w6FxdqAXMYHVideoIY7RvUlBqkR/oYR+an6DoU3UlHqUUC3Dq8jTSTdUvwUNOUalWhEQ= ARC-Message-Signature: i=1; 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Wed, 18 Sep 2019 13:36:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55864) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iAcVB-0004Zy-S1 for qemu-devel@nongnu.org; Wed, 18 Sep 2019 12:08:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iAcVA-0003Yv-IV for qemu-devel@nongnu.org; Wed, 18 Sep 2019 12:08:21 -0400 Received: from 10.mo7.mail-out.ovh.net ([178.33.250.56]:46025) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iAcVA-0003YB-Bn for qemu-devel@nongnu.org; Wed, 18 Sep 2019 12:08:20 -0400 Received: from player799.ha.ovh.net (unknown [10.109.160.217]) by mo7.mail-out.ovh.net (Postfix) with ESMTP id 0FEE71314B0 for ; Wed, 18 Sep 2019 18:08:19 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player799.ha.ovh.net (Postfix) with ESMTPSA id 9A3599F0E7E4; Wed, 18 Sep 2019 16:08:13 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 18 Sep 2019 18:06:35 +0200 Message-Id: <20190918160645.25126-16-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190918160645.25126-1-clg@kaod.org> References: <20190918160645.25126-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 6229322710203075558 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrudekgdeliecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 178.33.250.56 Subject: [Qemu-devel] [PATCH v4 15/25] ppc/xive: Synthesize interrupt from the saved IPB in the NVT X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Greg Kurz Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" When an interrupt can not be presented to a vCPU, the XIVE presenter updates the Interrupt Pending Buffer of the XIVE NVT if backlog is activated in the END. Later, when the same vCPU is dispatched, its context is pushed in the thread context registers and the VO bit is set in the CAM line word to activate the context. The HW grabs the associated NVT to pull the pending bits, and merges them with the IPB of the TIMA. If interrupts were missed while the vCPU was not dispatched, these are synthesized in this sequence. Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/xive_regs.h | 1 + hw/intc/xive.c | 67 +++++++++++++++++++++++++++++++++----- 2 files changed, 60 insertions(+), 8 deletions(-) diff --git a/include/hw/ppc/xive_regs.h b/include/hw/ppc/xive_regs.h index 3d7b6fd09664..dea0318e7e89 100644 --- a/include/hw/ppc/xive_regs.h +++ b/include/hw/ppc/xive_regs.h @@ -235,6 +235,7 @@ typedef struct XiveNVT { uint32_t w2; uint32_t w3; uint32_t w4; +#define NVT_W4_IPB PPC_BITMASK32(16, 23) uint32_t w5; uint32_t w6; uint32_t w7; diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 5f7c37b091a7..f47b0cf2b053 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -47,12 +47,6 @@ static uint8_t ipb_to_pipr(uint8_t ibp) return ibp ? clz32((uint32_t)ibp << 24) : 0xff; } =20 -static void ipb_update(uint8_t *regs, uint8_t priority) -{ - regs[TM_IPB] |=3D priority_to_ipb(priority); - regs[TM_PIPR] =3D ipb_to_pipr(regs[TM_IPB]); -} - static uint8_t exception_mask(uint8_t ring) { switch (ring) { @@ -359,6 +353,55 @@ static uint64_t xive_tm_pull_os_ctx(XivePresenter *xpt= r, XiveTCTX *tctx, return qw1w2; } =20 +static void xive_tctx_need_resend(XiveRouter *xrtr, XiveTCTX *tctx, + uint8_t nvt_blk, uint32_t nvt_idx) +{ + XiveNVT nvt; + uint8_t ipb; + + /* + * Grab the associated NVT to pull the pending bits, and merge + * them with the IPB of the thread interrupt context registers + */ + if (xive_router_get_nvt(xrtr, nvt_blk, nvt_idx, &nvt)) { + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVT %x/%x\n", + nvt_blk, nvt_idx); + return; + } + + ipb =3D xive_get_field32(NVT_W4_IPB, nvt.w4); + + if (ipb) { + /* Reset the NVT value */ + nvt.w4 =3D xive_set_field32(NVT_W4_IPB, nvt.w4, 0); + xive_router_write_nvt(xrtr, nvt_blk, nvt_idx, &nvt, 4); + + /* Merge in current context */ + xive_tctx_ipb_update(tctx, TM_QW1_OS, ipb); + } +} + +/* + * Updating the OS CAM line can trigger a resend of interrupt + */ +static void xive_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, uint64_t value, unsigned si= ze) +{ + uint32_t qw1w2 =3D value; + uint8_t nvt_blk =3D xive_nvt_blk(qw1w2); + uint32_t nvt_idx =3D xive_nvt_idx(qw1w2); + bool vo =3D !!(qw1w2 & TM_QW1W2_VO); + + /* First update the registers */ + qw1w2 =3D cpu_to_be32(qw1w2); + memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); + + /* Check the interrupt pending bits */ + if (vo) { + xive_tctx_need_resend(XIVE_ROUTER(xptr), tctx, nvt_blk, nvt_idx); + } +} + /* * Define a mapping of "special" operations depending on the TIMA page * offset and the size of the operation. @@ -380,6 +423,7 @@ static const XiveTmOp xive_tm_operations[] =3D { * effects */ { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_CPPR, 1, xive_tm_set_os_cppr, NULL= }, + { XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2, 4, xive_tm_push_os_ctx, N= ULL }, { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, xive_tm_set_hv_cppr, N= ULL }, { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, xive_tm_vt_push, NULL= }, { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, NULL, xive_tm_vt_poll= }, @@ -1523,14 +1567,21 @@ static void xive_router_end_notify(XiveRouter *xrtr= , uint8_t end_blk, * - logical server : forward request to IVPE (not supported) */ if (xive_end_is_backlog(&end)) { + uint8_t ipb; + if (format =3D=3D 1) { qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x invalid config: F1 & backlog\n", end_blk, end_idx); return; } - /* Record the IPB in the associated NVT structure */ - ipb_update((uint8_t *) &nvt.w4, priority); + /* + * Record the IPB in the associated NVT structure for later + * use. The presenter will resend the interrupt when the vCPU + * is dispatched again on a HW thread. + */ + ipb =3D xive_get_field32(NVT_W4_IPB, nvt.w4) | priority_to_ipb(pri= ority); + nvt.w4 =3D xive_set_field32(NVT_W4_IPB, nvt.w4, ipb); xive_router_write_nvt(xrtr, nvt_blk, nvt_idx, &nvt, 4); =20 /* --=20 2.21.0 From nobody Fri May 3 08:51:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1568825925; cv=none; d=zoho.com; s=zohoarc; b=OUr4O2p/8iUK2wKCzDwfnzxryiPKuZ8hz+R44ZjCrm3Dj+LvyDmRkaEc/pP1qJOpxKeLHMYN9PJetBS1/Mqlhdh6aka6NiELffbN33xVYNO0KPtLOXgCyUznlWbiKPZ/coMLGydgrZD/dPYH5doAXxSLLrpOoiNlK6Pv0YaF7Q0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1568825925; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=4tyD+Yi1JyYkO8rkA974U5omRvvwxMuqENCHfnnKEm4=; b=bi6UUxyNf6Uakj0XUKlh0g9dIz6r1r9yBy8cMugplf7x9TG0n3626z1FD7vjLiqncqDGpZ5nKHd7DFojKB6tkDJKCaffckhudSKX3ITSYh3vwJ8yUnNRi9KjwupmZDGG+9EXa8pSTWJhHBFU2D7UM7So0hXflt6H8bqvEGX5WS0= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1568825925772577.1804414030909; Wed, 18 Sep 2019 09:58:45 -0700 (PDT) Received: from localhost ([::1]:32844 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iAdHu-00038Y-Ec for importer@patchew.org; Wed, 18 Sep 2019 12:58:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55893) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iAcVH-0004hl-Tg for qemu-devel@nongnu.org; Wed, 18 Sep 2019 12:08:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iAcVG-0003cD-A4 for qemu-devel@nongnu.org; Wed, 18 Sep 2019 12:08:27 -0400 Received: from 7.mo177.mail-out.ovh.net ([46.105.61.149]:47648) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iAcVG-0003bK-4g for qemu-devel@nongnu.org; Wed, 18 Sep 2019 12:08:26 -0400 Received: from player799.ha.ovh.net (unknown [10.109.160.23]) by mo177.mail-out.ovh.net (Postfix) with ESMTP id C2A5510B58E for ; Wed, 18 Sep 2019 18:08:24 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player799.ha.ovh.net (Postfix) with ESMTPSA id 1332A9F0E85B; Wed, 18 Sep 2019 16:08:19 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 18 Sep 2019 18:06:36 +0200 Message-Id: <20190918160645.25126-17-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190918160645.25126-1-clg@kaod.org> References: <20190918160645.25126-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 6230730086807407590 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrudekgdeliecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.105.61.149 Subject: [Qemu-devel] [PATCH v4 16/25] ppc/pnv: Remove pnv_xive_vst_size() routine X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Greg Kurz Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" pnv_xive_vst_size() tries to compute the size of a VSD table from the information given by FW. The number of entries of the table are deduced from the result and the MMIO regions of the ESBs and the ENDS are also resized with the computed value. But for indirect tables, the result is incorrect. An indirect table is a one page array of VSDs pointing to subpages containing XIVE virtual structures. The number of first level VSD entries is page aligned and the overall computed size of the table is too large. It can also be completely wrong when the first VSD entry is not yet initialized. Remove pnv_xive_vst_size() and use a simpler form for direct tables. This is only useful when outputting the XIVE sources on the monitor and to resize the ESB MMIO window. Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/pnv_xive.c | 112 +++++++++++++++++---------------------------- 1 file changed, 43 insertions(+), 69 deletions(-) diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index 74d6ccbea3d6..b7d505839e68 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -123,36 +123,22 @@ static uint64_t pnv_xive_vst_page_size_allowed(uint32= _t page_shift) page_shift =3D=3D 21 || page_shift =3D=3D 24; } =20 -static uint64_t pnv_xive_vst_size(uint64_t vsd) -{ - uint64_t vst_tsize =3D 1ull << (GETFIELD(VSD_TSIZE, vsd) + 12); - - /* - * Read the first descriptor to get the page size of the indirect - * table. - */ - if (VSD_INDIRECT & vsd) { - uint32_t nr_pages =3D vst_tsize / XIVE_VSD_SIZE; - uint32_t page_shift; - - vsd =3D ldq_be_dma(&address_space_memory, vsd & VSD_ADDRESS_MASK); - page_shift =3D GETFIELD(VSD_TSIZE, vsd) + 12; - - if (!pnv_xive_vst_page_size_allowed(page_shift)) { - return 0; - } - - return nr_pages * (1ull << page_shift); - } - - return vst_tsize; -} - static uint64_t pnv_xive_vst_addr_direct(PnvXive *xive, uint32_t type, uint64_t vsd, uint32_t idx) { const XiveVstInfo *info =3D &vst_infos[type]; uint64_t vst_addr =3D vsd & VSD_ADDRESS_MASK; + uint64_t vst_tsize =3D 1ull << (GETFIELD(VSD_TSIZE, vsd) + 12); + uint32_t idx_max; + + idx_max =3D vst_tsize / info->size - 1; + if (idx > idx_max) { +#ifdef XIVE_DEBUG + xive_error(xive, "VST: %s entry %x out of range [ 0 .. %x ] !?", + info->name, idx, idx_max); +#endif + return 0; + } =20 return vst_addr + idx * info->size; } @@ -215,7 +201,6 @@ static uint64_t pnv_xive_vst_addr(PnvXive *xive, uint32= _t type, uint8_t blk, { const XiveVstInfo *info =3D &vst_infos[type]; uint64_t vsd; - uint32_t idx_max; =20 if (blk >=3D info->max_blocks) { xive_error(xive, "VST: invalid block id %d for VST %s %d !?", @@ -232,15 +217,6 @@ static uint64_t pnv_xive_vst_addr(PnvXive *xive, uint3= 2_t type, uint8_t blk, return xive ? pnv_xive_vst_addr(xive, type, blk, idx) : 0; } =20 - idx_max =3D pnv_xive_vst_size(vsd) / info->size - 1; - if (idx > idx_max) { -#ifdef XIVE_DEBUG - xive_error(xive, "VST: %s entry %x/%x out of range [ 0 .. %x ] !?", - info->name, blk, idx, idx_max); -#endif - return 0; - } - if (VSD_INDIRECT & vsd) { return pnv_xive_vst_addr_indirect(xive, type, vsd, idx); } @@ -519,19 +495,12 @@ static uint64_t pnv_xive_pc_size(PnvXive *xive) return (~xive->regs[CQ_PC_BARM >> 3] + 1) & CQ_PC_BARM_MASK; } =20 -static uint32_t pnv_xive_nr_ipis(PnvXive *xive) +static uint32_t pnv_xive_nr_ipis(PnvXive *xive, uint8_t blk) { - uint8_t blk =3D xive->chip->chip_id; - - return pnv_xive_vst_size(xive->vsds[VST_TSEL_SBE][blk]) * SBE_PER_BYTE; -} - -static uint32_t pnv_xive_nr_ends(PnvXive *xive) -{ - uint8_t blk =3D xive->chip->chip_id; + uint64_t vsd =3D xive->vsds[VST_TSEL_SBE][blk]; + uint64_t vst_tsize =3D 1ull << (GETFIELD(VSD_TSIZE, vsd) + 12); =20 - return pnv_xive_vst_size(xive->vsds[VST_TSEL_EQDT][blk]) - / vst_infos[VST_TSEL_EQDT].size; + return VSD_INDIRECT & vsd ? 0 : vst_tsize * SBE_PER_BYTE; } =20 /* @@ -664,6 +633,7 @@ static void pnv_xive_vst_set_exclusive(PnvXive *xive, u= int8_t type, XiveSource *xsrc =3D &xive->ipi_source; const XiveVstInfo *info =3D &vst_infos[type]; uint32_t page_shift =3D GETFIELD(VSD_TSIZE, vsd) + 12; + uint64_t vst_tsize =3D 1ull << page_shift; uint64_t vst_addr =3D vsd & VSD_ADDRESS_MASK; =20 /* Basic checks */ @@ -699,11 +669,16 @@ static void pnv_xive_vst_set_exclusive(PnvXive *xive,= uint8_t type, =20 case VST_TSEL_EQDT: /* - * Backing store pages for the END. Compute the number of ENDs - * provisioned by FW and resize the END ESB window accordingly. + * Backing store pages for the END. + * + * If the table is direct, we can compute the number of PQ + * entries provisioned by FW (such as skiboot) and resize the + * END ESB window accordingly. */ - memory_region_set_size(&end_xsrc->esb_mmio, pnv_xive_nr_ends(xive)= * - (1ull << (end_xsrc->esb_shift + 1))); + if (!(VSD_INDIRECT & vsd)) { + memory_region_set_size(&end_xsrc->esb_mmio, (vst_tsize / info-= >size) + * (1ull << xsrc->esb_shift)); + } memory_region_add_subregion(&xive->end_edt_mmio, 0, &end_xsrc->esb_mmio); break; @@ -712,11 +687,16 @@ static void pnv_xive_vst_set_exclusive(PnvXive *xive,= uint8_t type, /* * Backing store pages for the source PQ bits. The model does * not use these PQ bits backed in RAM because the XiveSource - * model has its own. Compute the number of IRQs provisioned - * by FW and resize the IPI ESB window accordingly. + * model has its own. + * + * If the table is direct, we can compute the number of PQ + * entries provisioned by FW (such as skiboot) and resize the + * ESB window accordingly. */ - memory_region_set_size(&xsrc->esb_mmio, pnv_xive_nr_ipis(xive) * - (1ull << xsrc->esb_shift)); + if (!(VSD_INDIRECT & vsd)) { + memory_region_set_size(&xsrc->esb_mmio, vst_tsize * SBE_PER_BY= TE + * (1ull << xsrc->esb_shift)); + } memory_region_add_subregion(&xive->ipi_edt_mmio, 0, &xsrc->esb_mmi= o); break; =20 @@ -1666,8 +1646,7 @@ void pnv_xive_pic_print_info(PnvXive *xive, Monitor *= mon) XiveRouter *xrtr =3D XIVE_ROUTER(xive); uint8_t blk =3D xive->chip->chip_id; uint32_t srcno0 =3D XIVE_SRCNO(blk, 0); - uint32_t nr_ipis =3D pnv_xive_nr_ipis(xive); - uint32_t nr_ends =3D pnv_xive_nr_ends(xive); + uint32_t nr_ipis =3D pnv_xive_nr_ipis(xive, blk); XiveEAS eas; XiveEND end; int i; @@ -1687,21 +1666,16 @@ void pnv_xive_pic_print_info(PnvXive *xive, Monitor= *mon) } } =20 - monitor_printf(mon, "XIVE[%x] ENDT %08x .. %08x\n", blk, 0, nr_ends - = 1); - for (i =3D 0; i < nr_ends; i++) { - if (xive_router_get_end(xrtr, blk, i, &end)) { - break; - } - xive_end_pic_print_info(&end, i, mon); + monitor_printf(mon, "XIVE[%x] ENDT\n", blk); + i =3D 0; + while (!xive_router_get_end(xrtr, blk, i, &end)) { + xive_end_pic_print_info(&end, i++, mon); } =20 - monitor_printf(mon, "XIVE[%x] END Escalation %08x .. %08x\n", blk, 0, - nr_ends - 1); - for (i =3D 0; i < nr_ends; i++) { - if (xive_router_get_end(xrtr, blk, i, &end)) { - break; - } - xive_end_eas_pic_print_info(&end, i, mon); + monitor_printf(mon, "XIVE[%x] END Escalation EAT\n", blk); + i =3D 0; + while (!xive_router_get_end(xrtr, blk, i, &end)) { + xive_end_eas_pic_print_info(&end, i++, mon); } } =20 --=20 2.21.0 From nobody Fri May 3 08:51:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; 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Wed, 18 Sep 2019 16:08:24 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 18 Sep 2019 18:06:37 +0200 Message-Id: <20190918160645.25126-18-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190918160645.25126-1-clg@kaod.org> References: <20190918160645.25126-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 6232418937404492774 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrudekgdeliecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.105.56.76 Subject: [Qemu-devel] [PATCH v4 17/25] ppc/pnv: Dump the XIVE NVT table X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Greg Kurz Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" This is to track the configuration of the base END index of the vCPU and the Interrupt Pending Buffer. The NVT IPB is updated when an interrupt can not be presented to a vCPU. Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/xive_regs.h | 2 ++ hw/intc/pnv_xive.c | 22 ++++++++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/include/hw/ppc/xive_regs.h b/include/hw/ppc/xive_regs.h index dea0318e7e89..dd42c33cef35 100644 --- a/include/hw/ppc/xive_regs.h +++ b/include/hw/ppc/xive_regs.h @@ -232,6 +232,8 @@ typedef struct XiveNVT { uint32_t w0; #define NVT_W0_VALID PPC_BIT32(0) uint32_t w1; +#define NVT_W1_EQ_BLOCK PPC_BITMASK32(0, 3) +#define NVT_W1_EQ_INDEX PPC_BITMASK32(4, 31) uint32_t w2; uint32_t w3; uint32_t w4; diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index b7d505839e68..782775136288 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -1641,6 +1641,21 @@ static const MemoryRegionOps pnv_xive_pc_ops =3D { }, }; =20 +static void xive_nvt_pic_print_info(XiveNVT *nvt, uint32_t nvt_idx, + Monitor *mon) +{ + uint8_t eq_blk =3D xive_get_field32(NVT_W1_EQ_BLOCK, nvt->w1); + uint32_t eq_idx =3D xive_get_field32(NVT_W1_EQ_INDEX, nvt->w1); + + if (!xive_nvt_is_valid(nvt)) { + return; + } + + monitor_printf(mon, " %08x end:%02x/%04x IPB:%02x\n", nvt_idx, + eq_blk, eq_idx, + xive_get_field32(NVT_W4_IPB, nvt->w4)); +} + void pnv_xive_pic_print_info(PnvXive *xive, Monitor *mon) { XiveRouter *xrtr =3D XIVE_ROUTER(xive); @@ -1649,6 +1664,7 @@ void pnv_xive_pic_print_info(PnvXive *xive, Monitor *= mon) uint32_t nr_ipis =3D pnv_xive_nr_ipis(xive, blk); XiveEAS eas; XiveEND end; + XiveNVT nvt; int i; =20 monitor_printf(mon, "XIVE[%x] Source %08x .. %08x\n", blk, srcno0, @@ -1677,6 +1693,12 @@ void pnv_xive_pic_print_info(PnvXive *xive, Monitor = *mon) while (!xive_router_get_end(xrtr, blk, i, &end)) { xive_end_eas_pic_print_info(&end, i++, mon); } + + monitor_printf(mon, "XIVE[%x] NVTT\n", blk); + i =3D 0; + while (!xive_router_get_nvt(xrtr, blk, i, &nvt)) { + xive_nvt_pic_print_info(&nvt, i++, mon); + } } =20 static void pnv_xive_reset(void *dev) --=20 2.21.0 From nobody Fri May 3 08:51:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1568827366423690.3011351009721; Wed, 18 Sep 2019 10:22:46 -0700 (PDT) Received: from localhost ([::1]:33248 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iAdf3-0000ni-Cs for importer@patchew.org; Wed, 18 Sep 2019 13:22:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55942) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iAcVU-0004wa-Tp for qemu-devel@nongnu.org; Wed, 18 Sep 2019 12:08:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iAcVT-0003l1-3R for qemu-devel@nongnu.org; Wed, 18 Sep 2019 12:08:40 -0400 Received: from 15.mo6.mail-out.ovh.net ([188.165.39.161]:50603) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iAcVS-0003i6-Ps for qemu-devel@nongnu.org; Wed, 18 Sep 2019 12:08:39 -0400 Received: from player799.ha.ovh.net (unknown [10.108.42.174]) by mo6.mail-out.ovh.net (Postfix) with ESMTP id 592481DDA89 for ; Wed, 18 Sep 2019 18:08:36 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player799.ha.ovh.net (Postfix) with ESMTPSA id 540D59F0E99C; Wed, 18 Sep 2019 16:08:30 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 18 Sep 2019 18:06:38 +0200 Message-Id: <20190918160645.25126-19-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190918160645.25126-1-clg@kaod.org> References: <20190918160645.25126-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 6234107785789606886 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrudekgdeljecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 188.165.39.161 Subject: [Qemu-devel] [PATCH v4 18/25] ppc/pnv: Skip empty slots of the XIVE NVT table X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Greg Kurz Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" We try to loop on the full table skipping empty indirect pages which are not necessarily allocated. This is useful to dump the contexts of the KVM vCPUs. Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/pnv_xive.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index 782775136288..a986d4ed9364 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -1641,6 +1641,12 @@ static const MemoryRegionOps pnv_xive_pc_ops =3D { }, }; =20 +/* + * skiboot uses an indirect NVT table with 64k subpages + */ +#define XIVE_NVT_COUNT (1 << XIVE_NVT_SHIFT) +#define XIVE_NVT_PER_PAGE (0x10000 / sizeof(XiveNVT)) + static void xive_nvt_pic_print_info(XiveNVT *nvt, uint32_t nvt_idx, Monitor *mon) { @@ -1694,10 +1700,12 @@ void pnv_xive_pic_print_info(PnvXive *xive, Monitor= *mon) xive_end_eas_pic_print_info(&end, i++, mon); } =20 - monitor_printf(mon, "XIVE[%x] NVTT\n", blk); - i =3D 0; - while (!xive_router_get_nvt(xrtr, blk, i, &nvt)) { - xive_nvt_pic_print_info(&nvt, i++, mon); + monitor_printf(mon, "XIVE[%x] NVTT %08x .. %08x\n", blk, 0, + XIVE_NVT_COUNT - 1); + for (i =3D 0; i < XIVE_NVT_COUNT; i +=3D XIVE_NVT_PER_PAGE) { + while (!xive_router_get_nvt(xrtr, blk, i, &nvt)) { + xive_nvt_pic_print_info(&nvt, i++, mon); + } } } =20 --=20 2.21.0 From nobody Fri May 3 08:51:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1568826335; cv=none; d=zoho.com; s=zohoarc; b=jpKtd3KiedCgBMQChdkEMohmrt9yaGazH2s4vWgMfgDOBiNjh/0BCWBsUBdFpPTjEE43LI6AqwmpT2Zv/oTBazOhw9y2YRqDJRDWitSSRoEWNCjlBiUiMpBjYdio97XrWCYQ4JLXUH0bIMszmKC1lgGANQJE3kAQD3MB1tmXDw8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1568826335; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=y3PPmoWVd7rx1ffe8CCH5/uaZHXhZYDlNlvcxLZmhBk=; b=M3t8kT3CpfXO7CNRHBIhsmJAKBWLcL9RNXliaFqE4OBQWnj2RNKJOPiNdWrCbyQnLrCUDbFwVLs4XYa/MvFtFN8CkKqeYsV0sUHZu8TQJoHa9mDr1FImNK/F45WywIf6bHtQQOlN3BDUAjnDlgexQhPGzwI84/Hyh1/5cW2xLyk= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1568826335501300.35789335179413; Wed, 18 Sep 2019 10:05:35 -0700 (PDT) Received: from localhost ([::1]:32984 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iAdOU-0008Jr-0g for importer@patchew.org; Wed, 18 Sep 2019 13:05:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55966) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iAcVZ-00052F-1a for qemu-devel@nongnu.org; Wed, 18 Sep 2019 12:08:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iAcVX-0003no-HM for qemu-devel@nongnu.org; Wed, 18 Sep 2019 12:08:44 -0400 Received: from 12.mo1.mail-out.ovh.net ([87.98.162.229]:39987) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iAcVX-0003mu-BX for qemu-devel@nongnu.org; Wed, 18 Sep 2019 12:08:43 -0400 Received: from player799.ha.ovh.net (unknown [10.109.160.23]) by mo1.mail-out.ovh.net (Postfix) with ESMTP id C8BE619029F for ; Wed, 18 Sep 2019 18:08:41 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player799.ha.ovh.net (Postfix) with ESMTPSA id 51A019F0EA12; Wed, 18 Sep 2019 16:08:36 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 18 Sep 2019 18:06:39 +0200 Message-Id: <20190918160645.25126-20-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190918160645.25126-1-clg@kaod.org> References: <20190918160645.25126-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 6235515161851562982 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrudekgdeliecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 87.98.162.229 Subject: [Qemu-devel] [PATCH v4 19/25] ppc/pnv: Introduce a pnv_xive_block_id() helper X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Greg Kurz Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" When PC_TCTXT_CHIPID_OVERRIDE is configured, the PC_TCTXT_CHIPID field overrides the hardwired chip ID in the Powerbus operations and for CAM compares. This is typically used in the one block-per-chip configuration to associate a unique block id number to each IC of the system. Simplify the model with a pnv_xive_block_id() helper and remove 'tctx_chipid' which becomes useless. The model does support multiple blocks per chip. Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: David Gibson --- include/hw/ppc/pnv_xive.h | 3 -- hw/intc/pnv_xive.c | 68 ++++++++++++++++++++------------------- 2 files changed, 35 insertions(+), 36 deletions(-) diff --git a/include/hw/ppc/pnv_xive.h b/include/hw/ppc/pnv_xive.h index 4fdaa9247d65..f4c7caad40ee 100644 --- a/include/hw/ppc/pnv_xive.h +++ b/include/hw/ppc/pnv_xive.h @@ -72,9 +72,6 @@ typedef struct PnvXive { /* Interrupt controller registers */ uint64_t regs[0x300]; =20 - /* Can be configured by FW */ - uint32_t tctx_chipid; - /* * Virtual Structure Descriptor tables : EAT, SBE, ENDT, NVTT, IRQ * These are in a SRAM protected by ECC. diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index a986d4ed9364..8c352315f6f5 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -85,13 +85,30 @@ static inline uint64_t SETFIELD(uint64_t mask, uint64_t= word, return (word & ~mask) | ((value << ctz64(mask)) & mask); } =20 +/* + * When PC_TCTXT_CHIPID_OVERRIDE is configured, the PC_TCTXT_CHIPID + * field overrides the hardwired chip ID in the Powerbus operations + * and for CAM compares + */ +static uint8_t pnv_xive_block_id(PnvXive *xive) +{ + uint8_t blk =3D xive->chip->chip_id; + uint64_t cfg_val =3D xive->regs[PC_TCTXT_CFG >> 3]; + + if (cfg_val & PC_TCTXT_CHIPID_OVERRIDE) { + blk =3D GETFIELD(PC_TCTXT_CHIPID, cfg_val); + } + + return blk; +} + /* * Remote access to controllers. HW uses MMIOs. For now, a simple scan * of the chips is good enough. * * TODO: Block scope support */ -static PnvXive *pnv_xive_get_ic(uint8_t blk) +static PnvXive *pnv_xive_get_remote(uint8_t blk) { PnvMachineState *pnv =3D PNV_MACHINE(qdev_get_machine()); int i; @@ -100,7 +117,7 @@ static PnvXive *pnv_xive_get_ic(uint8_t blk) Pnv9Chip *chip9 =3D PNV9_CHIP(pnv->chips[i]); PnvXive *xive =3D &chip9->xive; =20 - if (xive->chip->chip_id =3D=3D blk) { + if (pnv_xive_block_id(xive) =3D=3D blk) { return xive; } } @@ -212,7 +229,7 @@ static uint64_t pnv_xive_vst_addr(PnvXive *xive, uint32= _t type, uint8_t blk, =20 /* Remote VST access */ if (GETFIELD(VSD_MODE, vsd) =3D=3D VSD_MODE_FORWARD) { - xive =3D pnv_xive_get_ic(blk); + xive =3D pnv_xive_get_remote(blk); =20 return xive ? pnv_xive_vst_addr(xive, type, blk, idx) : 0; } @@ -360,7 +377,10 @@ static int pnv_xive_get_eas(XiveRouter *xrtr, uint8_t = blk, uint32_t idx, { PnvXive *xive =3D PNV_XIVE(xrtr); =20 - if (pnv_xive_get_ic(blk) !=3D xive) { + /* + * EAT lookups should be local to the IC + */ + if (pnv_xive_block_id(xive) !=3D blk) { xive_error(xive, "VST: EAS %x is remote !?", XIVE_SRCNO(blk, idx)); return -1; } @@ -471,7 +491,7 @@ static PnvXive *pnv_xive_tm_get_xive(PowerPCCPU *cpu) static void pnv_xive_notify(XiveNotifier *xn, uint32_t srcno) { PnvXive *xive =3D PNV_XIVE(xn); - uint8_t blk =3D xive->chip->chip_id; + uint8_t blk =3D pnv_xive_block_id(xive); =20 xive_router_notify(xn, XIVE_SRCNO(blk, srcno)); } @@ -835,20 +855,7 @@ static void pnv_xive_ic_reg_write(void *opaque, hwaddr= offset, case PC_TCTXT_CFG: /* * TODO: block group support - * - * PC_TCTXT_CFG_BLKGRP_EN - * PC_TCTXT_CFG_HARD_CHIPID_BLK : - * Moves the chipid into block field for hardwired CAM compares. - * Block offset value is adjusted to 0b0..01 & ThrdId - * - * Will require changes in xive_presenter_tctx_match(). I am - * not sure how to handle that yet. */ - - /* Overrides hardwired chip ID with the chip ID field */ - if (val & PC_TCTXT_CHIPID_OVERRIDE) { - xive->tctx_chipid =3D GETFIELD(PC_TCTXT_CHIPID, val); - } break; case PC_TCTXT_TRACK: /* @@ -1665,7 +1672,8 @@ static void xive_nvt_pic_print_info(XiveNVT *nvt, uin= t32_t nvt_idx, void pnv_xive_pic_print_info(PnvXive *xive, Monitor *mon) { XiveRouter *xrtr =3D XIVE_ROUTER(xive); - uint8_t blk =3D xive->chip->chip_id; + uint8_t blk =3D pnv_xive_block_id(xive); + uint8_t chip_id =3D xive->chip->chip_id; uint32_t srcno0 =3D XIVE_SRCNO(blk, 0); uint32_t nr_ipis =3D pnv_xive_nr_ipis(xive, blk); XiveEAS eas; @@ -1673,12 +1681,12 @@ void pnv_xive_pic_print_info(PnvXive *xive, Monitor= *mon) XiveNVT nvt; int i; =20 - monitor_printf(mon, "XIVE[%x] Source %08x .. %08x\n", blk, srcno0, - srcno0 + nr_ipis - 1); + monitor_printf(mon, "XIVE[%x] #%d Source %08x .. %08x\n", chip_id, blk, + srcno0, srcno0 + nr_ipis - 1); xive_source_pic_print_info(&xive->ipi_source, srcno0, mon); =20 - monitor_printf(mon, "XIVE[%x] EAT %08x .. %08x\n", blk, srcno0, - srcno0 + nr_ipis - 1); + monitor_printf(mon, "XIVE[%x] #%d EAT %08x .. %08x\n", chip_id, blk, + srcno0, srcno0 + nr_ipis - 1); for (i =3D 0; i < nr_ipis; i++) { if (xive_router_get_eas(xrtr, blk, i, &eas)) { break; @@ -1688,20 +1696,20 @@ void pnv_xive_pic_print_info(PnvXive *xive, Monitor= *mon) } } =20 - monitor_printf(mon, "XIVE[%x] ENDT\n", blk); + monitor_printf(mon, "XIVE[%x] #%d ENDT\n", chip_id, blk); i =3D 0; while (!xive_router_get_end(xrtr, blk, i, &end)) { xive_end_pic_print_info(&end, i++, mon); } =20 - monitor_printf(mon, "XIVE[%x] END Escalation EAT\n", blk); + monitor_printf(mon, "XIVE[%x] #%d END Escalation EAT\n", chip_id, blk); i =3D 0; while (!xive_router_get_end(xrtr, blk, i, &end)) { xive_end_eas_pic_print_info(&end, i++, mon); } =20 - monitor_printf(mon, "XIVE[%x] NVTT %08x .. %08x\n", blk, 0, - XIVE_NVT_COUNT - 1); + monitor_printf(mon, "XIVE[%x] #%d NVTT %08x .. %08x\n", chip_id, blk, + 0, XIVE_NVT_COUNT - 1); for (i =3D 0; i < XIVE_NVT_COUNT; i +=3D XIVE_NVT_PER_PAGE) { while (!xive_router_get_nvt(xrtr, blk, i, &nvt)) { xive_nvt_pic_print_info(&nvt, i++, mon); @@ -1715,12 +1723,6 @@ static void pnv_xive_reset(void *dev) XiveSource *xsrc =3D &xive->ipi_source; XiveENDSource *end_xsrc =3D &xive->end_source; =20 - /* - * Use the PnvChip id to identify the XIVE interrupt controller. - * It can be overriden by configuration at runtime. - */ - xive->tctx_chipid =3D xive->chip->chip_id; - /* Default page size (Should be changed at runtime to 64k) */ xive->ic_shift =3D xive->vc_shift =3D xive->pc_shift =3D 12; =20 --=20 2.21.0 From nobody Fri May 3 08:51:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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Wed, 18 Sep 2019 16:08:41 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 18 Sep 2019 18:06:40 +0200 Message-Id: <20190918160645.25126-21-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190918160645.25126-1-clg@kaod.org> References: <20190918160645.25126-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 6237204013030607846 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrudekgdeliecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 188.165.52.203 Subject: [Qemu-devel] [PATCH v4 20/25] ppc/pnv: Extend XiveRouter with a get_block_id() handler X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Greg Kurz Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" When doing CAM line compares, fetch the block id from the interrupt controller which can have set the PC_TCTXT_CHIPID field. Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/xive.h | 2 +- hw/intc/pnv_xive.c | 6 ++++++ hw/intc/spapr_xive.c | 6 ++++++ hw/intc/xive.c | 21 ++++++++++++++++----- 4 files changed, 29 insertions(+), 6 deletions(-) diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index 794dfcaae0f8..1f084b6e13a5 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -351,6 +351,7 @@ typedef struct XiveRouterClass { XiveNVT *nvt); int (*write_nvt)(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, XiveNVT *nvt, uint8_t word_number); + uint8_t (*get_block_id)(XiveRouter *xrtr); } XiveRouterClass; =20 int xive_router_get_eas(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_id= x, @@ -431,7 +432,6 @@ typedef struct XiveENDSource { DeviceState parent; =20 uint32_t nr_ends; - uint8_t block_id; =20 /* ESB memory region */ uint32_t esb_shift; diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index 8c352315f6f5..8fa78e1c6cd9 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -460,6 +460,11 @@ static int pnv_xive_match_nvt(XivePresenter *xptr, uin= t8_t format, return count; } =20 +static uint8_t pnv_xive_get_block_id(XiveRouter *xrtr) +{ + return pnv_xive_block_id(PNV_XIVE(xrtr)); +} + /* * The TIMA MMIO space is shared among the chips and to identify the * chip from which the access is being done, we extract the chip id @@ -1915,6 +1920,7 @@ static void pnv_xive_class_init(ObjectClass *klass, v= oid *data) xrc->write_end =3D pnv_xive_write_end; xrc->get_nvt =3D pnv_xive_get_nvt; xrc->write_nvt =3D pnv_xive_write_nvt; + xrc->get_block_id =3D pnv_xive_get_block_id; =20 xnc->notify =3D pnv_xive_notify; xpc->match_nvt =3D pnv_xive_match_nvt; diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c index 864f50167c65..1a2475811257 100644 --- a/hw/intc/spapr_xive.c +++ b/hw/intc/spapr_xive.c @@ -482,6 +482,11 @@ static int spapr_xive_match_nvt(XivePresenter *xptr, u= int8_t format, return count; } =20 +static uint8_t spapr_xive_get_block_id(XiveRouter *xrtr) +{ + return SPAPR_XIVE_BLOCK_ID; +} + static const VMStateDescription vmstate_spapr_xive_end =3D { .name =3D TYPE_SPAPR_XIVE "/end", .version_id =3D 1, @@ -571,6 +576,7 @@ static void spapr_xive_class_init(ObjectClass *klass, v= oid *data) xrc->write_end =3D spapr_xive_write_end; xrc->get_nvt =3D spapr_xive_get_nvt; xrc->write_nvt =3D spapr_xive_write_nvt; + xrc->get_block_id =3D spapr_xive_get_block_id; =20 xpc->match_nvt =3D spapr_xive_match_nvt; } diff --git a/hw/intc/xive.c b/hw/intc/xive.c index f47b0cf2b053..dfae584a319f 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -1322,17 +1322,25 @@ int xive_router_write_nvt(XiveRouter *xrtr, uint8_t= nvt_blk, uint32_t nvt_idx, return xrc->write_nvt(xrtr, nvt_blk, nvt_idx, nvt, word_number); } =20 +static int xive_router_get_block_id(XiveRouter *xrtr) +{ + XiveRouterClass *xrc =3D XIVE_ROUTER_GET_CLASS(xrtr); + + return xrc->get_block_id(xrtr); +} + /* * Encode the HW CAM line in the block group mode format : * * chip << 19 | 0000000 0 0001 thread (7Bit) */ -static uint32_t xive_tctx_hw_cam_line(XiveTCTX *tctx) +static uint32_t xive_tctx_hw_cam_line(XivePresenter *xptr, XiveTCTX *tctx) { CPUPPCState *env =3D &POWERPC_CPU(tctx->cs)->env; uint32_t pir =3D env->spr_cb[SPR_PIR].default_value; + uint8_t blk =3D xive_router_get_block_id(XIVE_ROUTER(xptr)); =20 - return xive_nvt_cam_line((pir >> 8) & 0xf, 1 << 7 | (pir & 0x7f)); + return xive_nvt_cam_line(blk, 1 << 7 | (pir & 0x7f)); } =20 /* @@ -1369,7 +1377,7 @@ int xive_presenter_tctx_match(XivePresenter *xptr, Xi= veTCTX *tctx, =20 /* PHYS ring */ if ((be32_to_cpu(qw3w2) & TM_QW3W2_VT) && - cam =3D=3D xive_tctx_hw_cam_line(tctx)) { + cam =3D=3D xive_tctx_hw_cam_line(xptr, tctx)) { return TM_QW3_HV_PHYS; } =20 @@ -1706,7 +1714,11 @@ static uint64_t xive_end_source_read(void *opaque, h= waddr addr, unsigned size) uint8_t pq; uint64_t ret =3D -1; =20 - end_blk =3D xsrc->block_id; + /* + * The block id should be deduced from the load address on the END + * ESB MMIO but our model only supports a single block per XIVE chip. + */ + end_blk =3D xive_router_get_block_id(xsrc->xrtr); end_idx =3D addr >> (xsrc->esb_shift + 1); =20 if (xive_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) { @@ -1815,7 +1827,6 @@ static void xive_end_source_realize(DeviceState *dev,= Error **errp) } =20 static Property xive_end_source_properties[] =3D { - DEFINE_PROP_UINT8("block-id", XiveENDSource, block_id, 0), DEFINE_PROP_UINT32("nr-ends", XiveENDSource, nr_ends, 0), DEFINE_PROP_UINT32("shift", XiveENDSource, esb_shift, XIVE_ESB_64K), DEFINE_PROP_END_OF_LIST(), --=20 2.21.0 From nobody Fri May 3 08:51:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Wed, 18 Sep 2019 12:08:53 -0400 Received: from player799.ha.ovh.net (unknown [10.109.143.209]) by mo1.mail-out.ovh.net (Postfix) with ESMTP id A926F19022E for ; Wed, 18 Sep 2019 18:08:52 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player799.ha.ovh.net (Postfix) with ESMTPSA id 40D949F0EA94; Wed, 18 Sep 2019 16:08:47 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 18 Sep 2019 18:06:41 +0200 Message-Id: <20190918160645.25126-22-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190918160645.25126-1-clg@kaod.org> References: <20190918160645.25126-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 6238611387565378534 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrudekgdeliecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 87.98.162.229 Subject: [Qemu-devel] [PATCH v4 21/25] ppc/pnv: Quiesce some XIVE errors X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Greg Kurz Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" When dumping the END and NVT tables, the error logging is too noisy. Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/pnv_xive.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index 8fa78e1c6cd9..4c1fa024cdf5 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -29,7 +29,7 @@ =20 #include "pnv_xive_regs.h" =20 -#define XIVE_DEBUG +#undef XIVE_DEBUG =20 /* * Virtual structures table (VST) @@ -174,7 +174,9 @@ static uint64_t pnv_xive_vst_addr_indirect(PnvXive *xiv= e, uint32_t type, vsd =3D ldq_be_dma(&address_space_memory, vsd_addr); =20 if (!(vsd & VSD_ADDRESS_MASK)) { +#ifdef XIVE_DEBUG xive_error(xive, "VST: invalid %s entry %x !?", info->name, idx); +#endif return 0; } =20 @@ -195,7 +197,9 @@ static uint64_t pnv_xive_vst_addr_indirect(PnvXive *xiv= e, uint32_t type, vsd =3D ldq_be_dma(&address_space_memory, vsd_addr); =20 if (!(vsd & VSD_ADDRESS_MASK)) { +#ifdef XIVE_DEBUG xive_error(xive, "VST: invalid %s entry %x !?", info->name, id= x); +#endif return 0; } =20 --=20 2.21.0 From nobody Fri May 3 08:51:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Wed, 18 Sep 2019 12:09:00 -0400 Received: from player799.ha.ovh.net (unknown [10.109.159.222]) by mo5.mail-out.ovh.net (Postfix) with ESMTP id D0EBB24BFBC for ; Wed, 18 Sep 2019 18:08:58 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player799.ha.ovh.net (Postfix) with ESMTPSA id AAED89F0EADB; Wed, 18 Sep 2019 16:08:52 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 18 Sep 2019 18:06:42 +0200 Message-Id: <20190918160645.25126-23-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190918160645.25126-1-clg@kaod.org> References: <20190918160645.25126-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 6240300235906649062 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrudekgdeliecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 188.165.51.82 Subject: [Qemu-devel] [PATCH v4 22/25] ppc/xive: Introduce a xive_os_cam_decode() helper X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Greg Kurz Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The OS CAM line has a special encoding exploited by the HW. Provide a helper routine to hide the details to the TIMA command handlers. This also clarifies the endian ness of different variables : 'qw1w2' is big-endian and 'cam' is native. Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive.c | 35 ++++++++++++++++++++++++++--------- 1 file changed, 26 insertions(+), 9 deletions(-) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index dfae584a319f..cdc4ea8b0e51 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -342,14 +342,29 @@ static void xive_tm_set_os_pending(XivePresenter *xpt= r, XiveTCTX *tctx, xive_tctx_ipb_update(tctx, TM_QW1_OS, priority_to_ipb(value & 0xff)); } =20 +static void xive_os_cam_decode(uint32_t cam, uint8_t *nvt_blk, + uint32_t *nvt_idx, bool *vo) +{ + *nvt_blk =3D xive_nvt_blk(cam); + *nvt_idx =3D xive_nvt_idx(cam); + *vo =3D !!(cam & TM_QW1W2_VO); +} + static uint64_t xive_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, unsigned size) { - uint32_t qw1w2_prev =3D xive_tctx_word2(&tctx->regs[TM_QW1_OS]); - uint32_t qw1w2; + uint32_t qw1w2 =3D xive_tctx_word2(&tctx->regs[TM_QW1_OS]); + uint32_t qw1w2_new; + uint32_t cam =3D be32_to_cpu(qw1w2); + uint8_t nvt_blk; + uint32_t nvt_idx; + bool vo; =20 - qw1w2 =3D xive_set_field32(TM_QW1W2_VO, qw1w2_prev, 0); - memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); + xive_os_cam_decode(cam, &nvt_blk, &nvt_idx, &vo); + + /* Invalidate CAM line */ + qw1w2_new =3D xive_set_field32(TM_QW1W2_VO, qw1w2, 0); + memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2_new, 4); return qw1w2; } =20 @@ -387,13 +402,15 @@ static void xive_tctx_need_resend(XiveRouter *xrtr, X= iveTCTX *tctx, static void xive_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, uint64_t value, unsigned si= ze) { - uint32_t qw1w2 =3D value; - uint8_t nvt_blk =3D xive_nvt_blk(qw1w2); - uint32_t nvt_idx =3D xive_nvt_idx(qw1w2); - bool vo =3D !!(qw1w2 & TM_QW1W2_VO); + uint32_t cam =3D value; + uint32_t qw1w2 =3D cpu_to_be32(cam); + uint8_t nvt_blk; + uint32_t nvt_idx; + bool vo; + + xive_os_cam_decode(cam, &nvt_blk, &nvt_idx, &vo); =20 /* First update the registers */ - qw1w2 =3D cpu_to_be32(qw1w2); memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); =20 /* Check the interrupt pending bits */ --=20 2.21.0 From nobody Fri May 3 08:51:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1568828534; cv=none; d=zoho.com; s=zohoarc; b=M3BbP8osOW4uPz2vXi/dVR3enOyTdSjNLFWPX2mnU5nE9Q3YDWo12/kLLadTUE72Cjv985jwkS5lJXwk3FYV5l3++y5a6ODonIaQReCLpy4veQfxkgjzrQ7wqRrSiCSom+pEWLBb5vCyeRDk13CXp7eI9Br+zifrWph/TYJMHcM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1568828534; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; 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Wed, 18 Sep 2019 12:09:06 -0400 Received: from 7.mo173.mail-out.ovh.net ([46.105.44.159]:52825) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iAcVt-0003z1-MC for qemu-devel@nongnu.org; Wed, 18 Sep 2019 12:09:05 -0400 Received: from player799.ha.ovh.net (unknown [10.109.146.213]) by mo173.mail-out.ovh.net (Postfix) with ESMTP id 53BF1119FEF for ; Wed, 18 Sep 2019 18:09:04 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player799.ha.ovh.net (Postfix) with ESMTPSA id D12DE9F0EB16; Wed, 18 Sep 2019 16:08:58 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 18 Sep 2019 18:06:43 +0200 Message-Id: <20190918160645.25126-24-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190918160645.25126-1-clg@kaod.org> References: <20190918160645.25126-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 6241989086273965030 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrudekgdeliecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.105.44.159 Subject: [Qemu-devel] [PATCH v4 23/25] ppc/xive: Check V bit in TM_PULL_POOL_CTX X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Greg Kurz Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" A context should be 'valid' when pulled from the thread interrupt context registers. Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index cdc4ea8b0e51..07b7c3586c12 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -362,6 +362,11 @@ static uint64_t xive_tm_pull_os_ctx(XivePresenter *xpt= r, XiveTCTX *tctx, =20 xive_os_cam_decode(cam, &nvt_blk, &nvt_idx, &vo); =20 + if (!vo) { + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: pulling invalid NVT %x/%x !?= \n", + nvt_blk, nvt_idx); + } + /* Invalidate CAM line */ qw1w2_new =3D xive_set_field32(TM_QW1W2_VO, qw1w2, 0); memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2_new, 4); --=20 2.21.0 From nobody Fri May 3 08:51:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1568830240; cv=none; d=zoho.com; s=zohoarc; b=d8tsCdNor8YPNIN5OTVIgkL38w9eYcu+secWbe/e9liLedLYNiglI/TsG+EhZvvQCXvsyw4lO8Qjda3f38U1z/oOEX9tM8rWZJkW/IS10ZDSdqbHveYAM2/OI8TKAkgafAQJt5Z/umncbGJvOirxpafvC1ajGnjVp4vgB/PVkOE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1568830240; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=9Vmkdb090OTxkZ339zFKahyF/jaYYzjC4HlzJWxEn8o=; b=b3RG7lHv1TWKvHGUuan7+bV63890yVKNkul7gE4T4aZMJnHs1d7GpzyQObXTaoNTHQIouBWWTo5HtGd5aIXS4ltxZrqoAZMM/cKzDBetI+fWZgvtf5mNMGVQB5m3FeErBV/xrH2nr1O7GTiDVFI0hPKV42RLuoBxh+SNaQ4PTV0= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1568830240323629.1137636012238; Wed, 18 Sep 2019 11:10:40 -0700 (PDT) Received: from localhost ([::1]:33524 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iAe31-0007i0-6W for importer@patchew.org; Wed, 18 Sep 2019 13:47:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56116) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iAcW0-0005ax-Ri for qemu-devel@nongnu.org; Wed, 18 Sep 2019 12:09:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iAcVz-00042f-Bm for qemu-devel@nongnu.org; Wed, 18 Sep 2019 12:09:12 -0400 Received: from 4.mo2.mail-out.ovh.net ([87.98.172.75]:49365) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iAcVz-00041q-6c for qemu-devel@nongnu.org; Wed, 18 Sep 2019 12:09:11 -0400 Received: from player799.ha.ovh.net (unknown [10.109.143.216]) by mo2.mail-out.ovh.net (Postfix) with ESMTP id BB6EE1AD3E9 for ; Wed, 18 Sep 2019 18:09:09 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player799.ha.ovh.net (Postfix) with ESMTPSA id 552AF9F0EB3D; Wed, 18 Sep 2019 16:09:04 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 18 Sep 2019 18:06:44 +0200 Message-Id: <20190918160645.25126-25-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190918160645.25126-1-clg@kaod.org> References: <20190918160645.25126-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 6243396460226907110 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrudekgdeljecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 87.98.172.75 Subject: [Qemu-devel] [PATCH v4 24/25] ppc/pnv: Improve trigger data definition X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Greg Kurz Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The trigger definition is used for triggers both for HW source interrupts, PHB, PSI, as well as for rerouting interrupts between Interrupt Controller. HW source controllers set bit0 of word0 to =E2=80=980=E2=80=99 as they prov= ide EAS information (EAS block + EAS index) in the 8 byte data and not END information, and bit1 of word0 to =E2=80=981=E2=80=99 to signal that the st= ate bit check has been performed. Introduce these new trigger bits and rename the XIVE_SRCNO macros in XIVE_EAS to reflect better the nature of the data. This is breaking the notification for the PSI model which will be fixed in the next patch. Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/xive_regs.h | 24 +++++++++++++++++++++--- hw/intc/pnv_xive.c | 16 ++++++++++++---- hw/intc/xive.c | 4 ++-- 3 files changed, 35 insertions(+), 9 deletions(-) diff --git a/include/hw/ppc/xive_regs.h b/include/hw/ppc/xive_regs.h index dd42c33cef35..83a2f2cc1318 100644 --- a/include/hw/ppc/xive_regs.h +++ b/include/hw/ppc/xive_regs.h @@ -22,9 +22,27 @@ /* * Interrupt source number encoding on PowerBUS */ -#define XIVE_SRCNO_BLOCK(srcno) (((srcno) >> 28) & 0xf) -#define XIVE_SRCNO_INDEX(srcno) ((srcno) & 0x0fffffff) -#define XIVE_SRCNO(blk, idx) ((uint32_t)(blk) << 28 | (idx)) +/* + * Trigger data definition + * + * The trigger definition is used for triggers both for HW source + * interrupts (PHB, PSI), as well as for rerouting interrupts between + * Interrupt Controller. + * + * HW source controllers set bit0 of word0 to =E2=80=980=E2=80=99 as they = provide EAS + * information (EAS block + EAS index) in the 8 byte data and not END + * information, and bit1 of word0 to =E2=80=981=E2=80=99 to signal that th= e state bit + * check has been performed. + */ +#define XIVE_TRIGGER_END PPC_BIT(0) +#define XIVE_TRIGGER_EAS PPC_BIT(1) + +/* + * QEMU macros to manipulate the trigger payload in native endian + */ +#define XIVE_EAS_BLOCK(n) (((n) >> 28) & 0xf) +#define XIVE_EAS_INDEX(n) ((n) & 0x0fffffff) +#define XIVE_EAS(blk, idx) ((uint32_t)(blk) << 28 | (idx)) =20 #define TM_SHIFT 16 =20 diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index 4c1fa024cdf5..61af3f23000f 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -385,7 +385,7 @@ static int pnv_xive_get_eas(XiveRouter *xrtr, uint8_t b= lk, uint32_t idx, * EAT lookups should be local to the IC */ if (pnv_xive_block_id(xive) !=3D blk) { - xive_error(xive, "VST: EAS %x is remote !?", XIVE_SRCNO(blk, idx)); + xive_error(xive, "VST: EAS %x is remote !?", XIVE_EAS(blk, idx)); return -1; } =20 @@ -502,7 +502,7 @@ static void pnv_xive_notify(XiveNotifier *xn, uint32_t = srcno) PnvXive *xive =3D PNV_XIVE(xn); uint8_t blk =3D pnv_xive_block_id(xive); =20 - xive_router_notify(xn, XIVE_SRCNO(blk, srcno)); + xive_router_notify(xn, XIVE_EAS(blk, srcno)); } =20 /* @@ -1287,12 +1287,20 @@ static const MemoryRegionOps pnv_xive_ic_reg_ops = =3D { =20 static void pnv_xive_ic_hw_trigger(PnvXive *xive, hwaddr addr, uint64_t va= l) { + uint8_t blk =3D XIVE_EAS_BLOCK(val); + uint32_t idx =3D XIVE_EAS_INDEX(val); + /* * Forward the source event notification directly to the Router. * The source interrupt number should already be correctly encoded * with the chip block id by the sending device (PHB, PSI). */ - xive_router_notify(XIVE_NOTIFIER(xive), val); + if (val & XIVE_TRIGGER_EAS) { + xive_router_notify(XIVE_NOTIFIER(xive), XIVE_EAS(blk, idx)); + } else { + xive_error(xive, "IC: END trigger at @0x%"HWADDR_PRIx" data 0x%"PR= Ix64, + addr, val); + } } =20 static void pnv_xive_ic_notify_write(void *opaque, hwaddr addr, uint64_t v= al, @@ -1683,7 +1691,7 @@ void pnv_xive_pic_print_info(PnvXive *xive, Monitor *= mon) XiveRouter *xrtr =3D XIVE_ROUTER(xive); uint8_t blk =3D pnv_xive_block_id(xive); uint8_t chip_id =3D xive->chip->chip_id; - uint32_t srcno0 =3D XIVE_SRCNO(blk, 0); + uint32_t srcno0 =3D XIVE_EAS(blk, 0); uint32_t nr_ipis =3D pnv_xive_nr_ipis(xive, blk); XiveEAS eas; XiveEND end; diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 07b7c3586c12..6702f32be601 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -1652,8 +1652,8 @@ do_escalation: void xive_router_notify(XiveNotifier *xn, uint32_t lisn) { XiveRouter *xrtr =3D XIVE_ROUTER(xn); - uint8_t eas_blk =3D XIVE_SRCNO_BLOCK(lisn); - uint32_t eas_idx =3D XIVE_SRCNO_INDEX(lisn); + uint8_t eas_blk =3D XIVE_EAS_BLOCK(lisn); + uint32_t eas_idx =3D XIVE_EAS_INDEX(lisn); XiveEAS eas; =20 /* EAS cache lookup */ --=20 2.21.0 From nobody Fri May 3 08:51:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Wed, 18 Sep 2019 12:09:17 -0400 Received: from player799.ha.ovh.net (unknown [10.108.42.75]) by mo6.mail-out.ovh.net (Postfix) with ESMTP id 032B81E18FE for ; Wed, 18 Sep 2019 18:09:15 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player799.ha.ovh.net (Postfix) with ESMTPSA id C18559F0EB7B; Wed, 18 Sep 2019 16:09:09 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 18 Sep 2019 18:06:45 +0200 Message-Id: <20190918160645.25126-26-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190918160645.25126-1-clg@kaod.org> References: <20190918160645.25126-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 6245085311069555686 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrudekgdeljecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.105.76.65 Subject: [Qemu-devel] [PATCH v4 25/25] ppc/pnv: Use the EAS trigger bit when triggering an interrupt from PSI X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Greg Kurz Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" and replace the cpu_physical_memory_write() by a address_space_stq_be(). Signed-off-by: C=C3=A9dric Le Goater --- hw/ppc/pnv_psi.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c index 88ba8e7b9b0a..3b0f4b02f9bf 100644 --- a/hw/ppc/pnv_psi.c +++ b/hw/ppc/pnv_psi.c @@ -660,10 +660,19 @@ static void pnv_psi_notify(XiveNotifier *xf, uint32_t= srcno) =20 uint32_t offset =3D (psi->regs[PSIHB_REG(PSIHB9_IVT_OFFSET)] >> PSIHB9_IVT_OFF_SHIFT); - uint64_t lisn =3D cpu_to_be64(offset + srcno); + uint64_t data =3D XIVE_TRIGGER_EAS | offset | srcno; + MemTxResult result; =20 - if (valid) { - cpu_physical_memory_write(notify_addr, &lisn, sizeof(lisn)); + if (!valid) { + return; + } + + address_space_stq_be(&address_space_memory, notify_addr, data, + MEMTXATTRS_UNSPECIFIED, &result); + if (result !=3D MEMTX_OK) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: trigger failed @%" + HWADDR_PRIx "\n", __func__, notif_port); + return; } } =20 --=20 2.21.0