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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id c132sm3562207wme.27.2019.09.13.08.49.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Sep 2019 08:49:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=1Sl1J/OS8LWghz5QlTGlE0bH3B4/gCCk6zhNctlDdKI=; b=RZqwTmuygmTqha5mtmiUtypoF+2weJ8VVHIQVqOspstHunFDXx6JUpimxT/E0jkt26 /bxn/e278dk3vV76pqJ0cK/Cl4uSpX2tPS9mGS5daRTpAgxq+wJAWoSGRRfpUtmxFsIZ PDla4jDxpNeIiC5Q1cRB7CAe56Ekk367YslTGqnl8KbbGByo3dw0bZDGOFsv6nUYtHMm tic58LIOt2uJ/sCjXkZ2nEQEUnhyrhhE5AjpUwmYtwfHA5nUjp3YvCtxLcpN24EbDrSy Xgv7qsknKhoRYPix3nPp8jfNfCC9zJ8iSgoBEOuVzjFxcZ9CmipEKMXiYXPf0+zZzCql UH0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1Sl1J/OS8LWghz5QlTGlE0bH3B4/gCCk6zhNctlDdKI=; b=iBjVtxFXTIStTnjqyIIbOIORIyg+xv4W5J5q3Wr94gEWKUY/sgguUR64hW9BQYGC9h wC9MP+fEnFGpSHelSqO8bJ9t+ZpKmVMn6KCfNe/IFrJwwehK8g4zqk8uSQPDGny8SDfC co5Ga7f2djnXvII/q59/v4cDDKTduqL6lwyxq6LVhdyRvmASFK2qlMcT5uFJV8DZ3nyG DTWrwc8O6WnhCobsor6iQTKTPMj+noXfnVCuIclOcRzJAASvFiMTa7cdszhL1cTfM3gU kLUJ2/h20LHRTWvUb2bX6snZtP29R01GtlF8Eh98QhlhCSYe3ZNiY0bchPs3clMheyj6 3m8w== X-Gm-Message-State: APjAAAUAdI1WCd6SbUENzwOFSAj7a1Jk1gC57BimYf48GveLFcKEfecn dix+1/R2baUfqLIe2deenaikl2RQoKjKYA== X-Google-Smtp-Source: APXvYqykAz1sOPM1rQo4wiKKb+Ry8fQR6Q0+rf9KJ7seZn0tXFxbzPy9z5YzJwCR50i1LKC4nUlV5A== X-Received: by 2002:a1c:7319:: with SMTP id d25mr3901877wmb.56.1568389799314; Fri, 13 Sep 2019 08:49:59 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 13 Sep 2019 16:49:44 +0100 Message-Id: <20190913154952.27724-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190913154952.27724-1-peter.maydell@linaro.org> References: <20190913154952.27724-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::330 Subject: [Qemu-devel] [PULL 04/12] aspeed: Use consistent typenames X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: C=C3=A9dric Le Goater Improve the naming of the different controller models to ease their generation when initializing the SoC. The rename of the SMC types is breaking migration compatibility. Signed-off-by: C=C3=A9dric Le Goater Message-id: 20190904070506.1052-5-clg@kaod.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/arm/aspeed_soc.h | 3 --- hw/arm/aspeed_soc.c | 25 ++++++++++++------------- hw/ssi/aspeed_smc.c | 12 ++++++------ 3 files changed, 18 insertions(+), 22 deletions(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index a56effebc16..ab5052b12cb 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -61,9 +61,6 @@ typedef struct AspeedSoCInfo { uint32_t silicon_rev; uint64_t sram_size; int spis_num; - const char *fmc_typename; - const char **spi_typename; - const char *gpio_typename; int wdts_num; const int *irqmap; const hwaddr *memmap; diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index 3aa73d2438e..25dbc409d35 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -112,10 +112,6 @@ static const int aspeed_soc_ast2400_irqmap[] =3D { =20 #define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap =20 -static const char *aspeed_soc_ast2400_typenames[] =3D { "aspeed.smc.spi" }; -static const char *aspeed_soc_ast2500_typenames[] =3D { - "aspeed.smc.ast2500-spi1", "aspeed.smc.ast2500-spi2" }; - static const AspeedSoCInfo aspeed_socs[] =3D { { .name =3D "ast2400-a1", @@ -123,9 +119,6 @@ static const AspeedSoCInfo aspeed_socs[] =3D { .silicon_rev =3D AST2400_A1_SILICON_REV, .sram_size =3D 0x8000, .spis_num =3D 1, - .fmc_typename =3D "aspeed.smc.fmc", - .spi_typename =3D aspeed_soc_ast2400_typenames, - .gpio_typename =3D "aspeed.gpio-ast2400", .wdts_num =3D 2, .irqmap =3D aspeed_soc_ast2400_irqmap, .memmap =3D aspeed_soc_ast2400_memmap, @@ -136,9 +129,6 @@ static const AspeedSoCInfo aspeed_socs[] =3D { .silicon_rev =3D AST2500_A1_SILICON_REV, .sram_size =3D 0x9000, .spis_num =3D 2, - .fmc_typename =3D "aspeed.smc.ast2500-fmc", - .spi_typename =3D aspeed_soc_ast2500_typenames, - .gpio_typename =3D "aspeed.gpio-ast2500", .wdts_num =3D 3, .irqmap =3D aspeed_soc_ast2500_irqmap, .memmap =3D aspeed_soc_ast2500_memmap, @@ -158,6 +148,12 @@ static void aspeed_soc_init(Object *obj) AspeedSoCState *s =3D ASPEED_SOC(obj); AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); int i; + char socname[8]; + char typename[64]; + + if (sscanf(sc->info->name, "%7s", socname) !=3D 1) { + g_assert_not_reached(); + } =20 for (i =3D 0; i < sc->info->num_cpus; i++) { object_initialize_child(obj, "cpu[*]", OBJECT(&s->cpu[i]), @@ -190,14 +186,16 @@ static void aspeed_soc_init(Object *obj) sysbus_init_child_obj(obj, "i2c", OBJECT(&s->i2c), sizeof(s->i2c), TYPE_ASPEED_I2C); =20 + snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); sysbus_init_child_obj(obj, "fmc", OBJECT(&s->fmc), sizeof(s->fmc), - sc->info->fmc_typename); + typename); object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs", &error_abort); =20 for (i =3D 0; i < sc->info->spis_num; i++) { + snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, soc= name); sysbus_init_child_obj(obj, "spi[*]", OBJECT(&s->spi[i]), - sizeof(s->spi[i]), sc->info->spi_typename[i]= ); + sizeof(s->spi[i]), typename); } =20 sysbus_init_child_obj(obj, "sdmc", OBJECT(&s->sdmc), sizeof(s->sdmc), @@ -226,8 +224,9 @@ static void aspeed_soc_init(Object *obj) sysbus_init_child_obj(obj, "xdma", OBJECT(&s->xdma), sizeof(s->xdma), TYPE_ASPEED_XDMA); =20 + snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); sysbus_init_child_obj(obj, "gpio", OBJECT(&s->gpio), sizeof(s->gpio), - sc->info->gpio_typename); + typename); } =20 static void aspeed_soc_realize(DeviceState *dev, Error **errp) diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index 9f3cff5fb6f..f4f7c181830 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -190,7 +190,7 @@ static const AspeedSegments aspeed_segments_ast2500_spi= 2[] =3D { =20 static const AspeedSMCController controllers[] =3D { { - .name =3D "aspeed.smc.smc", + .name =3D "aspeed.smc-ast2400", .r_conf =3D R_CONF, .r_ce_ctrl =3D R_CE_CTRL, .r_ctrl0 =3D R_CTRL0, @@ -203,7 +203,7 @@ static const AspeedSMCController controllers[] =3D { .has_dma =3D false, .nregs =3D ASPEED_SMC_R_SMC_MAX, }, { - .name =3D "aspeed.smc.fmc", + .name =3D "aspeed.fmc-ast2400", .r_conf =3D R_CONF, .r_ce_ctrl =3D R_CE_CTRL, .r_ctrl0 =3D R_CTRL0, @@ -216,7 +216,7 @@ static const AspeedSMCController controllers[] =3D { .has_dma =3D true, .nregs =3D ASPEED_SMC_R_MAX, }, { - .name =3D "aspeed.smc.spi", + .name =3D "aspeed.spi1-ast2400", .r_conf =3D R_SPI_CONF, .r_ce_ctrl =3D 0xff, .r_ctrl0 =3D R_SPI_CTRL0, @@ -229,7 +229,7 @@ static const AspeedSMCController controllers[] =3D { .has_dma =3D false, .nregs =3D ASPEED_SMC_R_SPI_MAX, }, { - .name =3D "aspeed.smc.ast2500-fmc", + .name =3D "aspeed.fmc-ast2500", .r_conf =3D R_CONF, .r_ce_ctrl =3D R_CE_CTRL, .r_ctrl0 =3D R_CTRL0, @@ -242,7 +242,7 @@ static const AspeedSMCController controllers[] =3D { .has_dma =3D true, .nregs =3D ASPEED_SMC_R_MAX, }, { - .name =3D "aspeed.smc.ast2500-spi1", + .name =3D "aspeed.spi1-ast2500", .r_conf =3D R_CONF, .r_ce_ctrl =3D R_CE_CTRL, .r_ctrl0 =3D R_CTRL0, @@ -255,7 +255,7 @@ static const AspeedSMCController controllers[] =3D { .has_dma =3D false, .nregs =3D ASPEED_SMC_R_MAX, }, { - .name =3D "aspeed.smc.ast2500-spi2", + .name =3D "aspeed.spi2-ast2500", .r_conf =3D R_CONF, .r_ce_ctrl =3D R_CE_CTRL, .r_ctrl0 =3D R_CTRL0, --=20 2.20.1