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X-Received-From: 2a00:1450:4864:20::436 Subject: [Qemu-devel] [PULL 10/12] aspeed/scu: Introduce a aspeed_scu_get_apb_freq() routine X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: C=C3=A9dric Le Goater The APB frequency can be calculated directly when needed from the HPLL_PARAM and CLK_SEL register values. This removes useless state in the model. Signed-off-by: C=C3=A9dric Le Goater Message-id: 20190904070506.1052-11-clg@kaod.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/misc/aspeed_scu.h | 8 +++----- hw/misc/aspeed_scu.c | 25 +++++++++---------------- hw/timer/aspeed_timer.c | 3 ++- 3 files changed, 14 insertions(+), 22 deletions(-) diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h index 90dd4dadede..239e94fe2c4 100644 --- a/include/hw/misc/aspeed_scu.h +++ b/include/hw/misc/aspeed_scu.h @@ -32,10 +32,6 @@ typedef struct AspeedSCUState { uint32_t hw_strap1; uint32_t hw_strap2; uint32_t hw_prot_key; - - uint32_t clkin; - uint32_t hpll; - uint32_t apb_freq; } AspeedSCUState; =20 #define AST2400_A0_SILICON_REV 0x02000303U @@ -56,12 +52,14 @@ typedef struct AspeedSCUClass { SysBusDeviceClass parent_class; =20 const uint32_t *resets; - uint32_t (*calc_hpll)(AspeedSCUState *s); + uint32_t (*calc_hpll)(AspeedSCUState *s, uint32_t hpll_reg); uint32_t apb_divider; } AspeedSCUClass; =20 #define ASPEED_SCU_PROT_KEY 0x1688A8A8 =20 +uint32_t aspeed_scu_get_apb_freq(AspeedSCUState *s); + /* * Extracted from Aspeed SDK v00.03.21. Fixes and extra definitions * were added. diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index d284458b9b3..620b25c2047 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -164,11 +164,12 @@ static uint32_t aspeed_scu_get_random(void) return num; } =20 -static void aspeed_scu_set_apb_freq(AspeedSCUState *s) +uint32_t aspeed_scu_get_apb_freq(AspeedSCUState *s) { AspeedSCUClass *asc =3D ASPEED_SCU_GET_CLASS(s); + uint32_t hpll =3D asc->calc_hpll(s, s->regs[HPLL_PARAM]); =20 - s->apb_freq =3D s->hpll / (SCU_CLK_GET_PCLK_DIV(s->regs[CLK_SEL]) + 1) + return hpll / (SCU_CLK_GET_PCLK_DIV(s->regs[CLK_SEL]) + 1) / asc->apb_divider; } =20 @@ -228,7 +229,6 @@ static void aspeed_scu_write(void *opaque, hwaddr offse= t, uint64_t data, return; case CLK_SEL: s->regs[reg] =3D data; - aspeed_scu_set_apb_freq(s); break; case HW_STRAP1: if (ASPEED_IS_AST2500(s->regs[SILICON_REV])) { @@ -290,11 +290,11 @@ static const uint32_t hpll_ast2400_freqs[][4] =3D { { 400, 375, 350, 425 }, /* 25MHz */ }; =20 -static uint32_t aspeed_2400_scu_calc_hpll(AspeedSCUState *s) +static uint32_t aspeed_2400_scu_calc_hpll(AspeedSCUState *s, uint32_t hpll= _reg) { - uint32_t hpll_reg =3D s->regs[HPLL_PARAM]; uint8_t freq_select; bool clk_25m_in; + uint32_t clkin =3D aspeed_scu_get_clkin(s); =20 if (hpll_reg & SCU_AST2400_H_PLL_OFF) { return 0; @@ -311,7 +311,7 @@ static uint32_t aspeed_2400_scu_calc_hpll(AspeedSCUStat= e *s) multiplier =3D (2 - od) * ((n + 2) / (d + 1)); } =20 - return s->clkin * multiplier; + return clkin * multiplier; } =20 /* HW strapping */ @@ -321,10 +321,10 @@ static uint32_t aspeed_2400_scu_calc_hpll(AspeedSCUSt= ate *s) return hpll_ast2400_freqs[clk_25m_in][freq_select] * 1000000; } =20 -static uint32_t aspeed_2500_scu_calc_hpll(AspeedSCUState *s) +static uint32_t aspeed_2500_scu_calc_hpll(AspeedSCUState *s, uint32_t hpll= _reg) { - uint32_t hpll_reg =3D s->regs[HPLL_PARAM]; uint32_t multiplier =3D 1; + uint32_t clkin =3D aspeed_scu_get_clkin(s); =20 if (hpll_reg & SCU_H_PLL_OFF) { return 0; @@ -338,7 +338,7 @@ static uint32_t aspeed_2500_scu_calc_hpll(AspeedSCUStat= e *s) multiplier =3D ((m + 1) / (n + 1)) / (p + 1); } =20 - return s->clkin * multiplier; + return clkin * multiplier; } =20 static void aspeed_scu_reset(DeviceState *dev) @@ -351,13 +351,6 @@ static void aspeed_scu_reset(DeviceState *dev) s->regs[HW_STRAP1] =3D s->hw_strap1; s->regs[HW_STRAP2] =3D s->hw_strap2; s->regs[PROT_KEY] =3D s->hw_prot_key; - - /* - * All registers are set. Now compute the frequencies of the main cloc= ks - */ - s->clkin =3D aspeed_scu_get_clkin(s); - s->hpll =3D asc->calc_hpll(s); - aspeed_scu_set_apb_freq(s); } =20 static uint32_t aspeed_silicon_revs[] =3D { diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c index 59c2bbeee60..2bda826882d 100644 --- a/hw/timer/aspeed_timer.c +++ b/hw/timer/aspeed_timer.c @@ -93,7 +93,8 @@ static inline uint32_t calculate_rate(struct AspeedTimer = *t) { AspeedTimerCtrlState *s =3D timer_to_ctrl(t); =20 - return timer_external_clock(t) ? TIMER_CLOCK_EXT_HZ : s->scu->apb_freq; + return timer_external_clock(t) ? TIMER_CLOCK_EXT_HZ : + aspeed_scu_get_apb_freq(s->scu); } =20 static inline uint32_t calculate_ticks(struct AspeedTimer *t, uint64_t now= _ns) --=20 2.20.1