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Fri, 13 Sep 2019 08:18:48 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: peter.maydell@linaro.org Date: Fri, 13 Sep 2019 16:18:42 +0100 Message-Id: <20190913151845.12582-4-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190913151845.12582-1-alex.bennee@linaro.org> References: <20190913151845.12582-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 Subject: [Qemu-devel] [PATCH v6 3/6] target/arm: handle A-profile semihosting at translate time X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) As for the other semihosting calls we can resolve this at translate time. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell --- v2 - update for change to gen_exception_internal_insn API v3 - update for decode tree, merge T32 & A32 commits - dropped r-b due to changes v4 - !IS_USER and !arm_dc_feature(s, ARM_FEATURE_M) v5 - only if !IS_USER for softmmu, linux-user is still allowed --- target/arm/translate.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index b5272119330..698c594e8ce 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10222,14 +10222,25 @@ static bool trans_CBZ(DisasContext *s, arg_CBZ *a) } =20 /* - * Supervisor call + * Supervisor call - both T32 & A32 come here so we need to check + * which mode we are in when checking for semihosting. */ =20 static bool trans_SVC(DisasContext *s, arg_SVC *a) { - gen_set_pc_im(s, s->base.pc_next); - s->svc_imm =3D a->imm; - s->base.is_jmp =3D DISAS_SWI; + const uint32_t semihost_imm =3D s->thumb ? 0xab : 0x123456; + + if (!arm_dc_feature(s, ARM_FEATURE_M) && semihosting_enabled() && +#ifndef CONFIG_USER_ONLY + !IS_USER(s) && +#endif + (a->imm =3D=3D semihost_imm)) { + gen_exception_internal_insn(s, s->base.pc_next, EXCP_SEMIHOST); + } else { + gen_set_pc_im(s, s->base.pc_next); + s->svc_imm =3D a->imm; + s->base.is_jmp =3D DISAS_SWI; + } return true; } =20 --=20 2.20.1