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Wed, 11 Sep 2019 09:50:01 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: peter.maydell@linaro.org Date: Wed, 11 Sep 2019 17:49:55 +0100 Message-Id: <20190911164959.11003-2-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190911164959.11003-1-alex.bennee@linaro.org> References: <20190911164959.11003-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 Subject: [Qemu-devel] [PATCH v5 1/5] tests/tcg: clean-up some comments after the de-tangling X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) These were missed in the recent de-tangling so have been updated to be more actuate. I've also built up ARM_TESTS in a manner similar to AARCH64_TESTS for better consistency. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell --- tests/tcg/Makefile.target | 7 +++++-- tests/tcg/aarch64/Makefile.target | 3 ++- tests/tcg/arm/Makefile.target | 15 ++++++++------- 3 files changed, 15 insertions(+), 10 deletions(-) diff --git a/tests/tcg/Makefile.target b/tests/tcg/Makefile.target index 8808beaf74b..679eb56bd37 100644 --- a/tests/tcg/Makefile.target +++ b/tests/tcg/Makefile.target @@ -74,8 +74,11 @@ TIMEOUT=3D15 endif =20 ifdef CONFIG_USER_ONLY -# The order we include is important. We include multiarch, base arch -# and finally arch if it's not the same as base arch. +# The order we include is important. We include multiarch first and +# then the target. If there are common tests shared between +# sub-targets (e.g. ARM & AArch64) then it is up to +# $(TARGET_NAME)/Makefile.target to include the common parent +# architecture in its VPATH. -include $(SRC_PATH)/tests/tcg/multiarch/Makefile.target -include $(SRC_PATH)/tests/tcg/$(TARGET_NAME)/Makefile.target =20 diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile= .target index e763dd9da37..9758f89f905 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -8,7 +8,7 @@ VPATH +=3D $(ARM_SRC) AARCH64_SRC=3D$(SRC_PATH)/tests/tcg/aarch64 VPATH +=3D $(AARCH64_SRC) =20 -# we don't build any other ARM test +# Float-convert Tests AARCH64_TESTS=3Dfcvt =20 fcvt: LDFLAGS+=3D-lm @@ -17,6 +17,7 @@ run-fcvt: fcvt $(call run-test,$<,$(QEMU) $<, "$< on $(TARGET_NAME)") $(call diff-out,$<,$(AARCH64_SRC)/fcvt.ref) =20 +# Pauth Tests AARCH64_TESTS +=3D pauth-1 pauth-2 run-pauth-%: QEMU_OPTS +=3D -cpu max =20 diff --git a/tests/tcg/arm/Makefile.target b/tests/tcg/arm/Makefile.target index aa4e4e3782c..7347d3d0adb 100644 --- a/tests/tcg/arm/Makefile.target +++ b/tests/tcg/arm/Makefile.target @@ -8,25 +8,26 @@ ARM_SRC=3D$(SRC_PATH)/tests/tcg/arm # Set search path for all sources VPATH +=3D $(ARM_SRC) =20 -ARM_TESTS=3Dhello-arm test-arm-iwmmxt - -TESTS +=3D $(ARM_TESTS) fcvt - +# Basic Hello World +ARM_TESTS =3D hello-arm hello-arm: CFLAGS+=3D-marm -ffreestanding hello-arm: LDFLAGS+=3D-nostdlib =20 +# IWMXT floating point extensions +ARM_TESTS +=3D test-arm-iwmmxt test-arm-iwmmxt: CFLAGS+=3D-marm -march=3Diwmmxt -mabi=3Daapcs -mfpu=3Dfpv= 4-sp-d16 test-arm-iwmmxt: test-arm-iwmmxt.S $(CC) $(CFLAGS) $< -o $@ $(LDFLAGS) =20 -ifeq ($(TARGET_NAME), arm) +# Float-convert Tests +ARM_TESTS +=3D fcvt fcvt: LDFLAGS+=3D-lm # fcvt: CFLAGS+=3D-march=3Darmv8.2-a+fp16 -mfpu=3Dneon-fp-armv8 - run-fcvt: fcvt $(call run-test,fcvt,$(QEMU) $<,"$< on $(TARGET_NAME)") $(call diff-out,fcvt,$(ARM_SRC)/fcvt.ref) -endif + +TESTS +=3D $(ARM_TESTS) =20 # On ARM Linux only supports 4k pages EXTRA_RUNS+=3Drun-test-mmap-4096 --=20 2.20.1 From nobody Sat Apr 20 03:49:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PATCH v5 2/5] target/arm: handle M-profile semihosting at translate time X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) We do this for other semihosting calls so we might as well do it for M-profile as well. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- v2 - update for change to gen_exception_internal_insn API v3 - update for decode tree v4 - use !IS_USER --- target/arm/m_helper.c | 18 ++++++------------ target/arm/translate.c | 8 +++++++- 2 files changed, 13 insertions(+), 13 deletions(-) diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 884d35d2b02..27cd2f3f964 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -2114,19 +2114,13 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) break; } break; + case EXCP_SEMIHOST: + qemu_log_mask(CPU_LOG_INT, + "...handling as semihosting call 0x%x\n", + env->regs[0]); + env->regs[0] =3D do_arm_semihosting(env); + return; case EXCP_BKPT: - if (semihosting_enabled()) { - int nr; - nr =3D arm_lduw_code(env, env->regs[15], arm_sctlr_b(env)) & 0= xff; - if (nr =3D=3D 0xab) { - env->regs[15] +=3D 2; - qemu_log_mask(CPU_LOG_INT, - "...handling as semihosting call 0x%x\n", - env->regs[0]); - env->regs[0] =3D do_arm_semihosting(env); - return; - } - } armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG, false); break; case EXCP_IRQ: diff --git a/target/arm/translate.c b/target/arm/translate.c index 34bb280e3da..6689acc911e 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8424,7 +8424,13 @@ static bool trans_BKPT(DisasContext *s, arg_BKPT *a) if (!ENABLE_ARCH_5) { return false; } - gen_exception_bkpt_insn(s, syn_aa32_bkpt(a->imm, false)); + if (arm_dc_feature(s, ARM_FEATURE_M) && + semihosting_enabled() && !IS_USER(s) && + (a->imm =3D=3D 0xab)) { + gen_exception_internal_insn(s, s->base.pc_next, EXCP_SEMIHOST); + } else { + gen_exception_bkpt_insn(s, syn_aa32_bkpt(a->imm, false)); + } return true; } =20 --=20 2.20.1 From nobody Sat Apr 20 03:49:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; 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X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [PATCH v5 3/5] target/arm: handle A-profile semihosting at translate time X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) As for the other semihosting calls we can resolve this at translate time. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell --- v2 - update for change to gen_exception_internal_insn API v3 - update for decode tree, merge T32 & A32 commits - dropped r-b due to changes v4 - !IS_USER and !arm_dc_feature(s, ARM_FEATURE_M) v5 - only if !IS_USER for softmmu, linux-user is still allowed --- target/arm/translate.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 6689acc911e..fac791c4b06 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10219,14 +10219,25 @@ static bool trans_CBZ(DisasContext *s, arg_CBZ *a) } =20 /* - * Supervisor call + * Supervisor call - both T32 & A32 come here so we need to check + * which mode we are in when checking for semihosting. */ =20 static bool trans_SVC(DisasContext *s, arg_SVC *a) { - gen_set_pc_im(s, s->base.pc_next); - s->svc_imm =3D a->imm; - s->base.is_jmp =3D DISAS_SWI; + const uint32_t semihost_imm =3D s->thumb ? 0xab : 0x123456; + + if (!arm_dc_feature(s, ARM_FEATURE_M) && semihosting_enabled() && +#ifndef CONFIG_USER_ONLY + !IS_USER(s) && +#endif + (a->imm =3D=3D semihost_imm)) { + gen_exception_internal_insn(s, s->base.pc_next, EXCP_SEMIHOST); + } else { + gen_set_pc_im(s, s->base.pc_next); + s->svc_imm =3D a->imm; + s->base.is_jmp =3D DISAS_SWI; + } return true; } =20 --=20 2.20.1 From nobody Sat Apr 20 03:49:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1568220972; cv=none; d=zoho.com; s=zohoarc; b=Lxnkijuiyb1wtHRUCDXUnbTT86DlBxGNxBoCvHxCdWw46jUyqDURFvW5TIX1rSgAWzBYUX9/Sqow2RKn1sblsL+RuiAKpH9WBbCIYSf4y6KfgLMdVHpkQSmWS8Wp3mapPbyuQZoCtTE6qytTZvrT/ygoK2GF82+AcZPiUN1T4fM= ARC-Message-Signature: i=1; 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Wed, 11 Sep 2019 09:50:04 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: peter.maydell@linaro.org Date: Wed, 11 Sep 2019 17:49:58 +0100 Message-Id: <20190911164959.11003-5-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190911164959.11003-1-alex.bennee@linaro.org> References: <20190911164959.11003-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PATCH v5 4/5] target/arm: remove run time semihosting checks X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Now we do all our checking and use a common EXCP_SEMIHOST for semihosting operations we can make helper code a lot simpler. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- v2 - fix re-base conflicts - hoist EXCP_SEMIHOST check - comment cleanups v5 - move CONFIG_TCG ifdefs --- target/arm/helper.c | 96 +++++++++++---------------------------------- 1 file changed, 22 insertions(+), 74 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 507026c9154..a87ae6d46a1 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8339,88 +8339,32 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *= cs) new_el, env->pc, pstate_read(env)); } =20 -static inline bool check_for_semihosting(CPUState *cs) -{ +/* + * Do semihosting call and set the appropriate return value. All the + * permission and validity checks have been done at translate time. + * + * We only see semihosting exceptions in TCG only as they are not + * trapped to the hypervisor in KVM. + */ #ifdef CONFIG_TCG - /* Check whether this exception is a semihosting call; if so - * then handle it and return true; otherwise return false. - */ +static void handle_semihosting(CPUState *cs) +{ ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; =20 if (is_a64(env)) { - if (cs->exception_index =3D=3D EXCP_SEMIHOST) { - /* This is always the 64-bit semihosting exception. - * The "is this usermode" and "is semihosting enabled" - * checks have been done at translate time. - */ - qemu_log_mask(CPU_LOG_INT, - "...handling as semihosting call 0x%" PRIx64 "\n= ", - env->xregs[0]); - env->xregs[0] =3D do_arm_semihosting(env); - return true; - } - return false; + qemu_log_mask(CPU_LOG_INT, + "...handling as semihosting call 0x%" PRIx64 "\n", + env->xregs[0]); + env->xregs[0] =3D do_arm_semihosting(env); } else { - uint32_t imm; - - /* Only intercept calls from privileged modes, to provide some - * semblance of security. - */ - if (cs->exception_index !=3D EXCP_SEMIHOST && - (!semihosting_enabled() || - ((env->uncached_cpsr & CPSR_M) =3D=3D ARM_CPU_MODE_USR))) { - return false; - } - - switch (cs->exception_index) { - case EXCP_SEMIHOST: - /* This is always a semihosting call; the "is this usermode" - * and "is semihosting enabled" checks have been done at - * translate time. - */ - break; - case EXCP_SWI: - /* Check for semihosting interrupt. */ - if (env->thumb) { - imm =3D arm_lduw_code(env, env->regs[15] - 2, arm_sctlr_b(= env)) - & 0xff; - if (imm =3D=3D 0xab) { - break; - } - } else { - imm =3D arm_ldl_code(env, env->regs[15] - 4, arm_sctlr_b(e= nv)) - & 0xffffff; - if (imm =3D=3D 0x123456) { - break; - } - } - return false; - case EXCP_BKPT: - /* See if this is a semihosting syscall. */ - if (env->thumb) { - imm =3D arm_lduw_code(env, env->regs[15], arm_sctlr_b(env)) - & 0xff; - if (imm =3D=3D 0xab) { - env->regs[15] +=3D 2; - break; - } - } - return false; - default: - return false; - } - qemu_log_mask(CPU_LOG_INT, "...handling as semihosting call 0x%x\n", env->regs[0]); env->regs[0] =3D do_arm_semihosting(env); - return true; } -#else - return false; -#endif } +#endif =20 /* Handle a CPU exception for A and R profile CPUs. * Do any appropriate logging, handle PSCI calls, and then hand off @@ -8451,13 +8395,17 @@ void arm_cpu_do_interrupt(CPUState *cs) return; } =20 - /* Semihosting semantics depend on the register width of the - * code that caused the exception, not the target exception level, - * so must be handled here. + /* + * Semihosting semantics depend on the register width of the code + * that caused the exception, not the target exception level, so + * must be handled here. */ - if (check_for_semihosting(cs)) { +#ifdef CONFIG_TCG + if (cs->exception_index =3D=3D EXCP_SEMIHOST) { + handle_semihosting(cs); return; } +#endif =20 /* Hooks may change global state so BQL should be held, also the * BQL needs to be held for any modification of --=20 2.20.1 From nobody Sat Apr 20 03:49:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2a00:1450:4864:20::341 Subject: [Qemu-devel] [PATCH v5 5/5] target/arm: remove run-time semihosting checks for linux-user X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Riku Voipio , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-devel@nongnu.org, Laurent Vivier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Now we do all our checking at translate time we can make cpu_loop a little bit simpler. We also introduce a simple linux-user semihosting test case to defend the functionality. The out-of-tree softmmu based semihosting tests are still more comprehensive. Signed-off-by: Alex Benn=C3=A9e --- linux-user/arm/cpu_loop.c | 3 --- linux-user/arm/target_syscall.h | 3 --- tests/tcg/aarch64/Makefile.target | 5 ++++ tests/tcg/arm/Makefile.target | 5 ++++ tests/tcg/arm/semihosting.c | 45 +++++++++++++++++++++++++++++++ 5 files changed, 55 insertions(+), 6 deletions(-) create mode 100644 tests/tcg/arm/semihosting.c diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c index 8d65de5b9f4..e28c45cd4ab 100644 --- a/linux-user/arm/cpu_loop.c +++ b/linux-user/arm/cpu_loop.c @@ -325,9 +325,6 @@ void cpu_loop(CPUARMState *env) =20 if (n =3D=3D ARM_NR_cacheflush) { /* nop */ - } else if (n =3D=3D ARM_NR_semihosting - || n =3D=3D ARM_NR_thumb_semihosting) { - env->regs[0] =3D do_arm_semihosting (env); } else if (n =3D=3D 0 || n >=3D ARM_SYSCALL_BASE || env->t= humb) { /* linux syscall */ if (env->thumb || n =3D=3D 0) { diff --git a/linux-user/arm/target_syscall.h b/linux-user/arm/target_syscal= l.h index afc0772e194..f85cbdaf56f 100644 --- a/linux-user/arm/target_syscall.h +++ b/linux-user/arm/target_syscall.h @@ -18,9 +18,6 @@ struct target_pt_regs { #define ARM_NR_set_tls (ARM_NR_BASE + 5) #define ARM_NR_get_tls (ARM_NR_BASE + 6) =20 -#define ARM_NR_semihosting 0x123456 -#define ARM_NR_thumb_semihosting 0xAB - #if defined(TARGET_WORDS_BIGENDIAN) #define UNAME_MACHINE "armv5teb" #else diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile= .target index 9758f89f905..509f1afa93d 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -21,4 +21,9 @@ run-fcvt: fcvt AARCH64_TESTS +=3D pauth-1 pauth-2 run-pauth-%: QEMU_OPTS +=3D -cpu max =20 +# Semihosting smoke test for linux-user +AARCH64_TESTS +=3D semihosting +run-semihosting: semihosting + $(call run-test,$<,$(QEMU) $< 2> $<.err, "$< on $(TARGET_NAME)") + TESTS +=3D $(AARCH64_TESTS) diff --git a/tests/tcg/arm/Makefile.target b/tests/tcg/arm/Makefile.target index 7347d3d0adb..3b7fc9a64be 100644 --- a/tests/tcg/arm/Makefile.target +++ b/tests/tcg/arm/Makefile.target @@ -27,6 +27,11 @@ run-fcvt: fcvt $(call run-test,fcvt,$(QEMU) $<,"$< on $(TARGET_NAME)") $(call diff-out,fcvt,$(ARM_SRC)/fcvt.ref) =20 +# Semihosting smoke test for linux-user +ARM_TESTS +=3D semihosting +run-semihosting: semihosting + $(call run-test,$<,$(QEMU) $< 2> $<.err, "$< on $(TARGET_NAME)") + TESTS +=3D $(ARM_TESTS) =20 # On ARM Linux only supports 4k pages diff --git a/tests/tcg/arm/semihosting.c b/tests/tcg/arm/semihosting.c new file mode 100644 index 00000000000..09c89cb481a --- /dev/null +++ b/tests/tcg/arm/semihosting.c @@ -0,0 +1,45 @@ +/* + * linux-user semihosting checks + * + * Copyright (c) 2019 + * Written by Alex Benn=C3=A9e + * + * SPDX-License-Identifier: GPL-3.0-or-later + */ + +#include + +#define SYS_WRITE0 0x04 +#define SYS_REPORTEXC 0x18 + +void __semi_call(uintptr_t type, uintptr_t arg0) +{ +#if defined(__arm__) + register uintptr_t t asm("r0") =3D type; + register uintptr_t a0 asm("r1") =3D arg0; + asm("svc 0xab" + : /* no return */ + : "r" (t), "r" (a0)); +#else + register uintptr_t t asm("x0") =3D type; + register uintptr_t a0 asm("x1") =3D arg0; + asm("hlt 0xf000" + : /* no return */ + : "r" (t), "r" (a0)); +#endif +} + +int main(int argc, char *argv[argc]) +{ +#if defined(__arm__) + uintptr_t exit_code =3D 0x20026; +#else + uintptr_t exit_block[2] =3D {0x20026, 0}; + uintptr_t exit_code =3D (uintptr_t) &exit_block; +#endif + + __semi_call(SYS_WRITE0, (uintptr_t) "Hello World"); + __semi_call(SYS_REPORTEXC, exit_code); + /* if we get here we failed */ + return -1; +} --=20 2.20.1