From nobody Sun May 5 04:16:47 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1568045164; cv=none; d=zoho.com; s=zohoarc; b=ejrFVLZM/horUq6l1RJrYQvI7MKc7DOicG+md+hETrQ2AWe752CGXu+l6I9IBd40oqkIhuVaeD9u74FeDBVRtBZaSh0XZ/RMw0KyPZwiyhgnapVB5JIuGdSrUQnLTu6NtvZ6J47IR22OAe93h7ppACaujdOYTtd2Zl7BlWc3WFw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1568045164; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=DfjSCeNdyqIysRXYqHo2jFlqNd4TB97UPMLCqKGqgBs=; b=aaO6RZwhaTr0h0FGg5aOEt9S/m4jl2XTzlpQWZuSgCScqJDs1//GJms13XuBvAIXktB7wuNIqCRY+B1Vqsvq7Iwbf8pqriS6Y/BV9Viw9w668v8EKq4vMqK8MnV1IohoPS/6puEOqxBp5avds1VrrG0mrH3/5owsoFPVjCLOsqQ= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 156804516483522.236314811323837; Mon, 9 Sep 2019 09:06:04 -0700 (PDT) Received: from localhost ([::1]:58450 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i7MB1-0005ub-82 for importer@patchew.org; Mon, 09 Sep 2019 12:06:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59677) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i7M4N-0008V4-UM for qemu-devel@nongnu.org; Mon, 09 Sep 2019 11:59:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i7M4J-0001jF-R4 for qemu-devel@nongnu.org; Mon, 09 Sep 2019 11:59:11 -0400 Received: from mout.kundenserver.de ([212.227.126.187]:45969) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i7M4A-0001dV-UH; Mon, 09 Sep 2019 11:59:00 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue010 [212.227.15.167]) with ESMTPSA (Nemesis) id 1MmUcL-1iY8Ee3yuv-00iUVo; Mon, 09 Sep 2019 17:58:22 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Mon, 9 Sep 2019 17:58:05 +0200 Message-Id: <20190909155813.27760-2-laurent@vivier.eu> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190909155813.27760-1-laurent@vivier.eu> References: <20190909155813.27760-1-laurent@vivier.eu> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K1:6/mzJe7Fl0+WsYlXB2+PgIP5vNZQhmX0CPCBJ+czyviI7OlFZGj THH/akNJ2epPnQv3MW4SqN3krldQAX3hWLYcZo/JazR9clkHeTx4kq0Mc2qUDmav29j+cXI b1jJ2oF+bgZF/kUGMKP6mAZ5XStNU3Y4bJfFWLZ4tfGY8bVPxin3x2ugaXaqeTaknNoBt4K FzDyyUnv6AIU+bMg4W4ZA== X-UI-Out-Filterresults: notjunk:1;V03:K0:OvB1iw7gfZQ=:3FrUXUMFVVcT1GI5Pd3gnm EjGTuv5SpP73Ulk38a+fM9DH2/vaEtbczeh1TsKzCpRkOytfNgBxm7gdCQcAXffkjGbdTXf9g QdjrBt5Vm19hRImgvn3z1W0Du45EYxMU/Iv8XTIfzwCIx6087j+ssVd2ZjoiFC23LBeUTNhv0 r45qYITgiTEi6WDrhqbNomEGAME7s9KrSaYPc4J4++afFRtsVBfDBIKv6hbkQ5Q/PHkTcuAem 3r7pytbIwmFKP5VCMMPXQp1SuEAb3X5znKTuDro0xVlMhfnqY5kcC5URaAYYrqOb/VRyYbLoz hHQrkP8TcoCmK027ICVMBLpceG/qjLgfrvxtsCRrwgAINGuitH4B3q9rr2mVom8Lhrw8WijB/ xg+XkJ7H631Q7duLW3jY4myrxVgwGhIEa/wU6RFbwQG+8Vh2QPeUgUMRzUwcg//8myeJOCsxy I99yAP86p6PSJ91xK9F3+bKI0DyIDOLJjCtDSfp9WqM3j79AxEQB/7IV2LIX84nf7NvPUSIUQ hPazD7NuzfRBz0mRLzkbI+ZQxK1QmmH8LH+M8g8JGGdGyCAMq4CN1gmuhZzt23wQuEGY8IFOd q/JI78YKTOSSid58ltYzs3LF0JB+aqe5mfbs5HDU4TOQLKdt8ci1ux/QTxUrV2yHmaxnr/SJ5 klftny9MPJCjWXbMQ6L4m1xvZmByknxPZwUU7qcFoBbC4xW4RBQCkVRFrk+vxGf6DyGWwgoJD r1RfW9FTiQnWZT40MFLsLJ7tdgfbLU82LO/+rIxdVfqCAksqB0poS7skN/Rj7ci9W4vf+UDRt T8byKglUfQnHtyLSxVKIELrGKgp4LfuUziNWwzLQtusQMMXhzk= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 212.227.126.187 Subject: [Qemu-devel] [PATCH v9 1/9] esp: add pseudo-DMA as used by Macintosh X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Kevin Wolf , qemu-block@nongnu.org, Thomas Huth , Jason Wang , Mark Cave-Ayland , "Dr . David Alan Gilbert" , Max Reitz , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Gerd Hoffmann , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Paolo Bonzini , Aurelien Jarno , Laurent Vivier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" There is no DMA in Quadra 800, so the CPU reads/writes the data from the PDMA register (offset 0x100, ESP_PDMA in hw/m68k/q800.c) and copies them to/from the memory. There is a nice assembly loop in the kernel to do that, see linux/drivers/scsi/mac_esp.c:MAC_ESP_PDMA_LOOP(). The start of the transfer is triggered by the DREQ interrupt (see linux mac_esp_send_pdma_cmd()), the CPU polls on the IRQ flag to start the transfer after a SCSI command has been sent (in Quadra 800 it goes through the VIA2, the via2-irq line and the vIFR register) The Macintosh hardware includes hardware handshaking to prevent the CPU from reading invalid data or writing data faster than the peripheral device can accept it. This is the "blind mode", and from the doc: "Approximate maximum SCSI transfer rates within a blocks are 1.4 MB per second for blind transfers in the Macintosh II" Some references can be found in: Apple Macintosh Family Hardware Reference, ISBN 0-201-19255-1 Guide to the Macintosh Family Hardware, ISBN-0-201-52405-8 Co-developed-by: Mark Cave-Ayland Signed-off-by: Mark Cave-Ayland Signed-off-by: Laurent Vivier --- hw/scsi/esp.c | 296 +++++++++++++++++++++++++++++++++++++----- include/hw/scsi/esp.h | 7 + 2 files changed, 274 insertions(+), 29 deletions(-) diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c index 841d79b60e..ffbeee9f3c 100644 --- a/hw/scsi/esp.c +++ b/hw/scsi/esp.c @@ -38,6 +38,8 @@ * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C1= 00.txt * and * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9= X.txt + * + * On Macintosh Quadra it is a NCR53C96. */ =20 static void esp_raise_irq(ESPState *s) @@ -58,6 +60,16 @@ static void esp_lower_irq(ESPState *s) } } =20 +static void esp_raise_drq(ESPState *s) +{ + qemu_irq_raise(s->irq_data); +} + +static void esp_lower_drq(ESPState *s) +{ + qemu_irq_lower(s->irq_data); +} + void esp_dma_enable(ESPState *s, int irq, int level) { if (level) { @@ -84,29 +96,11 @@ void esp_request_cancelled(SCSIRequest *req) } } =20 -static uint32_t get_cmd(ESPState *s, uint8_t *buf, uint8_t buflen) +static int get_cmd_cb(ESPState *s) { - uint32_t dmalen; int target; =20 target =3D s->wregs[ESP_WBUSID] & BUSID_DID; - if (s->dma) { - dmalen =3D s->rregs[ESP_TCLO]; - dmalen |=3D s->rregs[ESP_TCMID] << 8; - dmalen |=3D s->rregs[ESP_TCHI] << 16; - if (dmalen > buflen) { - return 0; - } - s->dma_memory_read(s->dma_opaque, buf, dmalen); - } else { - dmalen =3D s->ti_size; - if (dmalen > TI_BUFSZ) { - return 0; - } - memcpy(buf, s->ti_buf, dmalen); - buf[0] =3D buf[2] >> 5; - } - trace_esp_get_cmd(dmalen, target); =20 s->ti_size =3D 0; s->ti_rptr =3D 0; @@ -125,8 +119,48 @@ static uint32_t get_cmd(ESPState *s, uint8_t *buf, uin= t8_t buflen) s->rregs[ESP_RINTR] =3D INTR_DC; s->rregs[ESP_RSEQ] =3D SEQ_0; esp_raise_irq(s); + return -1; + } + return 0; +} + +static uint32_t get_cmd(ESPState *s, uint8_t *buf, uint8_t buflen) +{ + int target; + uint32_t dmalen; + + target =3D s->wregs[ESP_WBUSID] & BUSID_DID; + if (s->dma) { + dmalen =3D s->rregs[ESP_TCLO]; + dmalen |=3D s->rregs[ESP_TCMID] << 8; + dmalen |=3D s->rregs[ESP_TCHI] << 16; + if (dmalen > buflen) { + return 0; + } + if (s->dma_memory_read) { + s->dma_memory_read(s->dma_opaque, buf, dmalen); + } else { + memcpy(s->pdma_buf, buf, dmalen); + s->pdma_len =3D dmalen; + s->pdma_start =3D s->pdma_buf; + s->pdma_cur =3D s->pdma_buf; + esp_raise_drq(s); + return 0; + } + } else { + dmalen =3D s->ti_size; + if (dmalen > TI_BUFSZ) { + return 0; + } + memcpy(buf, s->ti_buf, dmalen); + buf[0] =3D buf[2] >> 5; + } + trace_esp_get_cmd(dmalen, target); + + if (get_cmd_cb(s) < 0) { return 0; } + return dmalen; } =20 @@ -165,6 +199,16 @@ static void do_cmd(ESPState *s, uint8_t *buf) do_busid_cmd(s, &buf[1], busid); } =20 +static void satn_pdma_cb(ESPState *s) +{ + if (get_cmd_cb(s) < 0) { + return; + } + if (s->pdma_cur !=3D s->pdma_start) { + do_cmd(s, s->pdma_start); + } +} + static void handle_satn(ESPState *s) { uint8_t buf[32]; @@ -174,11 +218,22 @@ static void handle_satn(ESPState *s) s->dma_cb =3D handle_satn; return; } + s->pdma_cb =3D satn_pdma_cb; len =3D get_cmd(s, buf, sizeof(buf)); if (len) do_cmd(s, buf); } =20 +static void s_without_satn_pdma_cb(ESPState *s) +{ + if (get_cmd_cb(s) < 0) { + return; + } + if (s->pdma_cur !=3D s->pdma_start) { + do_busid_cmd(s, s->pdma_start, 0); + } +} + static void handle_s_without_atn(ESPState *s) { uint8_t buf[32]; @@ -188,18 +243,36 @@ static void handle_s_without_atn(ESPState *s) s->dma_cb =3D handle_s_without_atn; return; } + s->pdma_cb =3D s_without_satn_pdma_cb; len =3D get_cmd(s, buf, sizeof(buf)); if (len) { do_busid_cmd(s, buf, 0); } } =20 +static void satn_stop_pdma_cb(ESPState *s) +{ + if (get_cmd_cb(s) < 0) { + return; + } + s->cmdlen =3D s->pdma_cur - s->pdma_start; + if (s->cmdlen) { + trace_esp_handle_satn_stop(s->cmdlen); + s->do_cmd =3D 1; + s->rregs[ESP_RSTAT] =3D STAT_TC | STAT_CD; + s->rregs[ESP_RINTR] =3D INTR_BS | INTR_FC; + s->rregs[ESP_RSEQ] =3D SEQ_CD; + esp_raise_irq(s); + } +} + static void handle_satn_stop(ESPState *s) { if (s->dma && !s->dma_enabled) { s->dma_cb =3D handle_satn_stop; return; } + s->pdma_cb =3D satn_stop_pdma_cb;; s->cmdlen =3D get_cmd(s, s->cmdbuf, sizeof(s->cmdbuf)); if (s->cmdlen) { trace_esp_handle_satn_stop(s->cmdlen); @@ -211,16 +284,33 @@ static void handle_satn_stop(ESPState *s) } } =20 +static void write_response_pdma_cb(ESPState *s) +{ + s->rregs[ESP_RSTAT] =3D STAT_TC | STAT_ST; + s->rregs[ESP_RINTR] =3D INTR_BS | INTR_FC; + s->rregs[ESP_RSEQ] =3D SEQ_CD; + esp_raise_irq(s); +} + static void write_response(ESPState *s) { trace_esp_write_response(s->status); s->ti_buf[0] =3D s->status; s->ti_buf[1] =3D 0; if (s->dma) { - s->dma_memory_write(s->dma_opaque, s->ti_buf, 2); - s->rregs[ESP_RSTAT] =3D STAT_TC | STAT_ST; - s->rregs[ESP_RINTR] =3D INTR_BS | INTR_FC; - s->rregs[ESP_RSEQ] =3D SEQ_CD; + if (s->dma_memory_write) { + s->dma_memory_write(s->dma_opaque, s->ti_buf, 2); + s->rregs[ESP_RSTAT] =3D STAT_TC | STAT_ST; + s->rregs[ESP_RINTR] =3D INTR_BS | INTR_FC; + s->rregs[ESP_RSEQ] =3D SEQ_CD; + } else { + s->pdma_len =3D 2; + s->pdma_start =3D s->ti_buf; + s->pdma_cur =3D s->ti_buf; + s->pdma_cb =3D write_response_pdma_cb; + esp_raise_drq(s); + return; + } } else { s->ti_size =3D 2; s->ti_rptr =3D 0; @@ -242,6 +332,41 @@ static void esp_dma_done(ESPState *s) esp_raise_irq(s); } =20 +static void do_dma_pdma_cb(ESPState *s) +{ + int to_device =3D (s->ti_size < 0); + int len =3D s->pdma_cur - s->pdma_start; + if (s->do_cmd) { + s->ti_size =3D 0; + s->cmdlen =3D 0; + s->do_cmd =3D 0; + do_cmd(s, s->cmdbuf); + return; + } + s->dma_left -=3D len; + s->async_buf +=3D len; + s->async_len -=3D len; + if (to_device) { + s->ti_size +=3D len; + } else { + s->ti_size -=3D len; + } + if (s->async_len =3D=3D 0) { + scsi_req_continue(s->current_req); + /* + * If there is still data to be read from the device then + * complete the DMA operation immediately. Otherwise defer + * until the scsi layer has completed. + */ + if (to_device || s->dma_left !=3D 0 || s->ti_size =3D=3D 0) { + return; + } + } + + /* Partially filled a scsi buffer. Complete immediately. */ + esp_dma_done(s); +} + static void esp_do_dma(ESPState *s) { uint32_t len; @@ -252,10 +377,27 @@ static void esp_do_dma(ESPState *s) trace_esp_do_dma(s->cmdlen, len); assert (s->cmdlen <=3D sizeof(s->cmdbuf) && len <=3D sizeof(s->cmdbuf) - s->cmdlen); - s->dma_memory_read(s->dma_opaque, &s->cmdbuf[s->cmdlen], len); + if (s->dma_memory_read) { + s->dma_memory_read(s->dma_opaque, &s->cmdbuf[s->cmdlen], len); + } else { + s->pdma_len =3D len; + s->pdma_start =3D &s->cmdbuf[s->cmdlen]; + s->pdma_cur =3D &s->cmdbuf[s->cmdlen]; + s->pdma_cb =3D do_dma_pdma_cb; + esp_raise_drq(s); + return; + } + trace_esp_handle_ti_cmd(s->cmdlen); + s->ti_size =3D 0; + s->cmdlen =3D 0; + s->do_cmd =3D 0; + do_cmd(s, s->cmdbuf); return; } if (s->async_len =3D=3D 0) { + if (s->dma_left =3D=3D 0) { + esp_dma_done(s); + } /* Defer until data is available. */ return; } @@ -264,9 +406,27 @@ static void esp_do_dma(ESPState *s) } to_device =3D (s->ti_size < 0); if (to_device) { - s->dma_memory_read(s->dma_opaque, s->async_buf, len); + if (s->dma_memory_read) { + s->dma_memory_read(s->dma_opaque, s->async_buf, len); + } else { + s->pdma_len =3D len; + s->pdma_start =3D s->async_buf; + s->pdma_cur =3D s->async_buf; + s->pdma_cb =3D do_dma_pdma_cb; + esp_raise_drq(s); + return; + } } else { - s->dma_memory_write(s->dma_opaque, s->async_buf, len); + if (s->dma_memory_write) { + s->dma_memory_write(s->dma_opaque, s->async_buf, len); + } else { + s->pdma_len =3D len; + s->pdma_start =3D s->async_buf; + s->pdma_cur =3D s->async_buf; + s->pdma_cb =3D do_dma_pdma_cb; + esp_raise_drq(s); + return; + } } s->dma_left -=3D len; s->async_buf +=3D len; @@ -373,8 +533,7 @@ static void handle_ti(ESPState *s) s->dma_left =3D minlen; s->rregs[ESP_RSTAT] &=3D ~STAT_TC; esp_do_dma(s); - } - if (s->do_cmd) { + } else if (s->do_cmd) { trace_esp_handle_ti_cmd(s->cmdlen); s->ti_size =3D 0; s->cmdlen =3D 0; @@ -401,6 +560,7 @@ void esp_hard_reset(ESPState *s) static void esp_soft_reset(ESPState *s) { qemu_irq_lower(s->irq); + qemu_irq_lower(s->irq_data); esp_hard_reset(s); } =20 @@ -641,6 +801,80 @@ static const MemoryRegionOps sysbus_esp_mem_ops =3D { .valid.accepts =3D esp_mem_accepts, }; =20 +static void sysbus_esp_pdma_write(void *opaque, hwaddr addr, + uint64_t val, unsigned int size) +{ + SysBusESPState *sysbus =3D opaque; + ESPState *s =3D &sysbus->esp; + uint32_t dmalen; + + dmalen =3D s->rregs[ESP_TCLO]; + dmalen |=3D s->rregs[ESP_TCMID] << 8; + dmalen |=3D s->rregs[ESP_TCHI] << 16; + if (dmalen =3D=3D 0 || s->pdma_len =3D=3D 0) { + return; + } + switch (size) { + case 1: + *s->pdma_cur++ =3D val; + s->pdma_len--; + dmalen--; + break; + case 2: + *s->pdma_cur++ =3D val >> 8; + *s->pdma_cur++ =3D val; + s->pdma_len -=3D 2; + dmalen -=3D 2; + break; + } + s->rregs[ESP_TCLO] =3D dmalen & 0xff; + s->rregs[ESP_TCMID] =3D dmalen >> 8; + s->rregs[ESP_TCHI] =3D dmalen >> 16; + if (s->pdma_len =3D=3D 0 && s->pdma_cb) { + esp_lower_drq(s); + s->pdma_cb(s); + s->pdma_cb =3D NULL; + } +} + +static uint64_t sysbus_esp_pdma_read(void *opaque, hwaddr addr, + unsigned int size) +{ + SysBusESPState *sysbus =3D opaque; + ESPState *s =3D &sysbus->esp; + uint64_t val =3D 0; + + if (s->pdma_len =3D=3D 0) { + return 0; + } + switch (size) { + case 1: + val =3D *s->pdma_cur++; + s->pdma_len--; + break; + case 2: + val =3D *s->pdma_cur++; + val =3D (val << 8) | *s->pdma_cur++; + s->pdma_len -=3D 2; + break; + } + + if (s->pdma_len =3D=3D 0 && s->pdma_cb) { + esp_lower_drq(s); + s->pdma_cb(s); + s->pdma_cb =3D NULL; + } + return val; +} + +static const MemoryRegionOps sysbus_esp_pdma_ops =3D { + .read =3D sysbus_esp_pdma_read, + .write =3D sysbus_esp_pdma_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid.min_access_size =3D 1, + .valid.max_access_size =3D 2, +}; + static const struct SCSIBusInfo esp_scsi_info =3D { .tcq =3D false, .max_target =3D ESP_MAX_DEVS, @@ -673,12 +907,16 @@ static void sysbus_esp_realize(DeviceState *dev, Erro= r **errp) ESPState *s =3D &sysbus->esp; =20 sysbus_init_irq(sbd, &s->irq); + sysbus_init_irq(sbd, &s->irq_data); assert(sysbus->it_shift !=3D -1); =20 s->chip_id =3D TCHI_FAS100A; memory_region_init_io(&sysbus->iomem, OBJECT(sysbus), &sysbus_esp_mem_= ops, - sysbus, "esp", ESP_REGS << sysbus->it_shift); + sysbus, "esp-regs", ESP_REGS << sysbus->it_shift= ); sysbus_init_mmio(sbd, &sysbus->iomem); + memory_region_init_io(&sysbus->pdma, OBJECT(sysbus), &sysbus_esp_pdma_= ops, + sysbus, "esp-pdma", 2); + sysbus_init_mmio(sbd, &sysbus->pdma); =20 qdev_init_gpio_in(dev, sysbus_esp_gpio_demux, 2); =20 diff --git a/include/hw/scsi/esp.h b/include/hw/scsi/esp.h index adab63d1c9..b19b86b27a 100644 --- a/include/hw/scsi/esp.h +++ b/include/hw/scsi/esp.h @@ -18,6 +18,7 @@ struct ESPState { uint8_t rregs[ESP_REGS]; uint8_t wregs[ESP_REGS]; qemu_irq irq; + qemu_irq irq_data; uint8_t chip_id; bool tchi_written; int32_t ti_size; @@ -48,6 +49,11 @@ struct ESPState { ESPDMAMemoryReadWriteFunc dma_memory_write; void *dma_opaque; void (*dma_cb)(ESPState *s); + uint8_t pdma_buf[32]; + uint32_t pdma_len; + uint8_t *pdma_start; + uint8_t *pdma_cur; + void (*pdma_cb)(ESPState *s); }; =20 #define TYPE_ESP "esp" @@ -59,6 +65,7 @@ typedef struct { /*< public >*/ =20 MemoryRegion iomem; + MemoryRegion pdma; uint32_t it_shift; ESPState esp; } SysBusESPState; --=20 2.21.0 From nobody Sun May 5 04:16:47 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1568044938; cv=none; d=zoho.com; s=zohoarc; b=ci4OBwJsIwac5Gy2hzxo9f1FlMulfBkhp0TfRQds6sJGT3vnCq1OTpIHKAQHccDFBchbapRXUFe+nAFPCx/mbJ5w1CiW46XTBJnfu7yaFh96RqyolHaKXyNn8brJjyUsvpEBt5zTgkujsnPekZGDcl0aUx5ResOLTWbeayuodcY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1568044938; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=Of56RIXPrSw+khoyg7zKYPtfFKOk1kMymis7ChWPK4o=; b=YsdDkKSw6/NY8+4flxto4DYXBz28v14GTCuxn0irBfKkJRJmJOPrJ6J+XtXDKtRqMEmTpscbSz2XF6WQms0r6ihzQYFYinvAmScYA03rtrVRg5bcPT6fPyU8Gn3crZqpSnCrrOm+cM2+aC+hZhep3mEang6JRKTzgbaPBG614HE= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1568044938005287.3223644913967; Mon, 9 Sep 2019 09:02:18 -0700 (PDT) Received: from localhost ([::1]:58404 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i7M7H-0001tO-EL for importer@patchew.org; Mon, 09 Sep 2019 12:02:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59562) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i7M4A-0008Oo-4m for qemu-devel@nongnu.org; Mon, 09 Sep 2019 11:59:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i7M48-0001c2-6P for qemu-devel@nongnu.org; Mon, 09 Sep 2019 11:58:58 -0400 Received: from mout.kundenserver.de ([212.227.126.135]:55175) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i7M47-0001b6-SJ; Mon, 09 Sep 2019 11:58:56 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue010 [212.227.15.167]) with ESMTPSA (Nemesis) id 1Macf4-1iiLUz3dbG-00cCBz; Mon, 09 Sep 2019 17:58:24 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Mon, 9 Sep 2019 17:58:06 +0200 Message-Id: <20190909155813.27760-3-laurent@vivier.eu> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190909155813.27760-1-laurent@vivier.eu> References: <20190909155813.27760-1-laurent@vivier.eu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K1:8uJDAP5+hWS+aWU8lEZZxs3h5s/dKlp2Ndd8c9qGg+i7VNqfAd/ 5KOa46rYkfva1tJPuMgFMC+M4nlSUNs+77LKB8m0dMYbwaOT0HMKAMAWrvqXPDKQ4pWTlMX MFd23y2Mef6LhLF/QAuliOJzFeh6BV1B6Yf+kHlMq3VjEmeqHXi9Ie02OzNrdIs3NBxqIyj DzX36HVN2tvCiEACynk7A== X-UI-Out-Filterresults: notjunk:1;V03:K0:BhffS3RVPYU=:fxikQw3eqOHY1dOF1uayU+ Ff8E6zExHQnec7LlGYUy5A3ukCE90fyFi8yjMgF9yc31zzO6iyixjHG+AExb6JqEnxYGQHugZ b4oGxXvB8BQ8Lr3jcRUGHPVfkSctbHb+Pjmkl9jKlJSCoyzGKrZ3RvdFqoqwqoTUZYIvnQopG qtjtZK4L8I/RQiFSxyNO/8J1n+xXzJPO3UjuwYqlVUmncGA2pTyU9u1awufdazAUUaFCbyoN2 enHjlG0EfWIqX+1UC+pvjjU5CwiMfS7wr8YGvGHRmdWo1x8IP47vqeXaLc8J7QXLS8aaYgtLS uNiMWhIzS2X1XHbXNWrNeC7LC2yXXdRh/oWQt5RUQ8H32w/xgOO+ek/03oBF5sYSdv5GJ+8MD zddws5sKn5WthXvGQ21MHz/Zp9bf7i2fxHDnfcQtVjHimKAZaCSso1+s+Vz8w8OglZ49ARu1c Qb95IJ1hK81himzwwyvPevVGcobRmKkw+c3GNAD6MHmVYyaJkPKfS/itBo9WIywHik0yBqjt1 6VFgVR0ZrMeJVIql/cq5haXJ7NzvlVUpCEy7idkXCVCx9ER6pxgVYUFb9YS/yMFDDvg/C14u9 Obr5LM6q7o3V4/8kG3JHbdZVAw7iSfdA7Ibo94RHX1eWvDfpe8F9RLsJ/fdQC6YhYXGiJkPmJ TEwwOiSYGHCFtf6DkhQhNmI7KDWzPwGf/PmP0RO274BCzazDYHnjjV++5+1fyoDx/jAWRG6Gf wg8nl/CTnUX0O26MPgpPqgRb+EJ+8nyPHtTteDNJMby1L0uIuBlh1mv2eECabUXhtnhaLJSeX RMjmhQuMNbT18WJT4aZ+noV06p7iNWUpkWgtGZuuca0Ed6IPDY= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 212.227.126.135 Subject: [Qemu-devel] [PATCH v9 2/9] dp8393x: manage big endian bus X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Kevin Wolf , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-block@nongnu.org, Thomas Huth , Jason Wang , Mark Cave-Ayland , "Dr . David Alan Gilbert" , Max Reitz , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Gerd Hoffmann , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Paolo Bonzini , Aurelien Jarno , Laurent Vivier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" This is needed by Quadra 800, this card can run on little-endian or big-endian bus. Signed-off-by: Laurent Vivier Tested-by: Herv=C3=A9 Poussineau Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Herv=C3=A9 Poussineau --- hw/net/dp8393x.c | 88 +++++++++++++++++++++++++++++++----------------- 1 file changed, 57 insertions(+), 31 deletions(-) diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c index a5678e11fa..693e244ce6 100644 --- a/hw/net/dp8393x.c +++ b/hw/net/dp8393x.c @@ -153,6 +153,7 @@ typedef struct dp8393xState { =20 /* Hardware */ uint8_t it_shift; + bool big_endian; qemu_irq irq; #ifdef DEBUG_SONIC int irq_level; @@ -223,6 +224,29 @@ static uint32_t dp8393x_wt(dp8393xState *s) return s->regs[SONIC_WT1] << 16 | s->regs[SONIC_WT0]; } =20 +static uint16_t dp8393x_get(dp8393xState *s, int width, uint16_t *base, + int offset) +{ + uint16_t val; + + if (s->big_endian) { + val =3D be16_to_cpu(base[offset * width + width - 1]); + } else { + val =3D le16_to_cpu(base[offset * width]); + } + return val; +} + +static void dp8393x_put(dp8393xState *s, int width, uint16_t *base, int of= fset, + uint16_t val) +{ + if (s->big_endian) { + base[offset * width + width - 1] =3D cpu_to_be16(val); + } else { + base[offset * width] =3D cpu_to_le16(val); + } +} + static void dp8393x_update_irq(dp8393xState *s) { int level =3D (s->regs[SONIC_IMR] & s->regs[SONIC_ISR]) ? 1 : 0; @@ -254,12 +278,12 @@ static void dp8393x_do_load_cam(dp8393xState *s) /* Fill current entry */ address_space_rw(&s->as, dp8393x_cdp(s), MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0); - s->cam[index][0] =3D data[1 * width] & 0xff; - s->cam[index][1] =3D data[1 * width] >> 8; - s->cam[index][2] =3D data[2 * width] & 0xff; - s->cam[index][3] =3D data[2 * width] >> 8; - s->cam[index][4] =3D data[3 * width] & 0xff; - s->cam[index][5] =3D data[3 * width] >> 8; + s->cam[index][0] =3D dp8393x_get(s, width, data, 1) & 0xff; + s->cam[index][1] =3D dp8393x_get(s, width, data, 1) >> 8; + s->cam[index][2] =3D dp8393x_get(s, width, data, 2) & 0xff; + s->cam[index][3] =3D dp8393x_get(s, width, data, 2) >> 8; + s->cam[index][4] =3D dp8393x_get(s, width, data, 3) & 0xff; + s->cam[index][5] =3D dp8393x_get(s, width, data, 3) >> 8; DPRINTF("load cam[%d] with %02x%02x%02x%02x%02x%02x\n", index, s->cam[index][0], s->cam[index][1], s->cam[index][2], s->cam[index][3], s->cam[index][4], s->cam[index][5]); @@ -272,7 +296,7 @@ static void dp8393x_do_load_cam(dp8393xState *s) /* Read CAM enable */ address_space_rw(&s->as, dp8393x_cdp(s), MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0); - s->regs[SONIC_CE] =3D data[0 * width]; + s->regs[SONIC_CE] =3D dp8393x_get(s, width, data, 0); DPRINTF("load cam done. cam enable mask 0x%04x\n", s->regs[SONIC_CE]); =20 /* Done */ @@ -293,10 +317,10 @@ static void dp8393x_do_read_rra(dp8393xState *s) MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0); =20 /* Update SONIC registers */ - s->regs[SONIC_CRBA0] =3D data[0 * width]; - s->regs[SONIC_CRBA1] =3D data[1 * width]; - s->regs[SONIC_RBWC0] =3D data[2 * width]; - s->regs[SONIC_RBWC1] =3D data[3 * width]; + s->regs[SONIC_CRBA0] =3D dp8393x_get(s, width, data, 0); + s->regs[SONIC_CRBA1] =3D dp8393x_get(s, width, data, 1); + s->regs[SONIC_RBWC0] =3D dp8393x_get(s, width, data, 2); + s->regs[SONIC_RBWC1] =3D dp8393x_get(s, width, data, 3); DPRINTF("CRBA0/1: 0x%04x/0x%04x, RBWC0/1: 0x%04x/0x%04x\n", s->regs[SONIC_CRBA0], s->regs[SONIC_CRBA1], s->regs[SONIC_RBWC0], s->regs[SONIC_RBWC1]); @@ -411,12 +435,12 @@ static void dp8393x_do_transmit_packets(dp8393xState = *s) tx_len =3D 0; =20 /* Update registers */ - s->regs[SONIC_TCR] =3D data[0 * width] & 0xf000; - s->regs[SONIC_TPS] =3D data[1 * width]; - s->regs[SONIC_TFC] =3D data[2 * width]; - s->regs[SONIC_TSA0] =3D data[3 * width]; - s->regs[SONIC_TSA1] =3D data[4 * width]; - s->regs[SONIC_TFS] =3D data[5 * width]; + s->regs[SONIC_TCR] =3D dp8393x_get(s, width, data, 0) & 0xf000; + s->regs[SONIC_TPS] =3D dp8393x_get(s, width, data, 1); + s->regs[SONIC_TFC] =3D dp8393x_get(s, width, data, 2); + s->regs[SONIC_TSA0] =3D dp8393x_get(s, width, data, 3); + s->regs[SONIC_TSA1] =3D dp8393x_get(s, width, data, 4); + s->regs[SONIC_TFS] =3D dp8393x_get(s, width, data, 5); =20 /* Handle programmable interrupt */ if (s->regs[SONIC_TCR] & SONIC_TCR_PINT) { @@ -442,9 +466,9 @@ static void dp8393x_do_transmit_packets(dp8393xState *s) address_space_rw(&s->as, dp8393x_ttda(s) + sizeof(uint16_t) * (4 + 3 * i) * wid= th, MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0); - s->regs[SONIC_TSA0] =3D data[0 * width]; - s->regs[SONIC_TSA1] =3D data[1 * width]; - s->regs[SONIC_TFS] =3D data[2 * width]; + s->regs[SONIC_TSA0] =3D dp8393x_get(s, width, data, 0); + s->regs[SONIC_TSA1] =3D dp8393x_get(s, width, data, 1); + s->regs[SONIC_TFS] =3D dp8393x_get(s, width, data, 2); } } =20 @@ -471,7 +495,8 @@ static void dp8393x_do_transmit_packets(dp8393xState *s) s->regs[SONIC_TCR] |=3D SONIC_TCR_PTX; =20 /* Write status */ - data[0 * width] =3D s->regs[SONIC_TCR] & 0x0fff; /* status */ + dp8393x_put(s, width, data, 0, + s->regs[SONIC_TCR] & 0x0fff); /* status */ size =3D sizeof(uint16_t) * width; address_space_rw(&s->as, dp8393x_ttda(s), @@ -485,8 +510,8 @@ static void dp8393x_do_transmit_packets(dp8393xState *s) sizeof(uint16_t) * (4 + 3 * s->regs[SONIC_TFC]) * width, MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0); - s->regs[SONIC_CTDA] =3D data[0 * width] & ~0x1; - if (data[0 * width] & 0x1) { + s->regs[SONIC_CTDA] =3D dp8393x_get(s, width, data, 0) & ~0x1; + if (dp8393x_get(s, width, data, 0) & 0x1) { /* EOL detected */ break; } @@ -749,7 +774,7 @@ static ssize_t dp8393x_receive(NetClientState *nc, cons= t uint8_t * buf, address =3D dp8393x_crda(s) + sizeof(uint16_t) * 5 * width; address_space_rw(&s->as, address, MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0); - if (data[0 * width] & 0x1) { + if (dp8393x_get(s, width, data, 0) & 0x1) { /* Still EOL ; stop reception */ return -1; } else { @@ -793,11 +818,11 @@ static ssize_t dp8393x_receive(NetClientState *nc, co= nst uint8_t * buf, =20 /* Write status to memory */ DPRINTF("Write status at %08x\n", dp8393x_crda(s)); - data[0 * width] =3D s->regs[SONIC_RCR]; /* status */ - data[1 * width] =3D rx_len; /* byte count */ - data[2 * width] =3D s->regs[SONIC_TRBA0]; /* pkt_ptr0 */ - data[3 * width] =3D s->regs[SONIC_TRBA1]; /* pkt_ptr1 */ - data[4 * width] =3D s->regs[SONIC_RSC]; /* seq_no */ + dp8393x_put(s, width, data, 0, s->regs[SONIC_RCR]); /* status */ + dp8393x_put(s, width, data, 1, rx_len); /* byte count */ + dp8393x_put(s, width, data, 2, s->regs[SONIC_TRBA0]); /* pkt_ptr0 */ + dp8393x_put(s, width, data, 3, s->regs[SONIC_TRBA1]); /* pkt_ptr1 */ + dp8393x_put(s, width, data, 4, s->regs[SONIC_RSC]); /* seq_no */ size =3D sizeof(uint16_t) * 5 * width; address_space_rw(&s->as, dp8393x_crda(s), MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 1); @@ -806,12 +831,12 @@ static ssize_t dp8393x_receive(NetClientState *nc, co= nst uint8_t * buf, size =3D sizeof(uint16_t) * width; address_space_rw(&s->as, dp8393x_crda(s) + sizeof(uint16_t) * 5 * widt= h, MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0); - s->regs[SONIC_LLFA] =3D data[0 * width]; + s->regs[SONIC_LLFA] =3D dp8393x_get(s, width, data, 0); if (s->regs[SONIC_LLFA] & 0x1) { /* EOL detected */ s->regs[SONIC_ISR] |=3D SONIC_ISR_RDE; } else { - data[0 * width] =3D 0; /* in_use */ + dp8393x_put(s, width, data, 0, 0); /* in_use */ address_space_rw(&s->as, dp8393x_crda(s) + sizeof(uint16_t) * 6 * = width, MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, sizeof(uint16_t), 1); s->regs[SONIC_CRDA] =3D s->regs[SONIC_LLFA]; @@ -924,6 +949,7 @@ static Property dp8393x_properties[] =3D { DEFINE_NIC_PROPERTIES(dp8393xState, conf), DEFINE_PROP_PTR("dma_mr", dp8393xState, dma_mr), DEFINE_PROP_UINT8("it_shift", dp8393xState, it_shift, 0), + DEFINE_PROP_BOOL("big_endian", dp8393xState, big_endian, false), DEFINE_PROP_END_OF_LIST(), }; =20 --=20 2.21.0 From nobody Sun May 5 04:16:47 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1568045392; cv=none; d=zoho.com; s=zohoarc; b=gGJEWALAU3QXBvsN1VypBhcRIV0cLUj10zYSRllbYoQog/LTXYL56Es/zSGIui9be/IhNFMVyLDHdCfGjWYaRX7nNdh7Zx1BirtWW7ptaBMKT7Dc0UD/9YW3FMBq56nCnzL79ylfj4oLulz5wRBuCX7LR6cr+vC+aSx+ltyEAXc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1568045392; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=5TVmWbLUHEEyX3eoYSmRvNLbrp7LW0xgB7T/Dwo0B1k=; b=GyfoFOrJ/J1B3JRtifs9N43MaKSfnMd+h5/RPJyVGadkJDZEeA4kCOLYRaN8g0duhIsujX5+1S1QAE2sUBGM0KuK/K5eNzDNLAuSzqV4iQXEIv/sF8Mc9oFkd9p123/jvzi1Po9MquZ0LQX7P9XrJzeUQU1JuR5tvBJxMRZ4ql4= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1568045392403338.0790990627821; Mon, 9 Sep 2019 09:09:52 -0700 (PDT) Received: from localhost ([::1]:58604 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i7MEh-0002d8-7l for importer@patchew.org; Mon, 09 Sep 2019 12:09:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59879) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i7M4k-0000TV-Bh for qemu-devel@nongnu.org; Mon, 09 Sep 2019 11:59:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i7M4g-0001we-L6 for qemu-devel@nongnu.org; Mon, 09 Sep 2019 11:59:34 -0400 Received: from mout.kundenserver.de ([212.227.126.187]:52669) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i7M4X-0001ra-N3; Mon, 09 Sep 2019 11:59:22 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue010 [212.227.15.167]) with ESMTPSA (Nemesis) id 1N5max-1iDhhB19n1-017BIs; Mon, 09 Sep 2019 17:58:27 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Mon, 9 Sep 2019 17:58:07 +0200 Message-Id: <20190909155813.27760-4-laurent@vivier.eu> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190909155813.27760-1-laurent@vivier.eu> References: <20190909155813.27760-1-laurent@vivier.eu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K1:jc/w3a2hbPMlbzuWICDpwHT1r34ONHsn/iwV0f1qgUbEz232m1t 3zAYQNAnNUkEkcKYK4FphWZsvstrLR5uc3UaskOayziu8gikvQZNQq91BL/cg+rGNhW6JMT 7HndfLXMSC9sx9zq0sl0+lgGGu8uZNw2dM7YX4+jWW02M02o014GGEoqmEY6uaaGdow2+LI DLjhq9TXWzcH8Teh8sBtg== X-UI-Out-Filterresults: notjunk:1;V03:K0:LJ57NGq0ki8=:EzFk/vg44lcWGsc/MOnxCa 8azY+i/dTCmfzOczds/lde53iMP8504prrCOWAVBBcNwfcCM21QIhQwJHMCfdAs8U5w0fd9FT YZpj9Cai8H60cqlzHFYH9rQ0Fq1su/lilPU+v/mxpvTSB/4Ms33a51tbTT86OujIfdjb1xITi aColVBZB5Ogiwq25Ds5Fcmubg8trCc3j9/cZESrwdoCbHGbaJGUdJW1cJ8MaDVTpijxJKzOIF PkGjJStigr/ula0IJN6VsE23CbbLtavlcwyV9mnGoPvDpuUgW6twU6ie8wp7cCluA98lZszCP PExr2GIvoHXTIKxnNpPBQ3NQ5x2pncmRxTWs/iMrrZ2q4BU/AHQhkq6kFatNUiFgC4x6A7sph oVSFYDHWC9Utu09qoEMBla9ETCGc10No8KXD5uc6967EwhwmqjbkiEaQzPAj3ZhFhdTbszbM5 mY/pOZwVFAucUaC5uj0fdJgtl6yLAfM1wlHCKdmVtz4Fvo/APMgvIvdQ4N1Y6AkoO1kIIuZJ1 MIavH6wpC4WbrvZHZRB272k2ivnPpyC5yoaxy3AEq5+IiPaEWIqJXAL/zIdU2I2hCYkmF1zq1 TILflJ4/YndHlEsL0xjbWg5suDmeqb+PQQOfF/yFocomGESaYsnCIM634yQEt34EdXvPzB5fb qrajYJeyC8cGRlo36IIYdfFrwpvszllnMGyFYK873t8q1Ek6b7LBgvDTxheoKfviOQhYeFrPo KakafkgOLOphKMkKzv6sjvnFZ/xuoK/LFQYqlz3ZIxdN41jGgkETgS/Jlr8d1Dqa9gVK2Rt23 LleCUT7Zzh1ttyM5ZGk1Zg9w3La/QD0TR8fPRh/KNiNA4ulpuA= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 212.227.126.187 Subject: [Qemu-devel] [PATCH v9 3/9] hw/m68k: add via support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Kevin Wolf , qemu-block@nongnu.org, Thomas Huth , Jason Wang , Mark Cave-Ayland , "Dr . David Alan Gilbert" , Max Reitz , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Gerd Hoffmann , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Paolo Bonzini , Aurelien Jarno , Laurent Vivier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Co-developed-by: Mark Cave-Ayland Signed-off-by: Mark Cave-Ayland Signed-off-by: Laurent Vivier Reviewed-by: Herv=C3=A9 Poussineau --- hw/misc/Kconfig | 4 + hw/misc/Makefile.objs | 1 + hw/misc/mac_via.c | 692 ++++++++++++++++++++++++++++++++++++++ include/hw/misc/mac_via.h | 107 ++++++ 4 files changed, 804 insertions(+) create mode 100644 hw/misc/mac_via.c create mode 100644 include/hw/misc/mac_via.h diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index 51754bb47c..18a5dc9c09 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -120,4 +120,8 @@ config AUX config UNIMP bool =20 +config MAC_VIA + bool + select MOS6522 + source macio/Kconfig diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index e4aad707fb..c4836dd5c3 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -76,6 +76,7 @@ obj-$(CONFIG_PVPANIC) +=3D pvpanic.o obj-$(CONFIG_AUX) +=3D auxbus.o obj-$(CONFIG_ASPEED_SOC) +=3D aspeed_xdma.o obj-$(CONFIG_ASPEED_SOC) +=3D aspeed_scu.o aspeed_sdmc.o +obj-$(CONFIG_MAC_VIA) +=3D mac_via.o obj-$(CONFIG_MSF2) +=3D msf2-sysreg.o obj-$(CONFIG_NRF51_SOC) +=3D nrf51_rng.o =20 diff --git a/hw/misc/mac_via.c b/hw/misc/mac_via.c new file mode 100644 index 0000000000..64914b806e --- /dev/null +++ b/hw/misc/mac_via.c @@ -0,0 +1,692 @@ +/* + * QEMU m68k Macintosh VIA device support + * + * Copyright (c) 2011-2018 Laurent Vivier + * Copyright (c) 2018 Mark Cave-Ayland + * + * Some parts from hw/misc/macio/cuda.c + * + * Copyright (c) 2004-2007 Fabrice Bellard + * Copyright (c) 2007 Jocelyn Mayer + * + * some parts from linux-2.6.29, arch/m68k/include/asm/mac_via.h + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "hw/sysbus.h" +#include "hw/irq.h" +#include "qemu/timer.h" +#include "hw/misc/mac_via.h" +#include "hw/misc/mos6522.h" +#include "hw/input/adb.h" +#include "sysemu/runstate.h" +#include "qapi/error.h" +#include "qemu/cutils.h" + + +/* + * VIAs: There are two in every machine, + */ + +#define VIA_SIZE (0x2000) + +/* + * Not all of these are true post MacII I think. + * CSA: probably the ones CHRP marks as 'unused' change purposes + * when the IWM becomes the SWIM. + * http://www.rs6000.ibm.com/resource/technology/chrpio/via5.mak.html + * ftp://ftp.austin.ibm.com/pub/technology/spec/chrp/inwork/CHRP_IORef_1.0= .pdf + * + * also, http://developer.apple.com/technotes/hw/hw_09.html claims the + * following changes for IIfx: + * VIA1A_vSccWrReq not available and that VIA1A_vSync has moved to an IOP. + * Also, "All of the functionality of VIA2 has been moved to other chips". + */ + +#define VIA1A_vSccWrReq 0x80 /* + * SCC write. (input) + * [CHRP] SCC WREQ: Reflects the state of t= he + * Wait/Request pins from the SCC. + * [Macintosh Family Hardware] + * as CHRP on SE/30,II,IIx,IIcx,IIci. + * on IIfx, "0 means an active request" + */ +#define VIA1A_vRev8 0x40 /* + * Revision 8 board ??? + * [CHRP] En WaitReqB: Lets the WaitReq_L + * signal from port B of the SCC appear on + * the PA7 input pin. Output. + * [Macintosh Family] On the SE/30, this + * is the bit to flip screen buffers. + * 0=3Dalternate, 1=3Dmain. + * on II,IIx,IIcx,IIci,IIfx this is a bit + * for Rev ID. 0=3DII,IIx, 1=3DIIcx,IIci,II= fx + */ +#define VIA1A_vHeadSel 0x20 /* + * Head select for IWM. + * [CHRP] unused. + * [Macintosh Family] "Floppy disk + * state-control line SEL" on all but IIfx + */ +#define VIA1A_vOverlay 0x10 /* + * [Macintosh Family] On SE/30,II,IIx,IIcx + * this bit enables the "Overlay" address + * map in the address decoders as it is on + * reset for mapping the ROM over the reset + * vector. 1=3Duse overlay map. + * On the IIci,IIfx it is another bit of the + * CPU ID: 0=3Dnormal IIci, 1=3DIIci with p= arity + * feature or IIfx. + * [CHRP] En WaitReqA: Lets the WaitReq_L + * signal from port A of the SCC appear + * on the PA7 input pin (CHRP). Output. + * [MkLinux] "Drive Select" + * (with 0x20 being 'disk head select') + */ +#define VIA1A_vSync 0x08 /* + * [CHRP] Sync Modem: modem clock select: + * 1: select the external serial clock to + * drive the SCC's /RTxCA pin. + * 0: Select the 3.6864MHz clock to drive + * the SCC cell. + * [Macintosh Family] Correct on all but II= fx + */ + +/* + * Macintosh Family Hardware sez: bits 0-2 of VIA1A are volume control + * on Macs which had the PWM sound hardware. Reserved on newer models. + * On IIci,IIfx, bits 1-2 are the rest of the CPU ID: + * bit 2: 1=3DIIci, 0=3DIIfx + * bit 1: 1 on both IIci and IIfx. + * MkLinux sez bit 0 is 'burnin flag' in this case. + * CHRP sez: VIA1A bits 0-2 and 5 are 'unused': if programmed as + * inputs, these bits will read 0. + */ +#define VIA1A_vVolume 0x07 /* Audio volume mask for PWM */ +#define VIA1A_CPUID0 0x02 /* CPU id bit 0 on RBV, others */ +#define VIA1A_CPUID1 0x04 /* CPU id bit 0 on RBV, others */ +#define VIA1A_CPUID2 0x10 /* CPU id bit 0 on RBV, others */ +#define VIA1A_CPUID3 0x40 /* CPU id bit 0 on RBV, others */ + +/* + * Info on VIA1B is from Macintosh Family Hardware & MkLinux. + * CHRP offers no info. + */ +#define VIA1B_vSound 0x80 /* + * Sound enable (for compatibility with + * PWM hardware) 0=3Denabled. + * Also, on IIci w/parity, shows parity err= or + * 0=3Derror, 1=3DOK. + */ +#define VIA1B_vMystery 0x40 /* + * On IIci, parity enable. 0=3Denabled,1=3D= disabled + * On SE/30, vertical sync interrupt enable. + * 0=3Denabled. This vSync interrupt shows = up + * as a slot $E interrupt. + */ +#define VIA1B_vADBS2 0x20 /* ADB state input bit 1 (unused on IIfx) */ +#define VIA1B_vADBS1 0x10 /* ADB state input bit 0 (unused on IIfx) */ +#define VIA1B_vADBInt 0x08 /* ADB interrupt 0=3Dinterrupt (unused on I= Ifx)*/ +#define VIA1B_vRTCEnb 0x04 /* Enable Real time clock. 0=3Denabled. */ +#define VIA1B_vRTCClk 0x02 /* Real time clock serial-clock line. */ +#define VIA1B_vRTCData 0x01 /* Real time clock serial-data line. */ + +/* + * VIA2 A register is the interrupt lines raised off the nubus + * slots. + * The below info is from 'Macintosh Family Hardware.' + * MkLinux calls the 'IIci internal video IRQ' below the 'RBV slot 0 = irq.' + * It also notes that the slot $9 IRQ is the 'Ethernet IRQ' and + * defines the 'Video IRQ' as 0x40 for the 'EVR' VIA work-alike. + * Perhaps OSS uses vRAM1 and vRAM2 for ADB. + */ + +#define VIA2A_vRAM1 0x80 /* RAM size bit 1 (IIci: reserved) */ +#define VIA2A_vRAM0 0x40 /* RAM size bit 0 (IIci: internal video IRQ= ) */ +#define VIA2A_vIRQE 0x20 /* IRQ from slot $E */ +#define VIA2A_vIRQD 0x10 /* IRQ from slot $D */ +#define VIA2A_vIRQC 0x08 /* IRQ from slot $C */ +#define VIA2A_vIRQB 0x04 /* IRQ from slot $B */ +#define VIA2A_vIRQA 0x02 /* IRQ from slot $A */ +#define VIA2A_vIRQ9 0x01 /* IRQ from slot $9 */ + +/* + * RAM size bits decoded as follows: + * bit1 bit0 size of ICs in bank A + * 0 0 256 kbit + * 0 1 1 Mbit + * 1 0 4 Mbit + * 1 1 16 Mbit + */ + +/* + * Register B has the fun stuff in it + */ + +#define VIA2B_vVBL 0x80 /* + * VBL output to VIA1 (60.15Hz) driven by + * timer T1. + * on IIci, parity test: 0=3Dtest mode. + * [MkLinux] RBV_PARODD: 1=3Dodd,0=3Deven. + */ +#define VIA2B_vSndJck 0x40 /* + * External sound jack status. + * 0=3Dplug is inserted. On SE/30, always 0 + */ +#define VIA2B_vTfr0 0x20 /* Transfer mode bit 0 ack from NuBus */ +#define VIA2B_vTfr1 0x10 /* Transfer mode bit 1 ack from NuBus */ +#define VIA2B_vMode32 0x08 /* + * 24/32bit switch - doubles as cache flush + * on II, AMU/PMMU control. + * if AMU, 0=3D24bit to 32bit translation + * if PMMU, 1=3DPMMU is accessing page tab= le. + * on SE/30 tied low. + * on IIx,IIcx,IIfx, unused. + * on IIci/RBV, cache control. 0=3Dflush cac= he. + */ +#define VIA2B_vPower 0x04 /* + * Power off, 0=3Dshut off power. + * on SE/30 this signal sent to PDS card. + */ +#define VIA2B_vBusLk 0x02 /* + * Lock NuBus transactions, 0=3Dlocked. + * on SE/30 sent to PDS card. + */ +#define VIA2B_vCDis 0x01 /* + * Cache control. On IIci, 1=3Ddisable cache = card + * on others, 0=3Ddisable processor's instruc= tion + * and data caches. + */ + +/* interrupt flags */ + +#define IRQ_SET 0x80 + +/* common */ + +#define VIA_IRQ_TIMER1 0x40 +#define VIA_IRQ_TIMER2 0x20 + +/* + * Apple sez: http://developer.apple.com/technotes/ov/ov_04.html + * Another example of a valid function that has no ROM support is the use + * of the alternate video page for page-flipping animation. Since there + * is no ROM call to flip pages, it is necessary to go play with the + * right bit in the VIA chip (6522 Versatile Interface Adapter). + * [CSA: don't know which one this is, but it's one of 'em!] + */ + +/* + * 6522 registers - see databook. + * CSA: Assignments for VIA1 confirmed from CHRP spec. + */ + +/* partial address decode. 0xYYXX : XX part for RBV, YY part for VIA */ +/* Note: 15 VIA regs, 8 RBV regs */ + +#define vBufB 0x0000 /* [VIA/RBV] Register B */ +#define vBufAH 0x0200 /* [VIA only] Buffer A, with handshake. DON'T USE= ! */ +#define vDirB 0x0400 /* [VIA only] Data Direction Register B. */ +#define vDirA 0x0600 /* [VIA only] Data Direction Register A. */ +#define vT1CL 0x0800 /* [VIA only] Timer one counter low. */ +#define vT1CH 0x0a00 /* [VIA only] Timer one counter high. */ +#define vT1LL 0x0c00 /* [VIA only] Timer one latches low. */ +#define vT1LH 0x0e00 /* [VIA only] Timer one latches high. */ +#define vT2CL 0x1000 /* [VIA only] Timer two counter low. */ +#define vT2CH 0x1200 /* [VIA only] Timer two counter high. */ +#define vSR 0x1400 /* [VIA only] Shift register. */ +#define vACR 0x1600 /* [VIA only] Auxilary control register. */ +#define vPCR 0x1800 /* [VIA only] Peripheral control register. */ + /* + * CHRP sez never ever to *write* this. + * Mac family says never to *change* t= his. + * In fact we need to initialize it once at start. + */ +#define vIFR 0x1a00 /* [VIA/RBV] Interrupt flag register. */ +#define vIER 0x1c00 /* [VIA/RBV] Interrupt enable register. */ +#define vBufA 0x1e00 /* [VIA/RBV] register A (no handshake) */ + +/* from linux 2.6 drivers/macintosh/via-macii.c */ + +/* Bits in ACR */ + +#define VIA1ACR_vShiftCtrl 0x1c /* Shift register control b= its */ +#define VIA1ACR_vShiftExtClk 0x0c /* Shift on external clock = */ +#define VIA1ACR_vShiftOut 0x10 /* Shift out if 1 */ + +/* + * Apple Macintosh Family Hardware Refenece + * Table 19-10 ADB transaction states + */ + +#define VIA1B_vADB_StateMask (VIA1B_vADBS1 | VIA1B_vADBS2) +#define VIA1B_vADB_StateShift 4 + +#define VIA_TIMER_FREQ (783360) + +/* VIA returns time offset from Jan 1, 1904, not 1970 */ +#define RTC_OFFSET 2082844800 + + +static void via1_VBL(void *opaque) +{ + MacVIAState *m =3D opaque; + MOS6522Q800VIA1State *v1s =3D MOS6522_Q800_VIA1(&m->mos6522_via1); + MOS6522State *s =3D MOS6522(v1s); + MOS6522DeviceClass *mdc =3D MOS6522_DEVICE_GET_CLASS(s); + + s->ifr |=3D VIA1_IRQ_VBLANK; + mdc->update_irq(s); + + timer_mod(m->VBL_timer, (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 16630) + / 16630 * 16630); +} + +static void via1_one_second(void *opaque) +{ + MacVIAState *m =3D opaque; + MOS6522Q800VIA1State *v1s =3D MOS6522_Q800_VIA1(&m->mos6522_via1); + MOS6522State *s =3D MOS6522(v1s); + MOS6522DeviceClass *mdc =3D MOS6522_DEVICE_GET_CLASS(s); + + s->ifr |=3D VIA1_IRQ_ONE_SECOND; + mdc->update_irq(s); + + timer_mod(m->one_second_timer, (qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + + 1000) / 1000 * 1000); +} + +static void via1_irq_request(void *opaque, int irq, int level) +{ + MOS6522Q800VIA1State *v1s =3D opaque; + MOS6522State *s =3D MOS6522(v1s); + MOS6522DeviceClass *mdc =3D MOS6522_DEVICE_GET_CLASS(s); + + if (level) { + s->ifr |=3D 1 << irq; + } else { + s->ifr &=3D ~(1 << irq); + } + + mdc->update_irq(s); +} + +static void via2_irq_request(void *opaque, int irq, int level) +{ + MOS6522Q800VIA2State *v2s =3D opaque; + MOS6522State *s =3D MOS6522(v2s); + MOS6522DeviceClass *mdc =3D MOS6522_DEVICE_GET_CLASS(s); + + if (level) { + s->ifr |=3D 1 << irq; + } else { + s->ifr &=3D ~(1 << irq); + } + + mdc->update_irq(s); +} + +static void via1_rtc_update(MacVIAState *m) +{ + MOS6522Q800VIA1State *v1s =3D MOS6522_Q800_VIA1(&m->mos6522_via1); + MOS6522State *s =3D MOS6522(v1s); + + if (s->b & VIA1B_vRTCEnb) { + return; + } + + if (s->dirb & VIA1B_vRTCData) { + /* send bits to the RTC */ + if (!(v1s->last_b & VIA1B_vRTCClk) && (s->b & VIA1B_vRTCClk)) { + m->data_out <<=3D 1; + m->data_out |=3D s->b & VIA1B_vRTCData; + m->data_out_cnt++; + } + } else { + /* receive bits from the RTC */ + if ((v1s->last_b & VIA1B_vRTCClk) && + !(s->b & VIA1B_vRTCClk) && + m->data_in_cnt) { + s->b =3D (s->b & ~VIA1B_vRTCData) | + ((m->data_in >> 7) & VIA1B_vRTCData); + m->data_in <<=3D 1; + m->data_in_cnt--; + } + } + + if (m->data_out_cnt =3D=3D 8) { + m->data_out_cnt =3D 0; + + if (m->cmd =3D=3D 0) { + if (m->data_out & 0x80) { + /* this is a read command */ + uint32_t time =3D m->tick_offset + + (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / + NANOSECONDS_PER_SECOND); + if (m->data_out =3D=3D 0x81) { /* seconds register = 0 */ + m->data_in =3D time & 0xff; + m->data_in_cnt =3D 8; + } else if (m->data_out =3D=3D 0x85) { /* seconds register = 1 */ + m->data_in =3D (time >> 8) & 0xff; + m->data_in_cnt =3D 8; + } else if (m->data_out =3D=3D 0x89) { /* seconds register = 2 */ + m->data_in =3D (time >> 16) & 0xff; + m->data_in_cnt =3D 8; + } else if (m->data_out =3D=3D 0x8d) { /* seconds register = 3 */ + m->data_in =3D (time >> 24) & 0xff; + m->data_in_cnt =3D 8; + } else if ((m->data_out & 0xf3) =3D=3D 0xa1) { + /* PRAM address 0x10 -> 0x13 */ + int addr =3D (m->data_out >> 2) & 0x03; + m->data_in =3D v1s->PRAM[addr]; + m->data_in_cnt =3D 8; + } else if ((m->data_out & 0xf3) =3D=3D 0xa1) { + /* PRAM address 0x00 -> 0x0f */ + int addr =3D (m->data_out >> 2) & 0x0f; + m->data_in =3D v1s->PRAM[addr]; + m->data_in_cnt =3D 8; + } else if ((m->data_out & 0xf8) =3D=3D 0xb8) { + /* extended memory designator and sector number */ + m->cmd =3D m->data_out; + } + } else { + /* this is a write command */ + m->cmd =3D m->data_out; + } + } else { + if (m->cmd & 0x80) { + if ((m->cmd & 0xf8) =3D=3D 0xb8) { + /* extended memory designator and sector number */ + int sector =3D m->cmd & 0x07; + int addr =3D (m->data_out >> 2) & 0x1f; + + m->data_in =3D v1s->PRAM[sector * 8 + addr]; + m->data_in_cnt =3D 8; + } + } else if (!m->wprotect) { + /* this is a write command */ + if (m->alt !=3D 0) { + /* extended memory designator and sector number */ + int sector =3D m->cmd & 0x07; + int addr =3D (m->alt >> 2) & 0x1f; + + v1s->PRAM[sector * 8 + addr] =3D m->data_out; + + m->alt =3D 0; + } else if (m->cmd =3D=3D 0x01) { /* seconds register 0 */ + /* FIXME */ + } else if (m->cmd =3D=3D 0x05) { /* seconds register 1 */ + /* FIXME */ + } else if (m->cmd =3D=3D 0x09) { /* seconds register 2 */ + /* FIXME */ + } else if (m->cmd =3D=3D 0x0d) { /* seconds register 3 */ + /* FIXME */ + } else if (m->cmd =3D=3D 0x31) { + /* Test Register */ + } else if (m->cmd =3D=3D 0x35) { + /* Write Protect register */ + m->wprotect =3D m->data_out & 1; + } else if ((m->cmd & 0xf3) =3D=3D 0xa1) { + /* PRAM address 0x10 -> 0x13 */ + int addr =3D (m->cmd >> 2) & 0x03; + v1s->PRAM[addr] =3D m->data_out; + } else if ((m->cmd & 0xf3) =3D=3D 0xa1) { + /* PRAM address 0x00 -> 0x0f */ + int addr =3D (m->cmd >> 2) & 0x0f; + v1s->PRAM[addr] =3D m->data_out; + } else if ((m->cmd & 0xf8) =3D=3D 0xb8) { + /* extended memory designator and sector number */ + m->alt =3D m->cmd; + } + } + } + m->data_out =3D 0; + } +} + +static uint64_t mos6522_q800_via1_read(void *opaque, hwaddr addr, unsigned= size) +{ + MOS6522Q800VIA1State *s =3D MOS6522_Q800_VIA1(opaque); + MOS6522State *ms =3D MOS6522(s); + + addr =3D (addr >> 9) & 0xf; + return mos6522_read(ms, addr, size); +} + +static void mos6522_q800_via1_write(void *opaque, hwaddr addr, uint64_t va= l, + unsigned size) +{ + MOS6522Q800VIA1State *s =3D MOS6522_Q800_VIA1(opaque); + MOS6522State *ms =3D MOS6522(s); + + addr =3D (addr >> 9) & 0xf; + mos6522_write(ms, addr, val, size); +} + +static const MemoryRegionOps mos6522_q800_via1_ops =3D { + .read =3D mos6522_q800_via1_read, + .write =3D mos6522_q800_via1_write, + .endianness =3D DEVICE_BIG_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 1, + }, +}; + +static uint64_t mos6522_q800_via2_read(void *opaque, hwaddr addr, unsigned= size) +{ + MOS6522Q800VIA2State *s =3D MOS6522_Q800_VIA2(opaque); + MOS6522State *ms =3D MOS6522(s); + + addr =3D (addr >> 9) & 0xf; + return mos6522_read(ms, addr, size); +} + +static void mos6522_q800_via2_write(void *opaque, hwaddr addr, uint64_t va= l, + unsigned size) +{ + MOS6522Q800VIA2State *s =3D MOS6522_Q800_VIA2(opaque); + MOS6522State *ms =3D MOS6522(s); + + addr =3D (addr >> 9) & 0xf; + mos6522_write(ms, addr, val, size); +} + +static const MemoryRegionOps mos6522_q800_via2_ops =3D { + .read =3D mos6522_q800_via2_read, + .write =3D mos6522_q800_via2_write, + .endianness =3D DEVICE_BIG_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 1, + }, +}; + +static void mac_via_reset(DeviceState *dev) +{ + MacVIAState *m =3D MAC_VIA(dev); + + timer_mod(m->VBL_timer, (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 16630) + / 16630 * 16630); + + timer_mod(m->one_second_timer, (qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + + 1000) / 1000 * 1000); +} + +static void mac_via_realize(DeviceState *dev, Error **errp) +{ + MacVIAState *m =3D MAC_VIA(dev); + MOS6522State *ms; + struct tm tm; + + /* Init VIAs 1 and 2 */ + sysbus_init_child_obj(OBJECT(dev), "via1", &m->mos6522_via1, + sizeof(m->mos6522_via1), TYPE_MOS6522_Q800_VIA1); + + sysbus_init_child_obj(OBJECT(dev), "via2", &m->mos6522_via2, + sizeof(m->mos6522_via2), TYPE_MOS6522_Q800_VIA2); + + /* Pass through mos6522 output IRQs */ + ms =3D MOS6522(&m->mos6522_via1); + object_property_add_alias(OBJECT(dev), "irq[0]", OBJECT(ms), + SYSBUS_DEVICE_GPIO_IRQ "[0]", &error_abort); + ms =3D MOS6522(&m->mos6522_via2); + object_property_add_alias(OBJECT(dev), "irq[1]", OBJECT(ms), + SYSBUS_DEVICE_GPIO_IRQ "[0]", &error_abort); + + /* Pass through mos6522 input IRQs */ + qdev_pass_gpios(DEVICE(&m->mos6522_via1), dev, "via1-irq"); + qdev_pass_gpios(DEVICE(&m->mos6522_via2), dev, "via2-irq"); + + /* VIA 1 */ + m->one_second_timer =3D timer_new_ms(QEMU_CLOCK_VIRTUAL, via1_one_seco= nd, m); + m->VBL_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, via1_VBL, m); + + qemu_get_timedate(&tm, 0); + m->tick_offset =3D (uint32_t)mktimegm(&tm) + RTC_OFFSET; +} + +static void mac_via_init(Object *obj) +{ + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + MacVIAState *m =3D MAC_VIA(obj); + + /* MMIO */ + memory_region_init(&m->mmio, obj, "mac-via", 2 * VIA_SIZE); + sysbus_init_mmio(sbd, &m->mmio); + + memory_region_init_io(&m->via1mem, obj, &mos6522_q800_via1_ops, + &m->mos6522_via1, "via1", VIA_SIZE); + memory_region_add_subregion(&m->mmio, 0x0, &m->via1mem); + + memory_region_init_io(&m->via2mem, obj, &mos6522_q800_via2_ops, + &m->mos6522_via2, "via2", VIA_SIZE); + memory_region_add_subregion(&m->mmio, VIA_SIZE, &m->via2mem); + + /* ADB */ + qbus_create_inplace((BusState *)&m->adb_bus, sizeof(m->adb_bus), + TYPE_ADB_BUS, DEVICE(obj), "adb.0"); +} + +static void mac_via_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->realize =3D mac_via_realize; + dc->reset =3D mac_via_reset; +} + +static TypeInfo mac_via_info =3D { + .name =3D TYPE_MAC_VIA, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(MacVIAState), + .instance_init =3D mac_via_init, + .class_init =3D mac_via_class_init, +}; + +/* VIA 1 */ +static void mos6522_q800_via1_portB_write(MOS6522State *s) +{ + MOS6522Q800VIA1State *v1s =3D container_of(s, MOS6522Q800VIA1State, + parent_obj); + MacVIAState *m =3D container_of(v1s, MacVIAState, mos6522_via1); + + via1_rtc_update(m); + + v1s->last_b =3D s->b; +} + +static void mos6522_q800_via1_reset(DeviceState *dev) +{ + MOS6522State *ms =3D MOS6522(dev); + MOS6522DeviceClass *mdc =3D MOS6522_DEVICE_GET_CLASS(ms); + + mdc->parent_reset(dev); + + ms->timers[0].frequency =3D VIA_TIMER_FREQ; + ms->timers[1].frequency =3D VIA_TIMER_FREQ; + + ms->b =3D VIA1B_vADB_StateMask | VIA1B_vADBInt | VIA1B_vRTCEnb; +} + +static void mos6522_q800_via1_init(Object *obj) +{ + qdev_init_gpio_in_named(DEVICE(obj), via1_irq_request, "via1-irq", + VIA1_IRQ_NB); +} + +static void mos6522_q800_via1_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + MOS6522DeviceClass *mdc =3D MOS6522_DEVICE_CLASS(oc); + + dc->reset =3D mos6522_q800_via1_reset; + mdc->portB_write =3D mos6522_q800_via1_portB_write; +} + +static const TypeInfo mos6522_q800_via1_type_info =3D { + .name =3D TYPE_MOS6522_Q800_VIA1, + .parent =3D TYPE_MOS6522, + .instance_size =3D sizeof(MOS6522Q800VIA1State), + .instance_init =3D mos6522_q800_via1_init, + .class_init =3D mos6522_q800_via1_class_init, +}; + +/* VIA 2 */ +static void mos6522_q800_via2_portB_write(MOS6522State *s) +{ + if (s->dirb & VIA2B_vPower && (s->b & VIA2B_vPower) =3D=3D 0) { + /* shutdown */ + qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); + } +} + +static void mos6522_q800_via2_reset(DeviceState *dev) +{ + MOS6522State *ms =3D MOS6522(dev); + MOS6522DeviceClass *mdc =3D MOS6522_DEVICE_GET_CLASS(ms); + + mdc->parent_reset(dev); + + ms->timers[0].frequency =3D VIA_TIMER_FREQ; + ms->timers[1].frequency =3D VIA_TIMER_FREQ; + + ms->dirb =3D 0; + ms->b =3D 0; +} + +static void mos6522_q800_via2_init(Object *obj) +{ + qdev_init_gpio_in_named(DEVICE(obj), via2_irq_request, "via2-irq", + VIA2_IRQ_NB); +} + +static void mos6522_q800_via2_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + MOS6522DeviceClass *mdc =3D MOS6522_DEVICE_CLASS(oc); + + dc->reset =3D mos6522_q800_via2_reset; + mdc->portB_write =3D mos6522_q800_via2_portB_write; +} + +static const TypeInfo mos6522_q800_via2_type_info =3D { + .name =3D TYPE_MOS6522_Q800_VIA2, + .parent =3D TYPE_MOS6522, + .instance_size =3D sizeof(MOS6522Q800VIA2State), + .instance_init =3D mos6522_q800_via2_init, + .class_init =3D mos6522_q800_via2_class_init, +}; + +static void mac_via_register_types(void) +{ + type_register_static(&mos6522_q800_via1_type_info); + type_register_static(&mos6522_q800_via2_type_info); + type_register_static(&mac_via_info); +} + +type_init(mac_via_register_types); diff --git a/include/hw/misc/mac_via.h b/include/hw/misc/mac_via.h new file mode 100644 index 0000000000..69bdecabb0 --- /dev/null +++ b/include/hw/misc/mac_via.h @@ -0,0 +1,107 @@ +/* + * + * Copyright (c) 2011-2018 Laurent Vivier + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef HW_MISC_MAC_VIA_H +#define HW_MISC_MAC_VIA_H + +#include "exec/memory.h" +#include "hw/sysbus.h" +#include "hw/misc/mos6522.h" + + +/* VIA 1 */ +#define VIA1_IRQ_ONE_SECOND_BIT 0 +#define VIA1_IRQ_VBLANK_BIT 1 +#define VIA1_IRQ_ADB_READY_BIT 2 +#define VIA1_IRQ_ADB_DATA_BIT 3 +#define VIA1_IRQ_ADB_CLOCK_BIT 4 + +#define VIA1_IRQ_NB 8 + +#define VIA1_IRQ_ONE_SECOND (1 << VIA1_IRQ_ONE_SECOND_BIT) +#define VIA1_IRQ_VBLANK (1 << VIA1_IRQ_VBLANK_BIT) +#define VIA1_IRQ_ADB_READY (1 << VIA1_IRQ_ADB_READY_BIT) +#define VIA1_IRQ_ADB_DATA (1 << VIA1_IRQ_ADB_DATA_BIT) +#define VIA1_IRQ_ADB_CLOCK (1 << VIA1_IRQ_ADB_CLOCK_BIT) + + +#define TYPE_MOS6522_Q800_VIA1 "mos6522-q800-via1" +#define MOS6522_Q800_VIA1(obj) OBJECT_CHECK(MOS6522Q800VIA1State, (obj), \ + TYPE_MOS6522_Q800_VIA1) + +typedef struct MOS6522Q800VIA1State { + /*< private >*/ + MOS6522State parent_obj; + + qemu_irq irqs[VIA1_IRQ_NB]; + uint8_t last_b; + uint8_t PRAM[256]; +} MOS6522Q800VIA1State; + + +/* VIA 2 */ +#define VIA2_IRQ_SCSI_DATA_BIT 0 +#define VIA2_IRQ_SLOT_BIT 1 +#define VIA2_IRQ_UNUSED_BIT 2 +#define VIA2_IRQ_SCSI_BIT 3 +#define VIA2_IRQ_ASC_BIT 4 + +#define VIA2_IRQ_NB 8 + +#define VIA2_IRQ_SCSI_DATA (1 << VIA2_IRQ_SCSI_DATA_BIT) +#define VIA2_IRQ_SLOT (1 << VIA2_IRQ_SLOT_BIT) +#define VIA2_IRQ_UNUSED (1 << VIA2_IRQ_SCSI_BIT) +#define VIA2_IRQ_SCSI (1 << VIA2_IRQ_UNUSED_BIT) +#define VIA2_IRQ_ASC (1 << VIA2_IRQ_ASC_BIT) + +#define TYPE_MOS6522_Q800_VIA2 "mos6522-q800-via2" +#define MOS6522_Q800_VIA2(obj) OBJECT_CHECK(MOS6522Q800VIA2State, (obj), \ + TYPE_MOS6522_Q800_VIA2) + +typedef struct MOS6522Q800VIA2State { + /*< private >*/ + MOS6522State parent_obj; +} MOS6522Q800VIA2State; + + +#define TYPE_MAC_VIA "mac_via" +#define MAC_VIA(obj) OBJECT_CHECK(MacVIAState, (obj), TYPE_MAC_VIA) + +typedef struct MacVIAState { + SysBusDevice busdev; + + /* MMIO */ + MemoryRegion mmio; + MemoryRegion via1mem; + MemoryRegion via2mem; + + /* VIAs */ + MOS6522Q800VIA1State mos6522_via1; + MOS6522Q800VIA2State mos6522_via2; + + /* RTC */ + uint32_t tick_offset; + + uint8_t data_out; + int data_out_cnt; + uint8_t data_in; + uint8_t data_in_cnt; + uint8_t cmd; + int wprotect; + int alt; + + /* ADB */ + ADBBusState adb_bus; + + /* external timers */ + QEMUTimer *one_second_timer; + QEMUTimer *VBL_timer; + +} MacVIAState; + +#endif --=20 2.21.0 From nobody Sun May 5 04:16:47 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1568044939; cv=none; d=zoho.com; s=zohoarc; b=D101Jt2SFgHwrG4CCrB5qnR1OcHY33EGhKg9QeNC8hyU8rDpE+XGqPZTUYRBjKy7zQDa8jM/0vRMlOwC19nQIpS4A850ucDALr/U7jfj/5+WQxB7G48PH96d1t33aP3kRuaybYmO+mmhkA2BJal8sPX0LZhe5LboVXq2ucW7/Jk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1568044939; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=57MIv2g5GF2ssaqNZCfSLueVY9EbNWX76OeFvlJV3cE=; b=KcF55s+c0xU4c0hQhouCLr7SYjJq0q/k6Eah9ucQe+lQKGMudk1hqEIXIXxxHKZV4nT5Z6mcfsPcKr+jlnctWEefpdyQivkRcxdSW4nmuXIBzzSwTSrhhhiNhKxVpEmTubx/oRweFh2NYlTIFDB9pTdXyvORkwTshdZfClb1/gI= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1568044939807356.06868553148183; Mon, 9 Sep 2019 09:02:19 -0700 (PDT) Received: from localhost ([::1]:58396 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i7M7C-0001nB-Df for importer@patchew.org; Mon, 09 Sep 2019 12:02:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59549) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i7M48-0008Oh-7Y for qemu-devel@nongnu.org; Mon, 09 Sep 2019 11:58:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i7M46-0001ai-Nq for qemu-devel@nongnu.org; Mon, 09 Sep 2019 11:58:56 -0400 Received: from mout.kundenserver.de ([212.227.126.130]:45445) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i7M46-0001aA-2i; Mon, 09 Sep 2019 11:58:54 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue010 [212.227.15.167]) with ESMTPSA (Nemesis) id 1N332D-1iHZJB3d1h-013J9E; Mon, 09 Sep 2019 17:58:29 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Mon, 9 Sep 2019 17:58:08 +0200 Message-Id: <20190909155813.27760-5-laurent@vivier.eu> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190909155813.27760-1-laurent@vivier.eu> References: <20190909155813.27760-1-laurent@vivier.eu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K1:8hJHv8g+pzlaXTuaiWQ3/L3ENgIU5WSGr5thhdcx65QDk1riDKt fZeDH0+88By1rRwI9bduWXdUHVnpU6O9svgs1cmepDGWZjH21iMnxJxO1l2mTG3qFgjYItB NrqXBrfIqo26VJyPW0DY2GC7mncBQFrv6o5DAFjpaxZG84ZCwBOEJduiNf53OvNoActEbhc zPYf4F0diD8OkipaXGmlg== X-UI-Out-Filterresults: notjunk:1;V03:K0:XYmLKxYZI80=:mzrurWVHlVzLZm5QICSCt1 AEj9SWl+RQ82revjiqRDNGicV23FyWKVlGlBIeEiAjyB9pmnt+LtwsmMxfKAK8fA1t3m1FIn9 QT5zGhal23VFij1FyakPuGbedb6NBzAHJuIYRAEBhqcwymfjRzdQd0QuweyJ+oQzYDr2GmmBU vZoYPmg0AlRyvP+UhwzhbCMoz6FR/k6qK5o/ivlZmyVeJOkNsMPAgHSAMjuuP3W4shleZJ2Nn i7/OILqK0w9PHruOB2s80rIqJv9g+fpiiYFZ3xjxBl7qQHswzG6TD+dqDhlr6Y8QTnLajCCxw RlO1LiqNqy0iYQvc6g2kpTpTx2SaChulggAvNfOrRYq1mcSIR3KFi9zfZ8LtVEoUfmGYehSHS ZfFF5DgLpMVE6VmOfnIWOxxYhks2QJYYYUsk3HeEASxXWoheQEHhztP06LpPYDSsueMsysgDA HtlPmyt+Yn5N83U3UJ/SOhEL+aI1nIK/0vl6WGWxsJFDQb9kKhK8BS/zFiC1mzQoCO7jWCnFR O8h9MQV+WZnR8Dm977v1WuCZXFsGfpeDZ8WUOlc4YbVL3fI9I+P7Wijdnh/RsnoSp8g8BNz0D ltQGparADQvrtS5EPKx9t+F6z/PJy9T67veXZpVN6DvHNmtNWP5WMlVV3ABY6+0Ytt7i27a1y 7nXzFDJZcDa6/fopHbiG5HQQIa1T9ro6mBwQi2RBWssLO/dy1yehNwg7SI1lRHrVs2izdH8zh QUNSiYksUATU6yZ9HMO2Y7N6nYTb/jehCDgcb2P3/8fOyxp8I7Nj9y38j+pe9q6BzX9E0JWOw dBVy333jDOD8Hn77d1k/MACk2bxKzx3XQ8s+MN6KNS2iHSrd3s= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 212.227.126.130 Subject: [Qemu-devel] [PATCH v9 4/9] hw/m68k: implement ADB bus support for via X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Kevin Wolf , qemu-block@nongnu.org, Thomas Huth , Jason Wang , Mark Cave-Ayland , "Dr . David Alan Gilbert" , Max Reitz , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Gerd Hoffmann , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Paolo Bonzini , Aurelien Jarno , Laurent Vivier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Co-developed-by: Mark Cave-Ayland Signed-off-by: Mark Cave-Ayland Signed-off-by: Laurent Vivier Reviewed-by: Herv=C3=A9 Poussineau Reviewed-by: Thomas Huth --- hw/misc/mac_via.c | 190 ++++++++++++++++++++++++++++++++++++++ include/hw/misc/mac_via.h | 7 ++ 2 files changed, 197 insertions(+) diff --git a/hw/misc/mac_via.c b/hw/misc/mac_via.c index 64914b806e..76cb5f8883 100644 --- a/hw/misc/mac_via.c +++ b/hw/misc/mac_via.c @@ -263,10 +263,16 @@ * Table 19-10 ADB transaction states */ =20 +#define ADB_STATE_NEW 0 +#define ADB_STATE_EVEN 1 +#define ADB_STATE_ODD 2 +#define ADB_STATE_IDLE 3 + #define VIA1B_vADB_StateMask (VIA1B_vADBS1 | VIA1B_vADBS2) #define VIA1B_vADB_StateShift 4 =20 #define VIA_TIMER_FREQ (783360) +#define VIA_ADB_POLL_FREQ 50 /* XXX: not real */ =20 /* VIA returns time offset from Jan 1, 1904, not 1970 */ #define RTC_OFFSET 2082844800 @@ -448,6 +454,181 @@ static void via1_rtc_update(MacVIAState *m) } } =20 +static int adb_via_poll(MacVIAState *s, int state, uint8_t *data) +{ + if (state !=3D ADB_STATE_IDLE) { + return 0; + } + + if (s->adb_data_in_size < s->adb_data_in_index) { + return 0; + } + + if (s->adb_data_out_index !=3D 0) { + return 0; + } + + s->adb_data_in_index =3D 0; + s->adb_data_out_index =3D 0; + s->adb_data_in_size =3D adb_poll(&s->adb_bus, s->adb_data_in, 0xffff); + + if (s->adb_data_in_size) { + *data =3D s->adb_data_in[s->adb_data_in_index++]; + qemu_irq_raise(s->adb_data_ready); + } + + return s->adb_data_in_size; +} + +static int adb_via_send(MacVIAState *s, int state, uint8_t data) +{ + switch (state) { + case ADB_STATE_NEW: + s->adb_data_out_index =3D 0; + break; + case ADB_STATE_EVEN: + if ((s->adb_data_out_index & 1) =3D=3D 0) { + return 0; + } + break; + case ADB_STATE_ODD: + if (s->adb_data_out_index & 1) { + return 0; + } + break; + case ADB_STATE_IDLE: + return 0; + } + + assert(s->adb_data_out_index < sizeof(s->adb_data_out) - 1); + + s->adb_data_out[s->adb_data_out_index++] =3D data; + qemu_irq_raise(s->adb_data_ready); + return 1; +} + +static int adb_via_receive(MacVIAState *s, int state, uint8_t *data) +{ + switch (state) { + case ADB_STATE_NEW: + return 0; + + case ADB_STATE_EVEN: + if (s->adb_data_in_size <=3D 0) { + qemu_irq_raise(s->adb_data_ready); + return 0; + } + + if (s->adb_data_in_index >=3D s->adb_data_in_size) { + *data =3D 0; + qemu_irq_raise(s->adb_data_ready); + return 1; + } + + if ((s->adb_data_in_index & 1) =3D=3D 0) { + return 0; + } + + break; + + case ADB_STATE_ODD: + if (s->adb_data_in_size <=3D 0) { + qemu_irq_raise(s->adb_data_ready); + return 0; + } + + if (s->adb_data_in_index >=3D s->adb_data_in_size) { + *data =3D 0; + qemu_irq_raise(s->adb_data_ready); + return 1; + } + + if (s->adb_data_in_index & 1) { + return 0; + } + + break; + + case ADB_STATE_IDLE: + if (s->adb_data_out_index =3D=3D 0) { + return 0; + } + + s->adb_data_in_size =3D adb_request(&s->adb_bus, s->adb_data_in, + s->adb_data_out, + s->adb_data_out_index); + s->adb_data_out_index =3D 0; + s->adb_data_in_index =3D 0; + if (s->adb_data_in_size < 0) { + *data =3D 0xff; + qemu_irq_raise(s->adb_data_ready); + return -1; + } + + if (s->adb_data_in_size =3D=3D 0) { + return 0; + } + + break; + } + + assert(s->adb_data_in_index < sizeof(s->adb_data_in) - 1); + + *data =3D s->adb_data_in[s->adb_data_in_index++]; + qemu_irq_raise(s->adb_data_ready); + if (*data =3D=3D 0xff || *data =3D=3D 0) { + return 0; + } + return 1; +} + +static void via1_adb_update(MacVIAState *m) +{ + MOS6522Q800VIA1State *v1s =3D MOS6522_Q800_VIA1(&m->mos6522_via1); + MOS6522State *s =3D MOS6522(v1s); + int state; + int ret; + + state =3D (s->b & VIA1B_vADB_StateMask) >> VIA1B_vADB_StateShift; + + if (s->acr & VIA1ACR_vShiftOut) { + /* output mode */ + ret =3D adb_via_send(m, state, s->sr); + if (ret > 0) { + s->b &=3D ~VIA1B_vADBInt; + } else { + s->b |=3D VIA1B_vADBInt; + } + } else { + /* input mode */ + ret =3D adb_via_receive(m, state, &s->sr); + if (ret > 0 && s->sr !=3D 0xff) { + s->b &=3D ~VIA1B_vADBInt; + } else { + s->b |=3D VIA1B_vADBInt; + } + } +} + +static void via_adb_poll(void *opaque) +{ + MacVIAState *m =3D opaque; + MOS6522Q800VIA1State *v1s =3D MOS6522_Q800_VIA1(&m->mos6522_via1); + MOS6522State *s =3D MOS6522(v1s); + int state; + + if (s->b & VIA1B_vADBInt) { + state =3D (s->b & VIA1B_vADB_StateMask) >> VIA1B_vADB_StateShift; + if (adb_via_poll(m, state, &s->sr)) { + s->b &=3D ~VIA1B_vADBInt; + } + } + + timer_mod(m->adb_poll_timer, + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + + (NANOSECONDS_PER_SECOND / VIA_ADB_POLL_FREQ)); +} + static uint64_t mos6522_q800_via1_read(void *opaque, hwaddr addr, unsigned= size) { MOS6522Q800VIA1State *s =3D MOS6522_Q800_VIA1(opaque); @@ -510,6 +691,10 @@ static void mac_via_reset(DeviceState *dev) { MacVIAState *m =3D MAC_VIA(dev); =20 + timer_mod(m->adb_poll_timer, + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + + (NANOSECONDS_PER_SECOND / VIA_ADB_POLL_FREQ)); + timer_mod(m->VBL_timer, (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 16630) / 16630 * 16630); =20 @@ -548,6 +733,10 @@ static void mac_via_realize(DeviceState *dev, Error **= errp) =20 qemu_get_timedate(&tm, 0); m->tick_offset =3D (uint32_t)mktimegm(&tm) + RTC_OFFSET; + + m->adb_poll_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, via_adb_poll, m= ); + m->adb_data_ready =3D qdev_get_gpio_in_named(dev, "via1-irq", + VIA1_IRQ_ADB_READY_BIT); } =20 static void mac_via_init(Object *obj) @@ -596,6 +785,7 @@ static void mos6522_q800_via1_portB_write(MOS6522State = *s) MacVIAState *m =3D container_of(v1s, MacVIAState, mos6522_via1); =20 via1_rtc_update(m); + via1_adb_update(m); =20 v1s->last_b =3D s->b; } diff --git a/include/hw/misc/mac_via.h b/include/hw/misc/mac_via.h index 69bdecabb0..2181140293 100644 --- a/include/hw/misc/mac_via.h +++ b/include/hw/misc/mac_via.h @@ -97,6 +97,13 @@ typedef struct MacVIAState { =20 /* ADB */ ADBBusState adb_bus; + QEMUTimer *adb_poll_timer; + qemu_irq adb_data_ready; + int adb_data_in_size; + int adb_data_in_index; + int adb_data_out_index; + uint8_t adb_data_in[128]; + uint8_t adb_data_out[16]; =20 /* external timers */ QEMUTimer *one_second_timer; --=20 2.21.0 From nobody Sun May 5 04:16:47 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1568045173; cv=none; d=zoho.com; s=zohoarc; b=BJujK0f5yvM16EQr454GaTnnzunhcGCD/LosH3zTAp8T1xZHYT8beuyIZQPro+Nz/hbcKuUC7+MV8fF3MloykxdLk3FI3mDQcLyRSmul7dMm6vM1xxMT8OGTOpT9zaV7av4p9JOR24qEhwREmaCKhaPDD4InrlbEn/uUV3zsTwQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1568045173; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=rfEm84HJ13EJoOQUAJ+4Y+bGiDrBPbYEVgUW2SI5Fgs=; b=N+h0nVy5jvZ8Et5y0DaC7hBeS3j7/9aAF8beP5a3rvu5eLO5Kvh0MbtxR/tJxmLCyw2jHAwl7FohKipIeO/J1oKOjcEJA64hxYsfllV7kbWWArAhsJbmHU568oaluSizjYjvfycYT9LZoUkFsKJGoe+rnZ2dyt3+ayZVeGfEzSY= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1568045173550340.3277031171267; Mon, 9 Sep 2019 09:06:13 -0700 (PDT) Received: from localhost ([::1]:58452 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i7MBA-00067b-1S for importer@patchew.org; Mon, 09 Sep 2019 12:06:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59736) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i7M4S-000089-PB for qemu-devel@nongnu.org; Mon, 09 Sep 2019 11:59:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i7M4Q-0001nn-Hw for qemu-devel@nongnu.org; Mon, 09 Sep 2019 11:59:16 -0400 Received: from mout.kundenserver.de ([212.227.126.133]:38033) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i7M4K-0001is-5y; Mon, 09 Sep 2019 11:59:09 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue010 [212.227.15.167]) with ESMTPSA (Nemesis) id 1M3D7V-1i8jda0445-003g3M; Mon, 09 Sep 2019 17:58:31 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Mon, 9 Sep 2019 17:58:09 +0200 Message-Id: <20190909155813.27760-6-laurent@vivier.eu> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190909155813.27760-1-laurent@vivier.eu> References: <20190909155813.27760-1-laurent@vivier.eu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K1:rWgOIt4deRoc3cQj39IVkTb+K099KDKEGsGQsFLoA+5gjMMxxyy DhfzTzvTxx549waU5qC0fYI6+Y1aP1VCHhZllcvNfUiPJ6NKNu+Yn+CSw59BWoilrwCtFor fbUS87Vrv6rTHq8dfcyvYz2mLyaXRcCMHk40twZ6zzUHmPCKz3uAkdu5bYMCC79WjNe60ec nLg+z5JLwVnF9+vVuzNmQ== X-UI-Out-Filterresults: notjunk:1;V03:K0:UFR4GwkZcmU=:WvwdMpzgx9oGv+pBUUasOA ZAHujuH7OoU1jULlM90fzseDHRABf1HRlnvY1ls5zg3dkEWupldJy56j2uDfpc+5ZI9vor01B 3K7LccuZ/8TASSlo7fg8XVV2pWnQJPanAdhczUa/7yP0i5wUi0OAq4wbJcFS2AQdwJ9/yYxfG DhIi+3tjh/gR7K5Okz5Lbz7rzxO0Pn9WvHsF0/LMH+ig9X2lxYUJdG6grAT+ag0GfN3nlwqpW 2vrNPOFE1hTePXlL8Tc92VD34PXrcXpEh9S9hKURF+E2OoRN98CitYzw0QI6QkDp82YxsMZi0 dQOHQrfOEd42tw1I+ZNiul2gRP2JHGGw/qd8xFDca4GKsuZ28TdQeQtftwQZpPr2GY0DfKawZ MdrRyAZkXVkkUObQtJywS0C2nUUytErkCs+csgPyURsNEziPcWT8w7Yi1GrBPhQ6j2e2uyUVX kbsXfMChgUd4ME3pDv/Rk54RRUoZo2bxAjV0ROTtf98EtLfn0kBXUVqQ8PgpsqA8Tg4U9iDC6 j5LdWJpKdrp1UinsoNTGZYugFcSSyXePU6ZQmX/3Jw0Dk5mKFCaJyGkvbDuEsg+fD6YSMwdWz oaf0papyZDH27kvAhpQDDMY1v2IXDmNsuPMorTA0jFADlOItJ9//NtLo5kiu5e7qg8pxLJdff xvYwvRlQ5YtBgrkaRw7HZ3xJ/QrdFHshbXKFpMMdw1lTg96JrYRPlFA7CWIz1cs8A9nRlxX7f XKf/3OwANje1Ir4oPujQDOkc61dlWfnTcQ/vlI1qqqGt0Zg8M+iibO1nnRet5e9RwNnCA1FWX wm2KlIWSepa3LFF1hjkBt5aeliJZdqPhkmFxM4P5L92wW0UfoI= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 212.227.126.133 Subject: [Qemu-devel] [PATCH v9 5/9] hw/m68k: add macfb video card X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Kevin Wolf , qemu-block@nongnu.org, Thomas Huth , Jason Wang , Mark Cave-Ayland , "Dr . David Alan Gilbert" , Max Reitz , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Gerd Hoffmann , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Paolo Bonzini , Aurelien Jarno , Laurent Vivier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Co-developed-by: Mark Cave-Ayland Signed-off-by: Mark Cave-Ayland Signed-off-by: Laurent Vivier Reviewed-by: Herv=C3=A9 Poussineau Reviewed-by: Thomas Huth --- arch_init.c | 4 + hw/display/Kconfig | 3 + hw/display/Makefile.objs | 1 + hw/display/macfb.c | 421 +++++++++++++++++++++++++++++++++++++ include/hw/display/macfb.h | 43 ++++ qemu-options.hx | 2 +- vl.c | 3 +- 7 files changed, 475 insertions(+), 2 deletions(-) create mode 100644 hw/display/macfb.c create mode 100644 include/hw/display/macfb.h diff --git a/arch_init.c b/arch_init.c index 0a1531124c..705d0b94ad 100644 --- a/arch_init.c +++ b/arch_init.c @@ -38,6 +38,10 @@ int graphic_width =3D 1024; int graphic_height =3D 768; int graphic_depth =3D 8; +#elif defined(TARGET_M68K) +int graphic_width =3D 800; +int graphic_height =3D 600; +int graphic_depth =3D 8; #else int graphic_width =3D 800; int graphic_height =3D 600; diff --git a/hw/display/Kconfig b/hw/display/Kconfig index cbdf7b1a67..867b47673c 100644 --- a/hw/display/Kconfig +++ b/hw/display/Kconfig @@ -132,3 +132,6 @@ config ATI_VGA select VGA select BITBANG_I2C select DDC + +config MACFB + bool diff --git a/hw/display/Makefile.objs b/hw/display/Makefile.objs index 5a4066383b..f2182e3bef 100644 --- a/hw/display/Makefile.objs +++ b/hw/display/Makefile.objs @@ -26,6 +26,7 @@ common-obj-$(CONFIG_EXYNOS4) +=3D exynos4210_fimd.o common-obj-$(CONFIG_FRAMEBUFFER) +=3D framebuffer.o obj-$(CONFIG_MILKYMIST) +=3D milkymist-vgafb.o common-obj-$(CONFIG_ZAURUS) +=3D tc6393xb.o +common-obj-$(CONFIG_MACFB) +=3D macfb.o =20 obj-$(CONFIG_MILKYMIST_TMU2) +=3D milkymist-tmu2.o milkymist-tmu2.o-cflags :=3D $(X11_CFLAGS) $(OPENGL_CFLAGS) diff --git a/hw/display/macfb.c b/hw/display/macfb.c new file mode 100644 index 0000000000..d7c5ef296e --- /dev/null +++ b/hw/display/macfb.c @@ -0,0 +1,421 @@ +/* + * QEMU Motorola 680x0 Macintosh Video Card Emulation + * Copyright (c) 2012-2018 Laurent Vivier + * + * some parts from QEMU G364 framebuffer Emulator. + * Copyright (c) 2007-2011 Herve Poussineau + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + * + */ + +#include "qemu/osdep.h" +#include "qemu/units.h" +#include "hw/sysbus.h" +#include "ui/console.h" +#include "ui/pixel_ops.h" +#include "hw/display/macfb.h" +#include "qapi/error.h" +#include "hw/qdev-properties.h" +#include "migration/vmstate.h" + +#define VIDEO_BASE 0x00001000 +#define DAFB_BASE 0x00800000 + +#define MACFB_PAGE_SIZE 4096 +#define MACFB_VRAM_SIZE (4 * MiB) + +#define DAFB_RESET 0x200 +#define DAFB_LUT 0x213 + + +typedef void macfb_draw_line_func(MacfbState *s, uint8_t *d, uint32_t addr, + int width); + +static inline uint8_t macfb_read_byte(MacfbState *s, uint32_t addr) +{ + return s->vram[addr & s->vram_bit_mask]; +} + +/* 1-bit color */ +static void macfb_draw_line1(MacfbState *s, uint8_t *d, uint32_t addr, + int width) +{ + uint8_t r, g, b; + int x; + + for (x =3D 0; x < width; x++) { + int bit =3D x & 7; + int idx =3D (macfb_read_byte(s, addr) >> (7 - bit)) & 1; + r =3D g =3D b =3D ((1 - idx) << 7); + addr +=3D (bit =3D=3D 7); + + *(uint32_t *)d =3D rgb_to_pixel32(r, g, b); + d +=3D 4; + } +} + +/* 2-bit color */ +static void macfb_draw_line2(MacfbState *s, uint8_t *d, uint32_t addr, + int width) +{ + uint8_t r, g, b; + int x; + + for (x =3D 0; x < width; x++) { + int bit =3D (x & 3); + int idx =3D (macfb_read_byte(s, addr) >> ((3 - bit) << 1)) & 3; + r =3D s->color_palette[idx * 3]; + g =3D s->color_palette[idx * 3 + 1]; + b =3D s->color_palette[idx * 3 + 2]; + addr +=3D (bit =3D=3D 3); + + *(uint32_t *)d =3D rgb_to_pixel32(r, g, b); + d +=3D 4; + } +} + +/* 4-bit color */ +static void macfb_draw_line4(MacfbState *s, uint8_t *d, uint32_t addr, + int width) +{ + uint8_t r, g, b; + int x; + + for (x =3D 0; x < width; x++) { + int bit =3D x & 1; + int idx =3D (macfb_read_byte(s, addr) >> ((1 - bit) << 2)) & 15; + r =3D s->color_palette[idx * 3]; + g =3D s->color_palette[idx * 3 + 1]; + b =3D s->color_palette[idx * 3 + 2]; + addr +=3D (bit =3D=3D 1); + + *(uint32_t *)d =3D rgb_to_pixel32(r, g, b); + d +=3D 4; + } +} + +/* 8-bit color */ +static void macfb_draw_line8(MacfbState *s, uint8_t *d, uint32_t addr, + int width) +{ + uint8_t r, g, b; + int x; + + for (x =3D 0; x < width; x++) { + r =3D s->color_palette[macfb_read_byte(s, addr) * 3]; + g =3D s->color_palette[macfb_read_byte(s, addr) * 3 + 1]; + b =3D s->color_palette[macfb_read_byte(s, addr) * 3 + 2]; + addr++; + + *(uint32_t *)d =3D rgb_to_pixel32(r, g, b); + d +=3D 4; + } +} + +/* 16-bit color */ +static void macfb_draw_line16(MacfbState *s, uint8_t *d, uint32_t addr, + int width) +{ + uint8_t r, g, b; + int x; + + for (x =3D 0; x < width; x++) { + uint16_t pixel; + pixel =3D (macfb_read_byte(s, addr) << 8) | macfb_read_byte(s, add= r + 1); + r =3D ((pixel >> 10) & 0x1f) << 3; + g =3D ((pixel >> 5) & 0x1f) << 3; + b =3D (pixel & 0x1f) << 3; + addr +=3D 2; + + *(uint32_t *)d =3D rgb_to_pixel32(r, g, b); + d +=3D 4; + } +} + +/* 24-bit color */ +static void macfb_draw_line24(MacfbState *s, uint8_t *d, uint32_t addr, + int width) +{ + uint8_t r, g, b; + int x; + + for (x =3D 0; x < width; x++) { + r =3D macfb_read_byte(s, addr); + g =3D macfb_read_byte(s, addr + 1); + b =3D macfb_read_byte(s, addr + 2); + addr +=3D 3; + + *(uint32_t *)d =3D rgb_to_pixel32(r, g, b); + d +=3D 4; + } +} + + +enum { + MACFB_DRAW_LINE1, + MACFB_DRAW_LINE2, + MACFB_DRAW_LINE4, + MACFB_DRAW_LINE8, + MACFB_DRAW_LINE16, + MACFB_DRAW_LINE24, + MACFB_DRAW_LINE_NB, +}; + +static macfb_draw_line_func * const + macfb_draw_line_table[MACFB_DRAW_LINE_NB] = =3D { + macfb_draw_line1, + macfb_draw_line2, + macfb_draw_line4, + macfb_draw_line8, + macfb_draw_line16, + macfb_draw_line24, +}; + +static int macfb_check_dirty(MacfbState *s, DirtyBitmapSnapshot *snap, + ram_addr_t addr, int len) +{ + return memory_region_snapshot_get_dirty(&s->mem_vram, snap, addr, len); +} + +static void macfb_draw_graphic(MacfbState *s) +{ + DisplaySurface *surface =3D qemu_console_surface(s->con); + DirtyBitmapSnapshot *snap =3D NULL; + ram_addr_t page; + uint32_t v =3D 0; + int y, ymin; + int macfb_stride =3D (s->depth * s->width + 7) / 8; + macfb_draw_line_func *macfb_draw_line; + + switch (s->depth) { + case 1: + v =3D MACFB_DRAW_LINE1; + break; + case 2: + v =3D MACFB_DRAW_LINE2; + break; + case 4: + v =3D MACFB_DRAW_LINE4; + break; + case 8: + v =3D MACFB_DRAW_LINE8; + break; + case 16: + v =3D MACFB_DRAW_LINE16; + break; + case 24: + v =3D MACFB_DRAW_LINE24; + break; + } + + macfb_draw_line =3D macfb_draw_line_table[v]; + assert(macfb_draw_line !=3D NULL); + + snap =3D memory_region_snapshot_and_clear_dirty(&s->mem_vram, 0x0, + memory_region_size(&s->mem_vr= am), + DIRTY_MEMORY_VGA); + + ymin =3D -1; + page =3D 0; + for (y =3D 0; y < s->height; y++, page +=3D macfb_stride) { + if (macfb_check_dirty(s, snap, page, macfb_stride)) { + uint8_t *data_display; + + data_display =3D surface_data(surface) + y * surface_stride(su= rface); + macfb_draw_line(s, data_display, page, s->width); + + if (ymin < 0) { + ymin =3D y; + } + } else { + if (ymin >=3D 0) { + dpy_gfx_update(s->con, 0, ymin, s->width, y - ymin); + ymin =3D -1; + } + } + } + + if (ymin >=3D 0) { + dpy_gfx_update(s->con, 0, ymin, s->width, y - ymin); + } + + g_free(snap); +} + +static void macfb_invalidate_display(void *opaque) +{ + MacfbState *s =3D opaque; + + memory_region_set_dirty(&s->mem_vram, 0, MACFB_VRAM_SIZE); +} + +static void macfb_update_display(void *opaque) +{ + MacfbState *s =3D opaque; + DisplaySurface *surface =3D qemu_console_surface(s->con); + + qemu_flush_coalesced_mmio_buffer(); + + if (s->width =3D=3D 0 || s->height =3D=3D 0) { + return; + } + + if (s->width !=3D surface_width(surface) || + s->height !=3D surface_height(surface)) { + qemu_console_resize(s->con, s->width, s->height); + } + + macfb_draw_graphic(s); +} + +static void macfb_reset(MacfbState *s) +{ + int i; + + s->palette_current =3D 0; + for (i =3D 0; i < 256; i++) { + s->color_palette[i * 3] =3D 255 - i; + s->color_palette[i * 3 + 1] =3D 255 - i; + s->color_palette[i * 3 + 2] =3D 255 - i; + } + memset(s->vram, 0, MACFB_VRAM_SIZE); + macfb_invalidate_display(s); +} + +static uint64_t macfb_ctrl_read(void *opaque, + hwaddr addr, + unsigned int size) +{ + return 0; +} + +static void macfb_ctrl_write(void *opaque, + hwaddr addr, + uint64_t val, + unsigned int size) +{ + MacfbState *s =3D opaque; + switch (addr) { + case DAFB_RESET: + s->palette_current =3D 0; + break; + case DAFB_LUT: + s->color_palette[s->palette_current++] =3D val; + if (s->palette_current % 3) { + macfb_invalidate_display(s); + } + break; + } +} + +static const MemoryRegionOps macfb_ctrl_ops =3D { + .read =3D macfb_ctrl_read, + .write =3D macfb_ctrl_write, + .endianness =3D DEVICE_BIG_ENDIAN, + .impl.min_access_size =3D 1, + .impl.max_access_size =3D 4, +}; + +static int macfb_post_load(void *opaque, int version_id) +{ + macfb_invalidate_display(opaque); + return 0; +} + +static const VMStateDescription vmstate_macfb =3D { + .name =3D "macfb", + .version_id =3D 1, + .minimum_version_id =3D 1, + .minimum_version_id_old =3D 1, + .post_load =3D macfb_post_load, + .fields =3D (VMStateField[]) { + VMSTATE_UINT8_ARRAY(color_palette, MacfbState, 256 * 3), + VMSTATE_UINT32(palette_current, MacfbState), + VMSTATE_END_OF_LIST() + } +}; + +static const GraphicHwOps macfb_ops =3D { + .invalidate =3D macfb_invalidate_display, + .gfx_update =3D macfb_update_display, +}; + +static void macfb_common_realize(DeviceState *dev, MacfbState *s, Error **= errp) +{ + DisplaySurface *surface; + + if (s->depth !=3D 1 && s->depth !=3D 2 && s->depth !=3D 4 && s->depth = !=3D 8 && + s->depth !=3D 16 && s->depth !=3D 24) { + error_setg(errp, "unknown guest depth %d", s->depth); + return; + } + + s->con =3D graphic_console_init(dev, 0, &macfb_ops, s); + surface =3D qemu_console_surface(s->con); + + if (surface_bits_per_pixel(surface) !=3D 32) { + error_setg(errp, "unknown host depth %d", + surface_bits_per_pixel(surface)); + return; + } + + memory_region_init_io(&s->mem_ctrl, NULL, &macfb_ctrl_ops, s, "macfb-c= trl", + 0x1000); + + memory_region_init_ram_nomigrate(&s->mem_vram, OBJECT(s), "macfb-vram", + MACFB_VRAM_SIZE, errp); + s->vram =3D memory_region_get_ram_ptr(&s->mem_vram); + s->vram_bit_mask =3D MACFB_VRAM_SIZE - 1; + vmstate_register_ram(&s->mem_vram, dev); + memory_region_set_coalescing(&s->mem_vram); +} + +static void macfb_sysbus_realize(DeviceState *dev, Error **errp) +{ + MacfbSysBusState *s =3D MACFB(dev); + MacfbState *ms =3D &s->macfb; + + macfb_common_realize(dev, ms, errp); + sysbus_init_mmio(SYS_BUS_DEVICE(s), &ms->mem_ctrl); + sysbus_init_mmio(SYS_BUS_DEVICE(s), &ms->mem_vram); +} + +static void macfb_sysbus_reset(DeviceState *d) +{ + MacfbSysBusState *s =3D MACFB(d); + macfb_reset(&s->macfb); +} + +static Property macfb_sysbus_properties[] =3D { + DEFINE_PROP_UINT32("width", MacfbSysBusState, macfb.width, 640), + DEFINE_PROP_UINT32("height", MacfbSysBusState, macfb.height, 480), + DEFINE_PROP_UINT8("depth", MacfbSysBusState, macfb.depth, 8), + DEFINE_PROP_END_OF_LIST(), +}; + +static void macfb_sysbus_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D macfb_sysbus_realize; + dc->desc =3D "SysBus Macintosh framebuffer"; + dc->reset =3D macfb_sysbus_reset; + dc->vmsd =3D &vmstate_macfb; + dc->props =3D macfb_sysbus_properties; +} + +static TypeInfo macfb_sysbus_info =3D { + .name =3D TYPE_MACFB, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(MacfbSysBusState), + .class_init =3D macfb_sysbus_class_init, +}; + +static void macfb_register_types(void) +{ + type_register_static(&macfb_sysbus_info); +} + +type_init(macfb_register_types) diff --git a/include/hw/display/macfb.h b/include/hw/display/macfb.h new file mode 100644 index 0000000000..3fe2592735 --- /dev/null +++ b/include/hw/display/macfb.h @@ -0,0 +1,43 @@ +/* + * QEMU Motorola 680x0 Macintosh Video Card Emulation + * Copyright (c) 2012-2018 Laurent Vivier + * + * some parts from QEMU G364 framebuffer Emulator. + * Copyright (c) 2007-2011 Herve Poussineau + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + * + */ + +#ifndef MACFB_H +#define MACFB_H + +#include "qemu/osdep.h" +#include "exec/memory.h" +#include "ui/console.h" + +typedef struct MacfbState { + MemoryRegion mem_vram; + MemoryRegion mem_ctrl; + QemuConsole *con; + + uint8_t *vram; + uint32_t vram_bit_mask; + uint32_t palette_current; + uint8_t color_palette[256 * 3]; + uint32_t width, height; /* in pixels */ + uint8_t depth; +} MacfbState; + +#define TYPE_MACFB "sysbus-macfb" +#define MACFB(obj) \ + OBJECT_CHECK(MacfbSysBusState, (obj), TYPE_MACFB) + +typedef struct { + SysBusDevice busdev; + + MacfbState macfb; +} MacfbSysBusState; + +#endif diff --git a/qemu-options.hx b/qemu-options.hx index bbfd936d29..e14b0b2beb 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -1798,7 +1798,7 @@ ETEXI =20 DEF("g", 1, QEMU_OPTION_g , "-g WxH[xDEPTH] Set the initial graphical resolution and depth\n", - QEMU_ARCH_PPC | QEMU_ARCH_SPARC) + QEMU_ARCH_PPC | QEMU_ARCH_SPARC | QEMU_ARCH_M68K) STEXI @item -g @var{width}x@var{height}[x@var{depth}] @findex -g diff --git a/vl.c b/vl.c index 630f5c5e9c..aa02e5b735 100644 --- a/vl.c +++ b/vl.c @@ -3270,7 +3270,8 @@ int main(int argc, char **argv, char **envp) if (*p =3D=3D 'x') { p++; depth =3D strtol(p, (char **)&p, 10); - if (depth !=3D 8 && depth !=3D 15 && depth !=3D 16= && + if (depth !=3D 1 && depth !=3D 2 && depth !=3D 4 && + depth !=3D 8 && depth !=3D 15 && depth !=3D 16= && depth !=3D 24 && depth !=3D 32) goto graphic_error; } else if (*p =3D=3D '\0') { --=20 2.21.0 From nobody Sun May 5 04:16:47 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1568045205; cv=none; d=zoho.com; s=zohoarc; b=MIgaBv/cqEQn2VkUdMMeGA2j0d4+7eZBc27Hmi0O0yFgtEBz6VXcNEg/lGvKbm9w4uyGjyUMIGTg5DqmVY9ntl/dw9JiZucux4U7cFyd2cDJRBWMNiFk4u+juSUyTkXV0g+jHRRaFhNiHkDiriIUryg/wUri5PeQukhMCBE/U7Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1568045205; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=toTFYWdn3XPzrwNjDroXJtnQxalgAxuSEI3i7xkYies=; b=lzWil6OGbhB4UeMRe32XUQvPhfZL+636p7ff56dLWZC5aXTj1jMcvQJZ7hJ6CrkbonCLMF4R8VIZDHMvvnFbmtpVPQlSzlxLFkEsOgyGkB50kygLfNs3aTohFLmGQlK2VogUqRWDiu5fTwXxrYM3nMbXqHtGf4AJVYQ6H4fJggI= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1568045205200540.4813197339656; Mon, 9 Sep 2019 09:06:45 -0700 (PDT) Received: from localhost ([::1]:58455 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i7MBf-0006wT-No for importer@patchew.org; Mon, 09 Sep 2019 12:06:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59774) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i7M4V-0000CZ-Gl for qemu-devel@nongnu.org; Mon, 09 Sep 2019 11:59:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i7M4S-0001p3-Pd for qemu-devel@nongnu.org; Mon, 09 Sep 2019 11:59:19 -0400 Received: from mout.kundenserver.de ([212.227.126.131]:44591) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i7M4L-0001jV-NL; Mon, 09 Sep 2019 11:59:11 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue010 [212.227.15.167]) with ESMTPSA (Nemesis) id 1N1x6X-1iIflg2x8T-012DDg; Mon, 09 Sep 2019 17:58:34 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Mon, 9 Sep 2019 17:58:10 +0200 Message-Id: <20190909155813.27760-7-laurent@vivier.eu> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190909155813.27760-1-laurent@vivier.eu> References: <20190909155813.27760-1-laurent@vivier.eu> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K1:LnKXBpACJ4aHmHNR7Osdtse9a8cUxCsNm91w5aZgfWjE5y5CNMj m+H2A+potinRnv/xiy2P4zcJiBEBVN7pB6NjoxWf1cBwMytTrMywMUwbVFnXPpsWgCv8NA9 ys3HYReyALiriTYTA+SKe4kLS/86RCSyuAD0H7qVP/DiKu8dei2YqGu9QLHIguD6acwt7UX JXowrRW0kztaa0PxyBYvg== X-UI-Out-Filterresults: notjunk:1;V03:K0:0TSoFonooRc=:skP2DaXz9XEnAxy/4CSCxm JZ/fe/lwIJyVpZ/sadMXYHc/TUcul5n2XP7AqQvjpK3Ve2u81kg21u8Gq7OUEVsKZdYujXunM CnWH/cJMDEu3KF10DeowonsaZHQChIiwfnbiPYc5H+uotXcp7U0+277JscIt6EDX6wOeT6z0A da2SkzI/MrLzQ0JMKrceY6tepxUsr6GTIUn+gnZSIWcP7RkBcKZ9ZxN6ek/23CiWljPUp7GGB utIPGkb+6PM9b1v/YODqmxc7s7VOLf9tvdv9gfl2Ff6KRuSDEdblTRlSf4+sXccwC6E7eet3F +VKu51jhAYRAni9EJzPH9rtEWWpEGUxYtq/byMGlQk7uBumh0BTKOyeZiXETX9Axe1MU+j1zk mdaUX6M8vlNt8dG4oJJzl77yWnOh/42RGVgMx5z0nOdG+sNDL1r0jWcI/qGCwxZi6qYa39RRL UqWNSBzQagPkFLCkhbHghxXT9R7P6pZHuULrdKJWCn0rdTwBuZZNKxD2PEiZMXYZ7R1CFhOjy 0J10oRMfUS4NXmb+xjqf3+apFBrNZ/CMjMSwW+wuwxmUTn/IwCN3729vG4k1jFOPdvGw9fUaI CCgu0uIRuI7J144ty98ThrouwYTRfMwAHm9OZrfKSPhiUbvT5LqJGfmMUIcADEdhRcI9pHRqg 3agsTGsx57XY9ResNMP66x5wP4ejWlR9wIV9YzJno/UBB+Pghnr6LkgHEDxBUALHZZosBaM61 Vb8jR5rsCnh4G5/MifwqdHEN25DBoVCGUalZqSe9lV/X6C1DaNwxJfQa4Bkyq5oQIBWiDLrUi 2jbi6kNr7L5EEyFQ6Uqym1P6d+4CC2WfWZcqlWWfKSqX5T+CKA= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 212.227.126.131 Subject: [Qemu-devel] [PATCH v9 6/9] hw/m68k: add Nubus support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Kevin Wolf , qemu-block@nongnu.org, Thomas Huth , Jason Wang , Mark Cave-Ayland , "Dr . David Alan Gilbert" , Max Reitz , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Gerd Hoffmann , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Paolo Bonzini , Aurelien Jarno , Laurent Vivier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Co-developed-by: Mark Cave-Ayland Signed-off-by: Mark Cave-Ayland Signed-off-by: Laurent Vivier Reviewed-by: Thomas Huth --- hw/Kconfig | 1 + hw/Makefile.objs | 1 + hw/nubus/Kconfig | 2 + hw/nubus/Makefile.objs | 4 + hw/nubus/mac-nubus-bridge.c | 45 ++++++ hw/nubus/nubus-bridge.c | 34 +++++ hw/nubus/nubus-bus.c | 111 ++++++++++++++ hw/nubus/nubus-device.c | 215 ++++++++++++++++++++++++++++ include/hw/nubus/mac-nubus-bridge.h | 24 ++++ include/hw/nubus/nubus.h | 69 +++++++++ 10 files changed, 506 insertions(+) create mode 100644 hw/nubus/Kconfig create mode 100644 hw/nubus/Makefile.objs create mode 100644 hw/nubus/mac-nubus-bridge.c create mode 100644 hw/nubus/nubus-bridge.c create mode 100644 hw/nubus/nubus-bus.c create mode 100644 hw/nubus/nubus-device.c create mode 100644 include/hw/nubus/mac-nubus-bridge.h create mode 100644 include/hw/nubus/nubus.h diff --git a/hw/Kconfig b/hw/Kconfig index b45db3c813..0501a55315 100644 --- a/hw/Kconfig +++ b/hw/Kconfig @@ -21,6 +21,7 @@ source isa/Kconfig source mem/Kconfig source misc/Kconfig source net/Kconfig +source nubus/Kconfig source nvram/Kconfig source pci-bridge/Kconfig source pci-host/Kconfig diff --git a/hw/Makefile.objs b/hw/Makefile.objs index ece6cc3755..457b95e28d 100644 --- a/hw/Makefile.objs +++ b/hw/Makefile.objs @@ -37,6 +37,7 @@ devices-dirs-y +=3D virtio/ devices-dirs-y +=3D watchdog/ devices-dirs-y +=3D xen/ devices-dirs-$(CONFIG_MEM_DEVICE) +=3D mem/ +devices-dirs-$(CONFIG_NUBUS) +=3D nubus/ devices-dirs-y +=3D semihosting/ devices-dirs-y +=3D smbios/ endif diff --git a/hw/nubus/Kconfig b/hw/nubus/Kconfig new file mode 100644 index 0000000000..8fb8b22189 --- /dev/null +++ b/hw/nubus/Kconfig @@ -0,0 +1,2 @@ +config NUBUS + bool diff --git a/hw/nubus/Makefile.objs b/hw/nubus/Makefile.objs new file mode 100644 index 0000000000..135ba7878d --- /dev/null +++ b/hw/nubus/Makefile.objs @@ -0,0 +1,4 @@ +common-obj-y +=3D nubus-device.o +common-obj-y +=3D nubus-bus.o +common-obj-y +=3D nubus-bridge.o +common-obj-$(CONFIG_Q800) +=3D mac-nubus-bridge.o diff --git a/hw/nubus/mac-nubus-bridge.c b/hw/nubus/mac-nubus-bridge.c new file mode 100644 index 0000000000..7c329300b8 --- /dev/null +++ b/hw/nubus/mac-nubus-bridge.c @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2013-2018 Laurent Vivier + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + * + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "hw/nubus/mac-nubus-bridge.h" + + +static void mac_nubus_bridge_init(Object *obj) +{ + MacNubusState *s =3D MAC_NUBUS_BRIDGE(obj); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + + s->bus =3D NUBUS_BUS(qbus_create(TYPE_NUBUS_BUS, DEVICE(s), NULL)); + + sysbus_init_mmio(sbd, &s->bus->super_slot_io); + sysbus_init_mmio(sbd, &s->bus->slot_io); +} + +static void mac_nubus_bridge_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->desc =3D "Nubus bridge"; +} + +static const TypeInfo mac_nubus_bridge_info =3D { + .name =3D TYPE_MAC_NUBUS_BRIDGE, + .parent =3D TYPE_NUBUS_BRIDGE, + .instance_init =3D mac_nubus_bridge_init, + .instance_size =3D sizeof(MacNubusState), + .class_init =3D mac_nubus_bridge_class_init, +}; + +static void mac_nubus_bridge_register_types(void) +{ + type_register_static(&mac_nubus_bridge_info); +} + +type_init(mac_nubus_bridge_register_types) diff --git a/hw/nubus/nubus-bridge.c b/hw/nubus/nubus-bridge.c new file mode 100644 index 0000000000..cd8c6a91eb --- /dev/null +++ b/hw/nubus/nubus-bridge.c @@ -0,0 +1,34 @@ +/* + * QEMU Macintosh Nubus + * + * Copyright (c) 2013-2018 Laurent Vivier + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + * + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "hw/nubus/nubus.h" + +static void nubus_bridge_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->fw_name =3D "nubus"; +} + +static const TypeInfo nubus_bridge_info =3D { + .name =3D TYPE_NUBUS_BRIDGE, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(SysBusDevice), + .class_init =3D nubus_bridge_class_init, +}; + +static void nubus_register_types(void) +{ + type_register_static(&nubus_bridge_info); +} + +type_init(nubus_register_types) diff --git a/hw/nubus/nubus-bus.c b/hw/nubus/nubus-bus.c new file mode 100644 index 0000000000..942a6d5342 --- /dev/null +++ b/hw/nubus/nubus-bus.c @@ -0,0 +1,111 @@ +/* + * QEMU Macintosh Nubus + * + * Copyright (c) 2013-2018 Laurent Vivier + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + * + */ + +#include "qemu/osdep.h" +#include "hw/nubus/nubus.h" +#include "hw/sysbus.h" +#include "qapi/error.h" + + +static NubusBus *nubus_find(void) +{ + /* Returns NULL unless there is exactly one nubus device */ + return NUBUS_BUS(object_resolve_path_type("", TYPE_NUBUS_BUS, NULL)); +} + +static void nubus_slot_write(void *opaque, hwaddr addr, uint64_t val, + unsigned int size) +{ + /* read only */ +} + + +static uint64_t nubus_slot_read(void *opaque, hwaddr addr, + unsigned int size) +{ + return 0; +} + +static const MemoryRegionOps nubus_slot_ops =3D { + .read =3D nubus_slot_read, + .write =3D nubus_slot_write, + .endianness =3D DEVICE_BIG_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 1, + }, +}; + +static void nubus_super_slot_write(void *opaque, hwaddr addr, uint64_t val, + unsigned int size) +{ + /* read only */ +} + +static uint64_t nubus_super_slot_read(void *opaque, hwaddr addr, + unsigned int size) +{ + return 0; +} + +static const MemoryRegionOps nubus_super_slot_ops =3D { + .read =3D nubus_super_slot_read, + .write =3D nubus_super_slot_write, + .endianness =3D DEVICE_BIG_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 1, + }, +}; + +static void nubus_realize(BusState *bus, Error **errp) +{ + if (!nubus_find()) { + error_setg(errp, "at most one %s device is permitted", TYPE_NUBUS_= BUS); + return; + } +} + +static void nubus_init(Object *obj) +{ + NubusBus *nubus =3D NUBUS_BUS(obj); + + memory_region_init_io(&nubus->super_slot_io, obj, &nubus_super_slot_op= s, + nubus, "nubus-super-slots", + NUBUS_SUPER_SLOT_NB * NUBUS_SUPER_SLOT_SIZE); + + memory_region_init_io(&nubus->slot_io, obj, &nubus_slot_ops, + nubus, "nubus-slots", + NUBUS_SLOT_NB * NUBUS_SLOT_SIZE); + + nubus->current_slot =3D NUBUS_FIRST_SLOT; +} + +static void nubus_class_init(ObjectClass *oc, void *data) +{ + BusClass *bc =3D BUS_CLASS(oc); + + bc->realize =3D nubus_realize; +} + +static const TypeInfo nubus_bus_info =3D { + .name =3D TYPE_NUBUS_BUS, + .parent =3D TYPE_BUS, + .instance_size =3D sizeof(NubusBus), + .instance_init =3D nubus_init, + .class_init =3D nubus_class_init, +}; + +static void nubus_register_types(void) +{ + type_register_static(&nubus_bus_info); +} + +type_init(nubus_register_types) diff --git a/hw/nubus/nubus-device.c b/hw/nubus/nubus-device.c new file mode 100644 index 0000000000..01ccad9e8e --- /dev/null +++ b/hw/nubus/nubus-device.c @@ -0,0 +1,215 @@ +/* + * QEMU Macintosh Nubus + * + * Copyright (c) 2013-2018 Laurent Vivier + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + * + */ + +#include "qemu/osdep.h" +#include "hw/nubus/nubus.h" +#include "qapi/error.h" + + +/* The Format Block Structure */ + +#define FBLOCK_DIRECTORY_OFFSET 0 +#define FBLOCK_LENGTH 4 +#define FBLOCK_CRC 8 +#define FBLOCK_REVISION_LEVEL 12 +#define FBLOCK_FORMAT 13 +#define FBLOCK_TEST_PATTERN 14 +#define FBLOCK_RESERVED 18 +#define FBLOCK_BYTE_LANES 19 + +#define FBLOCK_SIZE 20 +#define FBLOCK_PATTERN_VAL 0x5a932bc7 + +static uint64_t nubus_fblock_read(void *opaque, hwaddr addr, unsigned int = size) +{ + NubusDevice *dev =3D opaque; + uint64_t val; + +#define BYTE(v, b) (((v) >> (24 - 8 * (b))) & 0xff) + switch (addr) { + case FBLOCK_BYTE_LANES: + val =3D dev->byte_lanes; + val |=3D (val ^ 0xf) << 4; + break; + case FBLOCK_RESERVED: + val =3D 0x00; + break; + case FBLOCK_TEST_PATTERN...FBLOCK_TEST_PATTERN + 3: + val =3D BYTE(FBLOCK_PATTERN_VAL, addr - FBLOCK_TEST_PATTERN); + break; + case FBLOCK_FORMAT: + val =3D dev->rom_format; + break; + case FBLOCK_REVISION_LEVEL: + val =3D dev->rom_rev; + break; + case FBLOCK_CRC...FBLOCK_CRC + 3: + val =3D BYTE(dev->rom_crc, addr - FBLOCK_CRC); + break; + case FBLOCK_LENGTH...FBLOCK_LENGTH + 3: + val =3D BYTE(dev->rom_length, addr - FBLOCK_LENGTH); + break; + case FBLOCK_DIRECTORY_OFFSET...FBLOCK_DIRECTORY_OFFSET + 3: + val =3D BYTE(dev->directory_offset, addr - FBLOCK_DIRECTORY_OFFSET= ); + break; + default: + val =3D 0; + break; + } + return val; +} + +static void nubus_fblock_write(void *opaque, hwaddr addr, uint64_t val, + unsigned int size) +{ + /* read only */ +} + +static const MemoryRegionOps nubus_format_block_ops =3D { + .read =3D nubus_fblock_read, + .write =3D nubus_fblock_write, + .endianness =3D DEVICE_BIG_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 1, + } +}; + +static void nubus_register_format_block(NubusDevice *dev) +{ + char *fblock_name; + + fblock_name =3D g_strdup_printf("nubus-slot-%d-format-block", + dev->slot_nb); + + hwaddr fblock_offset =3D memory_region_size(&dev->slot_mem) - FBLOCK_S= IZE; + memory_region_init_io(&dev->fblock_io, NULL, &nubus_format_block_ops, + dev, fblock_name, FBLOCK_SIZE); + memory_region_add_subregion(&dev->slot_mem, fblock_offset, + &dev->fblock_io); + + g_free(fblock_name); +} + +static void mac_nubus_rom_write(void *opaque, hwaddr addr, uint64_t val, + unsigned int size) +{ + /* read only */ +} + +static uint64_t mac_nubus_rom_read(void *opaque, hwaddr addr, + unsigned int size) +{ + NubusDevice *dev =3D opaque; + + return dev->rom[addr]; +} + +static const MemoryRegionOps mac_nubus_rom_ops =3D { + .read =3D mac_nubus_rom_read, + .write =3D mac_nubus_rom_write, + .endianness =3D DEVICE_BIG_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 1, + }, +}; + + +void nubus_register_rom(NubusDevice *dev, const uint8_t *rom, uint32_t siz= e, + int revision, int format, uint8_t byte_lanes) +{ + hwaddr rom_offset; + char *rom_name; + + /* FIXME : really compute CRC */ + dev->rom_length =3D 0; + dev->rom_crc =3D 0; + + dev->rom_rev =3D revision; + dev->rom_format =3D format; + + dev->byte_lanes =3D byte_lanes; + dev->directory_offset =3D -size; + + /* ROM */ + + dev->rom =3D rom; + rom_name =3D g_strdup_printf("nubus-slot-%d-rom", dev->slot_nb); + memory_region_init_io(&dev->rom_io, NULL, &mac_nubus_rom_ops, + dev, rom_name, size); + memory_region_set_readonly(&dev->rom_io, true); + + rom_offset =3D memory_region_size(&dev->slot_mem) - FBLOCK_SIZE + + dev->directory_offset; + memory_region_add_subregion(&dev->slot_mem, rom_offset, &dev->rom_io); + + g_free(rom_name); +} + +static void nubus_device_realize(DeviceState *dev, Error **errp) +{ + NubusBus *nubus =3D NUBUS_BUS(qdev_get_parent_bus(DEVICE(dev))); + NubusDevice *nd =3D NUBUS_DEVICE(dev); + char *name; + hwaddr slot_offset; + + if (nubus->current_slot < NUBUS_FIRST_SLOT || + nubus->current_slot > NUBUS_LAST_SLOT) { + error_setg(errp, "Cannot register nubus card, not enough slots"); + return; + } + + nd->slot_nb =3D nubus->current_slot++; + name =3D g_strdup_printf("nubus-slot-%d", nd->slot_nb); + + if (nd->slot_nb < NUBUS_FIRST_SLOT) { + /* Super */ + slot_offset =3D (nd->slot_nb - 6) * NUBUS_SUPER_SLOT_SIZE; + + memory_region_init(&nd->slot_mem, OBJECT(dev), name, + NUBUS_SUPER_SLOT_SIZE); + memory_region_add_subregion(&nubus->super_slot_io, slot_offset, + &nd->slot_mem); + } else { + /* Normal */ + slot_offset =3D nd->slot_nb * NUBUS_SLOT_SIZE; + + memory_region_init(&nd->slot_mem, OBJECT(dev), name, NUBUS_SLOT_SI= ZE); + memory_region_add_subregion(&nubus->slot_io, slot_offset, + &nd->slot_mem); + } + + g_free(name); + nubus_register_format_block(nd); +} + +static void nubus_device_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->realize =3D nubus_device_realize; + dc->bus_type =3D TYPE_NUBUS_BUS; +} + +static const TypeInfo nubus_device_type_info =3D { + .name =3D TYPE_NUBUS_DEVICE, + .parent =3D TYPE_DEVICE, + .abstract =3D true, + .instance_size =3D sizeof(NubusDevice), + .class_init =3D nubus_device_class_init, +}; + +static void nubus_register_types(void) +{ + type_register_static(&nubus_device_type_info); +} + +type_init(nubus_register_types) diff --git a/include/hw/nubus/mac-nubus-bridge.h b/include/hw/nubus/mac-nub= us-bridge.h new file mode 100644 index 0000000000..ce9c789d99 --- /dev/null +++ b/include/hw/nubus/mac-nubus-bridge.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2013-2018 Laurent Vivier + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + * + */ + +#ifndef HW_NUBUS_MAC_H +#define HW_NUBUS_MAC_H + +#include "hw/nubus/nubus.h" + +#define TYPE_MAC_NUBUS_BRIDGE "mac-nubus-bridge" +#define MAC_NUBUS_BRIDGE(obj) OBJECT_CHECK(MacNubusState, (obj), \ + TYPE_MAC_NUBUS_BRIDGE) + +typedef struct MacNubusState { + SysBusDevice sysbus_dev; + + NubusBus *bus; +} MacNubusState; + +#endif diff --git a/include/hw/nubus/nubus.h b/include/hw/nubus/nubus.h new file mode 100644 index 0000000000..a8634e54c5 --- /dev/null +++ b/include/hw/nubus/nubus.h @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2013-2018 Laurent Vivier + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + * + */ + +#ifndef HW_NUBUS_NUBUS_H +#define HW_NUBUS_NUBUS_H + +#include "hw/qdev-properties.h" +#include "exec/address-spaces.h" + +#define NUBUS_SUPER_SLOT_SIZE 0x10000000U +#define NUBUS_SUPER_SLOT_NB 0x9 + +#define NUBUS_SLOT_SIZE 0x01000000 +#define NUBUS_SLOT_NB 0xF + +#define NUBUS_FIRST_SLOT 0x9 +#define NUBUS_LAST_SLOT 0xF + +#define TYPE_NUBUS_DEVICE "nubus-device" +#define NUBUS_DEVICE(obj) \ + OBJECT_CHECK(NubusDevice, (obj), TYPE_NUBUS_DEVICE) + +#define TYPE_NUBUS_BUS "nubus-bus" +#define NUBUS_BUS(obj) OBJECT_CHECK(NubusBus, (obj), TYPE_NUBUS_BUS) + +#define TYPE_NUBUS_BRIDGE "nubus-bridge" +#define NUBUS_BRIDGE(obj) OBJECT_CHECK(NubusBridge, (obj), TYPE_NUBUS_BRID= GE) + +typedef struct NubusBus { + BusState qbus; + + MemoryRegion super_slot_io; + MemoryRegion slot_io; + + int current_slot; +} NubusBus; + +typedef struct NubusDevice { + DeviceState qdev; + + int slot_nb; + MemoryRegion slot_mem; + + /* Format Block */ + + MemoryRegion fblock_io; + + uint32_t rom_length; + uint32_t rom_crc; + uint8_t rom_rev; + uint8_t rom_format; + uint8_t byte_lanes; + int32_t directory_offset; + + /* ROM */ + + MemoryRegion rom_io; + const uint8_t *rom; +} NubusDevice; + +void nubus_register_rom(NubusDevice *dev, const uint8_t *rom, uint32_t siz= e, + int revision, int format, uint8_t byte_lanes); + +#endif --=20 2.21.0 From nobody Sun May 5 04:16:47 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1568044940; cv=none; d=zoho.com; s=zohoarc; b=ZlQfg399YFeQ2+Vbe8wCyShs/Wg/3UQ9zEqZw1xgpu4cEuxGl5irmIvUb77K6zRVBWYAlJ1eqgjAHbEg5PfTzAoYyC2taWOqwLPi5ktj5nDArAPhpNTN11gAZriwEs6QVgbYnSFnQFxzSqfJRtJQe1WZG/yrf8a505hCz7D9EFI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1568044940; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=qW5ifSqbKipwpFdWS3OxluIyWRREucVhY95wJ0M7vDU=; b=NxgeqbgslBarFjK/hczoNzmxJHqIzDJU+tw/eS1S8tETItsi05XZqhXY6ydtXtKhcEi8j5heC+S5qDW9f3loQLtomLA+7SplGuZbigeqzb7yE9fh+2NAvu93PnuD0htijs+mK6qysSxo8kBhB5jdFHpqKCkhHelDy9M9wkRMgc0= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1568044940845883.0689542052759; Mon, 9 Sep 2019 09:02:20 -0700 (PDT) Received: from localhost ([::1]:58402 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i7M7G-0001sP-U8 for importer@patchew.org; Mon, 09 Sep 2019 12:02:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59585) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i7M4C-0008Oy-3D for qemu-devel@nongnu.org; Mon, 09 Sep 2019 11:59:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i7M4A-0001dL-4J for qemu-devel@nongnu.org; Mon, 09 Sep 2019 11:58:59 -0400 Received: from mout.kundenserver.de ([212.227.126.135]:53351) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i7M48-0001bF-59; Mon, 09 Sep 2019 11:58:58 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue010 [212.227.15.167]) with ESMTPSA (Nemesis) id 1Mq2za-1iSt262DMw-00nBc7; Mon, 09 Sep 2019 17:58:36 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Mon, 9 Sep 2019 17:58:11 +0200 Message-Id: <20190909155813.27760-8-laurent@vivier.eu> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190909155813.27760-1-laurent@vivier.eu> References: <20190909155813.27760-1-laurent@vivier.eu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K1:dXX0A0pG8ITV2Z8PgvJaD6rrHOLQTZFzX0lXW661YBR/M2UsIrp d/VT6AB1cWQs2rTHaMxZfnDmNhFKBr/a7clAijmW/ka88Ka42qOTnYZHqhHkvn0+FZknNuN xkRhh9360kuRbMGHTee6TVFsr5zP6lkIVHNHUpt59FUDzSiGn81CPTfeftqCj+iUeZJ5ho5 ozDTOJP3Hx72fF6TsE3sg== X-UI-Out-Filterresults: notjunk:1;V03:K0:hbJ2So1mPC4=:46RetFbv06BZKzUkF6G3Rq UfbKbd8PpEq3Ep2q2+iVh0fQrQdAbZZewIeDe/cEtsQ4Jvxl93rnJlNWtmvWQxZxmBWzLacQM rjPcND93Kn2sIt12iw7MpkY0jA56KU7gVaTYyNvJ1nlyJCyQ+9+kSOsEDBIXKBF6afp/am+Rk bQC2uJetvlce/NziAVI4z+DqVkxGC6uKTMu1AJBprb70aJQuBfl7EvXFYtBUXgMI6rvd/LIjY gmXAevZ48AW0oD7m7+cu9BTKAegvITaHk93I9abKNeYqVFZWfIDj5TyalCHfhMDQPIJe0qBIh pQ1lMQWzOJwgmka2OU2BSjRRqbZ8RDLguByjRgmNBMYGK6X7/ZENoUc7XTqB7SnWpl4hV5vIP tqIPgA4W3zmbnp4RTy2dkM711Nb+FfDt3s+e7oZfMPOI/aQ8c3sWvDBNdyL8stuIKEuCIsLAb JCl8lQNdfLrjZUVSf3yCIPWPnkfubYnttfMJMctPeIcVXeveuV4OYljOrkb9k6j13b6lGZ5cR D+dLnDWOMXrkQUzEj6Jr6TBomIZEBN26QTL5giWwd5i6M7Cc/d1XZz1ZzoW9J9OpKWGcE69ZY PeP8uiLqoViNG4E9CF6ZS+JLNdNyyXMRjzqPvj+HXvw4JQCj70NsIBIC/jrpf1KiklFexMvW5 tWRNORBsRDHPuYA0PmMXLKji/yYA6dH1w68DTRWjMQR5HOZHjVSE8X4Eb/xOowQkHuI7GgsBG UTEnRTkjYei7Itn9EgIDr22VT2QXLWyACSd8rK0vurRPA7SspHRwt6Bc0xICYvbSTLWyeqbTc yMlC6/Py1KvIBX9EH5oSYiJHEcQHEhHl2P12SuFKEM+il/RTTE= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 212.227.126.135 Subject: [Qemu-devel] [PATCH v9 7/9] hw/m68k: add Nubus support for macfb video card X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Kevin Wolf , qemu-block@nongnu.org, Thomas Huth , Jason Wang , Mark Cave-Ayland , "Dr . David Alan Gilbert" , Max Reitz , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Gerd Hoffmann , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Paolo Bonzini , Aurelien Jarno , Laurent Vivier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Mark Cave-Ayland Co-developed-by: Mark Cave-Ayland Signed-off-by: Mark Cave-Ayland Signed-off-by: Laurent Vivier Reviewed-by: Herv=C3=A9 Poussineau --- hw/display/Kconfig | 1 + hw/display/macfb.c | 56 ++++++++++++++++++++++++++++++++++++++ include/hw/display/macfb.h | 21 ++++++++++++++ 3 files changed, 78 insertions(+) diff --git a/hw/display/Kconfig b/hw/display/Kconfig index 867b47673c..02163048cd 100644 --- a/hw/display/Kconfig +++ b/hw/display/Kconfig @@ -135,3 +135,4 @@ config ATI_VGA =20 config MACFB bool + depends on NUBUS diff --git a/hw/display/macfb.c b/hw/display/macfb.c index d7c5ef296e..f4fa8e3206 100644 --- a/hw/display/macfb.c +++ b/hw/display/macfb.c @@ -15,6 +15,7 @@ #include "hw/sysbus.h" #include "ui/console.h" #include "ui/pixel_ops.h" +#include "hw/nubus/nubus.h" #include "hw/display/macfb.h" #include "qapi/error.h" #include "hw/qdev-properties.h" @@ -382,12 +383,38 @@ static void macfb_sysbus_realize(DeviceState *dev, Er= ror **errp) sysbus_init_mmio(SYS_BUS_DEVICE(s), &ms->mem_vram); } =20 +const uint8_t macfb_rom[] =3D { + 255, 0, 0, 0, +}; + +static void macfb_nubus_realize(DeviceState *dev, Error **errp) +{ + NubusDevice *nd =3D NUBUS_DEVICE(dev); + MacfbNubusState *s =3D NUBUS_MACFB(dev); + MacfbNubusDeviceClass *ndc =3D MACFB_NUBUS_GET_CLASS(dev); + MacfbState *ms =3D &s->macfb; + + ndc->parent_realize(dev, errp); + + macfb_common_realize(dev, ms, errp); + memory_region_add_subregion(&nd->slot_mem, DAFB_BASE, &ms->mem_ctrl); + memory_region_add_subregion(&nd->slot_mem, VIDEO_BASE, &ms->mem_vram); + + nubus_register_rom(nd, macfb_rom, sizeof(macfb_rom), 1, 9, 0xf); +} + static void macfb_sysbus_reset(DeviceState *d) { MacfbSysBusState *s =3D MACFB(d); macfb_reset(&s->macfb); } =20 +static void macfb_nubus_reset(DeviceState *d) +{ + MacfbNubusState *s =3D NUBUS_MACFB(d); + macfb_reset(&s->macfb); +} + static Property macfb_sysbus_properties[] =3D { DEFINE_PROP_UINT32("width", MacfbSysBusState, macfb.width, 640), DEFINE_PROP_UINT32("height", MacfbSysBusState, macfb.height, 480), @@ -395,6 +422,13 @@ static Property macfb_sysbus_properties[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 +static Property macfb_nubus_properties[] =3D { + DEFINE_PROP_UINT32("width", MacfbNubusState, macfb.width, 640), + DEFINE_PROP_UINT32("height", MacfbNubusState, macfb.height, 480), + DEFINE_PROP_UINT8("depth", MacfbNubusState, macfb.depth, 8), + DEFINE_PROP_END_OF_LIST(), +}; + static void macfb_sysbus_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -406,6 +440,19 @@ static void macfb_sysbus_class_init(ObjectClass *klass= , void *data) dc->props =3D macfb_sysbus_properties; } =20 +static void macfb_nubus_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + MacfbNubusDeviceClass *ndc =3D MACFB_NUBUS_DEVICE_CLASS(klass); + + device_class_set_parent_realize(dc, macfb_nubus_realize, + &ndc->parent_realize); + dc->desc =3D "Nubus Macintosh framebuffer"; + dc->reset =3D macfb_nubus_reset; + dc->vmsd =3D &vmstate_macfb; + dc->props =3D macfb_nubus_properties; +} + static TypeInfo macfb_sysbus_info =3D { .name =3D TYPE_MACFB, .parent =3D TYPE_SYS_BUS_DEVICE, @@ -413,9 +460,18 @@ static TypeInfo macfb_sysbus_info =3D { .class_init =3D macfb_sysbus_class_init, }; =20 +static TypeInfo macfb_nubus_info =3D { + .name =3D TYPE_NUBUS_MACFB, + .parent =3D TYPE_NUBUS_DEVICE, + .instance_size =3D sizeof(MacfbNubusState), + .class_init =3D macfb_nubus_class_init, + .class_size =3D sizeof(MacfbNubusDeviceClass), +}; + static void macfb_register_types(void) { type_register_static(&macfb_sysbus_info); + type_register_static(&macfb_nubus_info); } =20 type_init(macfb_register_types) diff --git a/include/hw/display/macfb.h b/include/hw/display/macfb.h index 3fe2592735..26367ae2c4 100644 --- a/include/hw/display/macfb.h +++ b/include/hw/display/macfb.h @@ -40,4 +40,25 @@ typedef struct { MacfbState macfb; } MacfbSysBusState; =20 +#define MACFB_NUBUS_DEVICE_CLASS(class) \ + OBJECT_CLASS_CHECK(MacfbNubusDeviceClass, (class), TYPE_NUBUS_MACFB) +#define MACFB_NUBUS_GET_CLASS(obj) \ + OBJECT_GET_CLASS(MacfbNubusDeviceClass, (obj), TYPE_NUBUS_MACFB) + +typedef struct MacfbNubusDeviceClass { + DeviceClass parent_class; + + DeviceRealize parent_realize; +} MacfbNubusDeviceClass; + +#define TYPE_NUBUS_MACFB "nubus-macfb" +#define NUBUS_MACFB(obj) \ + OBJECT_CHECK(MacfbNubusState, (obj), TYPE_NUBUS_MACFB) + +typedef struct { + NubusDevice busdev; + + MacfbState macfb; +} MacfbNubusState; + #endif --=20 2.21.0 From nobody Sun May 5 04:16:47 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1568045155; cv=none; d=zoho.com; s=zohoarc; b=THtL+A0QUN/cOWNLbG5QF1Sq+lQXUt3xOPSxeZ07EcKsJnIPsdJYOib/mLVSHzCe5vRZZcm8Jg9e5Sj6ep/hrRw4hsUtKa5DLNyLvnsrSJt72ltDb2daCfEq1bsBS3a42ifrteRFR6lJzVPpPFl+5ixqTTofTzMUtBQju25D06I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1568045155; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=JPYcpBhJPnD+wulPqw07Eh3r/RZUZ2cMZKGtvEM4now=; b=E635ZZ4VsMGA+wAfMPmHE76nldl+IUrRahiM16buGPV6lkcGRUiop9sXJosYsHUZY99GQ39iyDbbu87DqSum3JC9bVGhc1wPxkLcuBYTsnCf+6eMeQjBzlWJh59L4NFYkAGh2F8/8kTKfx/FosJ+GPhj0M7LujjLJizgixoaG70= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1568045155201960.8828805088621; Mon, 9 Sep 2019 09:05:55 -0700 (PDT) Received: from localhost ([::1]:58448 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i7MAr-0005aF-G3 for importer@patchew.org; Mon, 09 Sep 2019 12:05:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59726) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i7M4S-00007V-AQ for qemu-devel@nongnu.org; Mon, 09 Sep 2019 11:59:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i7M4P-0001nS-Vn for qemu-devel@nongnu.org; Mon, 09 Sep 2019 11:59:16 -0400 Received: from mout.kundenserver.de ([212.227.126.133]:35287) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i7M4I-0001he-Je; Mon, 09 Sep 2019 11:59:07 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue010 [212.227.15.167]) with ESMTPSA (Nemesis) id 1M89bP-1i2f6M3lpL-005MLu; Mon, 09 Sep 2019 17:58:38 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Mon, 9 Sep 2019 17:58:12 +0200 Message-Id: <20190909155813.27760-9-laurent@vivier.eu> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190909155813.27760-1-laurent@vivier.eu> References: <20190909155813.27760-1-laurent@vivier.eu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K1:NstPmxFU1nxu+RQl5jYAud0o038aaM2df+BV2B7csGvmF9cFje3 iidCv+FjeCJc83AuuG6OAzxgKasBnMU+h8baYhArj6AYGUEg0Qaa+SWyCvT8ifM8YAaHzXd 8w6vqX3y2A02aEzApMifYhNLLage/XdQBmrYb1KSSMoRqQ+K+1zZJ6dgkE2oDqtY6kZTXcm feUPfiyl+cZN+M7g5NjFA== X-UI-Out-Filterresults: notjunk:1;V03:K0:P8aSxeJ0YWc=:m3RZZjWxjIJ79pksUhBoUQ asi9AiwjHzhPyQPoPW0q9M0v3pTFtWqvvQd5wro/N85UJvvk6rLVmwvjYUVRoHI0b8lhLRUgo ufVmmhl/tQvkn9BHlIYoembdGrU0FGh6ZmPh4bLwnPPCwfM1sSCHWz0aGw7H3/xmZoWLWHAbX gSHCUA5VBQRlsVtAV0d4ktbI8DGUiDZ9Gg21J7rt79HMzgKM6EgFZ9g7r3HoZUrUMtkOl3Ums c3O8j6g7VfEns3sNstyyxrjW+y46Ha1Wda9EH+AOffgCU7x/zrcrJua2KIn/rNO6/F0y+SxaR FSjFOJfEoG2bBjknql4tGMYdJO6+KbTRqS47e/o5IgK+SKaCe9wxepOnDWLBX++3/YFnn0e+S SObmPbGV95iT3f8eArHvX+LsklImZKrnodicZPGyb2726vb3Ns0pnbCAKu/LVVQU2kPHUTX9S 1pTGicMpYKFM9Km9ehpvnZ2w92GUn9gfTUKRiCoacRj00ZJVfa7DgPAylym61UnvvvwkfM/AX v8c+mX1PesUcIy0aBrOIJ4KfYkTegxbMdilbUg4WNAyycE7k27yhmk5E2FPFsnKp6eOb/eMFw 05ndJ323fSju1eGsPhELMNbCGSMLB26c491YR6uOuKglgKn+k/rz96w2pjBZzDuFnxkvDTact 5RRk5YdPKdpBR/iIa5NfC6WkyYUAcH+H+V1Dv5UtPlPIwPVthlRyQws1d58TSqxckAYj6UL0C yF9GGxgnt6o294O8KJ0JvOW0BpMalinvECihNYJJJbQu8DXw1Z1KTfUOYpwSZfc/dcKCflTsx Yijt+bKuo/LtM+WHX8id6tgWIIO4+xLXYWGiJvHiRuTifWvcQM= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 212.227.126.133 Subject: [Qemu-devel] [PATCH v9 8/9] hw/m68k: add a dummy SWIM floppy controller X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Kevin Wolf , qemu-block@nongnu.org, Thomas Huth , Jason Wang , Mark Cave-Ayland , "Dr . David Alan Gilbert" , Max Reitz , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Gerd Hoffmann , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Paolo Bonzini , Aurelien Jarno , Laurent Vivier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Co-developed-by: Mark Cave-Ayland Signed-off-by: Mark Cave-Ayland Signed-off-by: Laurent Vivier Reviewed-by: Herv=C3=A9 Poussineau --- hw/block/Kconfig | 3 + hw/block/Makefile.objs | 1 + hw/block/swim.c | 421 ++++++++++++++++++++++++++++++++++++++++ include/hw/block/swim.h | 76 ++++++++ 4 files changed, 501 insertions(+) create mode 100644 hw/block/swim.c create mode 100644 include/hw/block/swim.h diff --git a/hw/block/Kconfig b/hw/block/Kconfig index df96dc5dcc..2d17f481ad 100644 --- a/hw/block/Kconfig +++ b/hw/block/Kconfig @@ -37,3 +37,6 @@ config VHOST_USER_BLK # Only PCI devices are provided for now default y if VIRTIO_PCI depends on VIRTIO && VHOST_USER && LINUX + +config SWIM + bool diff --git a/hw/block/Makefile.objs b/hw/block/Makefile.objs index f5f643f0cc..28c2495a00 100644 --- a/hw/block/Makefile.objs +++ b/hw/block/Makefile.objs @@ -8,6 +8,7 @@ common-obj-$(CONFIG_XEN) +=3D xen-block.o common-obj-$(CONFIG_ECC) +=3D ecc.o common-obj-$(CONFIG_ONENAND) +=3D onenand.o common-obj-$(CONFIG_NVME_PCI) +=3D nvme.o +common-obj-$(CONFIG_SWIM) +=3D swim.o =20 obj-$(CONFIG_SH4) +=3D tc58128.o =20 diff --git a/hw/block/swim.c b/hw/block/swim.c new file mode 100644 index 0000000000..6e26915238 --- /dev/null +++ b/hw/block/swim.c @@ -0,0 +1,421 @@ +/* + * QEMU Macintosh floppy disk controller emulator (SWIM) + * + * Copyright (c) 2014-2018 Laurent Vivier + * + * This work is licensed under the terms of the GNU GPL, version 2. See + * the COPYING file in the top-level directory. + * + */ + +#include "qemu/osdep.h" +#include "qemu/main-loop.h" +#include "qapi/error.h" +#include "sysemu/block-backend.h" +#include "hw/sysbus.h" +#include "hw/block/block.h" +#include "hw/block/swim.h" +#include "hw/qdev-properties.h" + +/* IWM registers */ + +#define IWM_PH0L 0 +#define IWM_PH0H 1 +#define IWM_PH1L 2 +#define IWM_PH1H 3 +#define IWM_PH2L 4 +#define IWM_PH2H 5 +#define IWM_PH3L 6 +#define IWM_PH3H 7 +#define IWM_MTROFF 8 +#define IWM_MTRON 9 +#define IWM_INTDRIVE 10 +#define IWM_EXTDRIVE 11 +#define IWM_Q6L 12 +#define IWM_Q6H 13 +#define IWM_Q7L 14 +#define IWM_Q7H 15 + +/* SWIM registers */ + +#define SWIM_WRITE_DATA 0 +#define SWIM_WRITE_MARK 1 +#define SWIM_WRITE_CRC 2 +#define SWIM_WRITE_PARAMETER 3 +#define SWIM_WRITE_PHASE 4 +#define SWIM_WRITE_SETUP 5 +#define SWIM_WRITE_MODE0 6 +#define SWIM_WRITE_MODE1 7 + +#define SWIM_READ_DATA 8 +#define SWIM_READ_MARK 9 +#define SWIM_READ_ERROR 10 +#define SWIM_READ_PARAMETER 11 +#define SWIM_READ_PHASE 12 +#define SWIM_READ_SETUP 13 +#define SWIM_READ_STATUS 14 +#define SWIM_READ_HANDSHAKE 15 + +#define REG_SHIFT 9 + +#define SWIM_MODE_IWM 0 +#define SWIM_MODE_SWIM 1 + +/* bits in phase register */ + +#define SWIM_SEEK_NEGATIVE 0x074 +#define SWIM_STEP 0x071 +#define SWIM_MOTOR_ON 0x072 +#define SWIM_MOTOR_OFF 0x076 +#define SWIM_INDEX 0x073 +#define SWIM_EJECT 0x077 +#define SWIM_SETMFM 0x171 +#define SWIM_SETGCR 0x175 +#define SWIM_RELAX 0x033 +#define SWIM_LSTRB 0x008 +#define SWIM_CA_MASK 0x077 + +/* Select values for swim_select and swim_readbit */ + +#define SWIM_READ_DATA_0 0x074 +#define SWIM_TWOMEG_DRIVE 0x075 +#define SWIM_SINGLE_SIDED 0x076 +#define SWIM_DRIVE_PRESENT 0x077 +#define SWIM_DISK_IN 0x170 +#define SWIM_WRITE_PROT 0x171 +#define SWIM_TRACK_ZERO 0x172 +#define SWIM_TACHO 0x173 +#define SWIM_READ_DATA_1 0x174 +#define SWIM_MFM_MODE 0x175 +#define SWIM_SEEK_COMPLETE 0x176 +#define SWIM_ONEMEG_MEDIA 0x177 + +/* Bits in handshake register */ + +#define SWIM_MARK_BYTE 0x01 +#define SWIM_CRC_ZERO 0x02 +#define SWIM_RDDATA 0x04 +#define SWIM_SENSE 0x08 +#define SWIM_MOTEN 0x10 +#define SWIM_ERROR 0x20 +#define SWIM_DAT2BYTE 0x40 +#define SWIM_DAT1BYTE 0x80 + +/* bits in setup register */ + +#define SWIM_S_INV_WDATA 0x01 +#define SWIM_S_3_5_SELECT 0x02 +#define SWIM_S_GCR 0x04 +#define SWIM_S_FCLK_DIV2 0x08 +#define SWIM_S_ERROR_CORR 0x10 +#define SWIM_S_IBM_DRIVE 0x20 +#define SWIM_S_GCR_WRITE 0x40 +#define SWIM_S_TIMEOUT 0x80 + +/* bits in mode register */ + +#define SWIM_CLFIFO 0x01 +#define SWIM_ENBL1 0x02 +#define SWIM_ENBL2 0x04 +#define SWIM_ACTION 0x08 +#define SWIM_WRITE_MODE 0x10 +#define SWIM_HEDSEL 0x20 +#define SWIM_MOTON 0x80 + +static void swim_change_cb(void *opaque, bool load, Error **errp) +{ + FDrive *drive =3D opaque; + + if (!load) { + blk_set_perm(drive->blk, 0, BLK_PERM_ALL, &error_abort); + } else { + if (!blkconf_apply_backend_options(drive->conf, + blk_is_read_only(drive->blk), f= alse, + errp)) { + return; + } + } +} + +static const BlockDevOps swim_block_ops =3D { + .change_media_cb =3D swim_change_cb, +}; + +static Property swim_drive_properties[] =3D { + DEFINE_PROP_INT32("unit", SWIMDrive, unit, -1), + DEFINE_BLOCK_PROPERTIES(SWIMDrive, conf), + DEFINE_PROP_END_OF_LIST(), +}; + +static void swim_drive_realize(DeviceState *qdev, Error **errp) +{ + SWIMDrive *dev =3D SWIM_DRIVE(qdev); + SWIMBus *bus =3D SWIM_BUS(qdev->parent_bus); + FDrive *drive; + int ret; + + if (dev->unit =3D=3D -1) { + for (dev->unit =3D 0; dev->unit < SWIM_MAX_FD; dev->unit++) { + drive =3D &bus->ctrl->drives[dev->unit]; + if (!drive->blk) { + break; + } + } + } + + if (dev->unit >=3D SWIM_MAX_FD) { + error_setg(errp, "Can't create floppy unit %d, bus supports " + "only %d units", dev->unit, SWIM_MAX_FD); + return; + } + + drive =3D &bus->ctrl->drives[dev->unit]; + if (drive->blk) { + error_setg(errp, "Floppy unit %d is in use", dev->unit); + return; + } + + if (!dev->conf.blk) { + /* Anonymous BlockBackend for an empty drive */ + dev->conf.blk =3D blk_new(qemu_get_aio_context(), 0, BLK_PERM_ALL); + ret =3D blk_attach_dev(dev->conf.blk, qdev); + assert(ret =3D=3D 0); + } + + blkconf_blocksizes(&dev->conf); + if (dev->conf.logical_block_size !=3D 512 || + dev->conf.physical_block_size !=3D 512) + { + error_setg(errp, "Physical and logical block size must " + "be 512 for floppy"); + return; + } + + /* + * rerror/werror aren't supported by fdc and therefore not even regist= ered + * with qdev. So set the defaults manually before they are used in + * blkconf_apply_backend_options(). + */ + dev->conf.rerror =3D BLOCKDEV_ON_ERROR_AUTO; + dev->conf.werror =3D BLOCKDEV_ON_ERROR_AUTO; + + if (!blkconf_apply_backend_options(&dev->conf, + blk_is_read_only(dev->conf.blk), + false, errp)) { + return; + } + + /* + * 'enospc' is the default for -drive, 'report' is what blk_new() give= s us + * for empty drives. + */ + if (blk_get_on_error(dev->conf.blk, 0) !=3D BLOCKDEV_ON_ERROR_ENOSPC && + blk_get_on_error(dev->conf.blk, 0) !=3D BLOCKDEV_ON_ERROR_REPORT) { + error_setg(errp, "fdc doesn't support drive option werror"); + return; + } + if (blk_get_on_error(dev->conf.blk, 1) !=3D BLOCKDEV_ON_ERROR_REPORT) { + error_setg(errp, "fdc doesn't support drive option rerror"); + return; + } + + drive->conf =3D &dev->conf; + drive->blk =3D dev->conf.blk; + drive->swimctrl =3D bus->ctrl; + + blk_set_dev_ops(drive->blk, &swim_block_ops, drive); +} + +static void swim_drive_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *k =3D DEVICE_CLASS(klass); + k->realize =3D swim_drive_realize; + set_bit(DEVICE_CATEGORY_STORAGE, k->categories); + k->bus_type =3D TYPE_SWIM_BUS; + k->props =3D swim_drive_properties; + k->desc =3D "virtual SWIM drive"; +} + +static const TypeInfo swim_drive_info =3D { + .name =3D TYPE_SWIM_DRIVE, + .parent =3D TYPE_DEVICE, + .instance_size =3D sizeof(SWIMDrive), + .class_init =3D swim_drive_class_init, +}; + +static const TypeInfo swim_bus_info =3D { + .name =3D TYPE_SWIM_BUS, + .parent =3D TYPE_BUS, + .instance_size =3D sizeof(SWIMBus), +}; + +static void iwmctrl_write(void *opaque, hwaddr reg, uint64_t value, + unsigned size) +{ + SWIMCtrl *swimctrl =3D opaque; + + reg >>=3D REG_SHIFT; + + swimctrl->regs[reg >> 1] =3D reg & 1; + + if (swimctrl->regs[IWM_Q6] && + swimctrl->regs[IWM_Q7]) { + if (swimctrl->regs[IWM_MTR]) { + /* data register */ + swimctrl->iwm_data =3D value; + } else { + /* mode register */ + swimctrl->iwm_mode =3D value; + /* detect sequence to switch from IWM mode to SWIM mode */ + switch (swimctrl->iwm_switch) { + case 0: + if (value =3D=3D 0x57) { + swimctrl->iwm_switch++; + } + break; + case 1: + if (value =3D=3D 0x17) { + swimctrl->iwm_switch++; + } + break; + case 2: + if (value =3D=3D 0x57) { + swimctrl->iwm_switch++; + } + break; + case 3: + if (value =3D=3D 0x57) { + swimctrl->mode =3D SWIM_MODE_SWIM; + swimctrl->iwm_switch =3D 0; + } + break; + } + } + } +} + +static uint64_t iwmctrl_read(void *opaque, hwaddr reg, unsigned size) +{ + SWIMCtrl *swimctrl =3D opaque; + + reg >>=3D REG_SHIFT; + + swimctrl->regs[reg >> 1] =3D reg & 1; + + return 0; +} + +static void swimctrl_write(void *opaque, hwaddr reg, uint64_t value, + unsigned size) +{ + SWIMCtrl *swimctrl =3D opaque; + + if (swimctrl->mode =3D=3D SWIM_MODE_IWM) { + iwmctrl_write(opaque, reg, value, size); + return; + } + + reg >>=3D REG_SHIFT; + + switch (reg) { + case SWIM_WRITE_PHASE: + swimctrl->swim_phase =3D value; + break; + case SWIM_WRITE_MODE0: + swimctrl->swim_mode &=3D ~value; + break; + case SWIM_WRITE_MODE1: + swimctrl->swim_mode |=3D value; + break; + case SWIM_WRITE_DATA: + case SWIM_WRITE_MARK: + case SWIM_WRITE_CRC: + case SWIM_WRITE_PARAMETER: + case SWIM_WRITE_SETUP: + break; + } +} + +static uint64_t swimctrl_read(void *opaque, hwaddr reg, unsigned size) +{ + SWIMCtrl *swimctrl =3D opaque; + uint32_t value =3D 0; + + if (swimctrl->mode =3D=3D SWIM_MODE_IWM) { + return iwmctrl_read(opaque, reg, size); + } + + reg >>=3D REG_SHIFT; + + switch (reg) { + case SWIM_READ_PHASE: + value =3D swimctrl->swim_phase; + break; + case SWIM_READ_HANDSHAKE: + if (swimctrl->swim_phase =3D=3D SWIM_DRIVE_PRESENT) { + /* always answer "no drive present" */ + value =3D SWIM_SENSE; + } + break; + case SWIM_READ_DATA: + case SWIM_READ_MARK: + case SWIM_READ_ERROR: + case SWIM_READ_PARAMETER: + case SWIM_READ_SETUP: + case SWIM_READ_STATUS: + break; + } + + return value; +} + +static const MemoryRegionOps swimctrl_mem_ops =3D { + .write =3D swimctrl_write, + .read =3D swimctrl_read, + .endianness =3D DEVICE_NATIVE_ENDIAN, +}; + +static void sysbus_swim_init(Object *obj) +{ + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + SWIM *sbs =3D SWIM(obj); + SWIMCtrl *swimctrl =3D &sbs->ctrl; + + memory_region_init_io(&swimctrl->iomem, obj, &swimctrl_mem_ops, swimct= rl, + "swim", 0x2000); + sysbus_init_mmio(sbd, &swimctrl->iomem); +} + +static void sysbus_swim_realize(DeviceState *dev, Error **errp) +{ + SWIM *sys =3D SWIM(dev); + SWIMCtrl *swimctrl =3D &sys->ctrl; + + qbus_create_inplace(&swimctrl->bus, sizeof(SWIMBus), TYPE_SWIM_BUS, de= v, + NULL); + swimctrl->bus.ctrl =3D swimctrl; +} + +static void sysbus_swim_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->realize =3D sysbus_swim_realize; +} + +static const TypeInfo sysbus_swim_info =3D { + .name =3D TYPE_SWIM, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(SWIM), + .instance_init =3D sysbus_swim_init, + .class_init =3D sysbus_swim_class_init, +}; + +static void swim_register_types(void) +{ + type_register_static(&sysbus_swim_info); + type_register_static(&swim_bus_info); + type_register_static(&swim_drive_info); +} + +type_init(swim_register_types) diff --git a/include/hw/block/swim.h b/include/hw/block/swim.h new file mode 100644 index 0000000000..e69c644995 --- /dev/null +++ b/include/hw/block/swim.h @@ -0,0 +1,76 @@ +/* + * QEMU Macintosh floppy disk controller emulator (SWIM) + * + * Copyright (c) 2014-2018 Laurent Vivier + * + * This work is licensed under the terms of the GNU GPL, version 2. See + * the COPYING file in the top-level directory. + * + */ + +#ifndef SWIM_H +#define SWIM_H + +#include "qemu/osdep.h" +#include "hw/sysbus.h" + +#define SWIM_MAX_FD 2 + +typedef struct SWIMDrive SWIMDrive; +typedef struct SWIMBus SWIMBus; +typedef struct SWIMCtrl SWIMCtrl; + +#define TYPE_SWIM_DRIVE "swim-drive" +#define SWIM_DRIVE(obj) OBJECT_CHECK(SWIMDrive, (obj), TYPE_SWIM_DRIVE) + +struct SWIMDrive { + DeviceState qdev; + int32_t unit; + BlockConf conf; +}; + +#define TYPE_SWIM_BUS "swim-bus" +#define SWIM_BUS(obj) OBJECT_CHECK(SWIMBus, (obj), TYPE_SWIM_BUS) + +struct SWIMBus { + BusState bus; + struct SWIMCtrl *ctrl; +}; + +typedef struct FDrive { + SWIMCtrl *swimctrl; + BlockBackend *blk; + BlockConf *conf; +} FDrive; + +struct SWIMCtrl { + MemoryRegion iomem; + FDrive drives[SWIM_MAX_FD]; + int mode; + /* IWM mode */ + int iwm_switch; + int regs[8]; +#define IWM_PH0 0 +#define IWM_PH1 1 +#define IWM_PH2 2 +#define IWM_PH3 3 +#define IWM_MTR 4 +#define IWM_DRIVE 5 +#define IWM_Q6 6 +#define IWM_Q7 7 + uint8_t iwm_data; + uint8_t iwm_mode; + /* SWIM mode */ + uint8_t swim_phase; + uint8_t swim_mode; + SWIMBus bus; +}; + +#define TYPE_SWIM "swim" +#define SWIM(obj) OBJECT_CHECK(SWIM, (obj), TYPE_SWIM) + +typedef struct SWIM { + SysBusDevice parent_obj; + SWIMCtrl ctrl; +} SWIM; +#endif --=20 2.21.0 From nobody Sun May 5 04:16:47 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1568045323; cv=none; d=zoho.com; s=zohoarc; b=NUCsLMAB42Qlk0O+OazDb2HtgZQRMcDVxlQn19SS4OEaE0ITMNXfRk28gd/1QoJ0ELba3p8r+uepL2K4SvTw5geDmJyjU/1/uIXY3ZFNBqFxqDonOSBLDSFRQWZ2nulAV9OvAoBGUvUo7rJz0z8WHLXXfoLy3HtPDnVg3rcMMWY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1568045323; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=61O7VJ+gy8DX+e1XN6t7qf3FntKce9XuJNBZIPOY0PU=; b=iyj42gzX6doIqu94a9qW4SfL2aVgznXc1s7fvC1vjKlrTP98w9fN/lNOIVyyBS+DOblv7celustYw5QBH3//h3aqM+FUVBHBR+gCSJdYH+Rywgd+NqYVuKO90maF1Hprd2cxhKT9JFhlBBrOX5oqHB/2WqCrSEvlvgzKPNXFGh8= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1568045323359798.7157306722962; Mon, 9 Sep 2019 09:08:43 -0700 (PDT) Received: from localhost ([::1]:58552 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i7MDZ-0000zw-Cu for importer@patchew.org; Mon, 09 Sep 2019 12:08:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59824) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i7M4c-0000Ij-Ug for qemu-devel@nongnu.org; Mon, 09 Sep 2019 11:59:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i7M4Y-0001sj-Ur for qemu-devel@nongnu.org; Mon, 09 Sep 2019 11:59:26 -0400 Received: from mout.kundenserver.de ([212.227.126.187]:38335) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i7M4S-0001oi-Sx; Mon, 09 Sep 2019 11:59:17 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue010 [212.227.15.167]) with ESMTPSA (Nemesis) id 1MQNF3-1hlXxO1B8z-00MKyK; Mon, 09 Sep 2019 17:58:39 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Mon, 9 Sep 2019 17:58:13 +0200 Message-Id: <20190909155813.27760-10-laurent@vivier.eu> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190909155813.27760-1-laurent@vivier.eu> References: <20190909155813.27760-1-laurent@vivier.eu> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K1:p5z7uZCy6YgfdAdT6H2Q6C4ZzagPP3oHpPWdj0cFbjwt/A8Qwo2 cOJq/Ggfgh1c0Hpp2FgcEcvkvLPDXNo1EVaCeCOlIJ7U2e//FxMZ9PyW6UVgLe3Q6KLYUfl gHmyysi7LbFcUMLV/mny6daDOCH0redNXl9k9ip3/VxEni6nkkPiOpdOeAIh2IutFpa5EDi yYEq8au7HfijUXBYT9rsw== X-UI-Out-Filterresults: notjunk:1;V03:K0:Iad30P61p7s=:HJJdTyHqzSdiU0YP0Mtaae Q6YVADS1VqvQ5dqpGJ2ik/qX2ryeh/Jpzk4hy7hdzOari3rQIB2k54wP1+n/EHTRyqLyehSin e3AZTZWdjbARh7dsMWog7UpI/fQ37mHfnHNgaEqufZJe9mPCoLmULq11OSr6jnQ05/1/i7ZNO 3Wwb8E1rVh/8gWOJyqcIqQAucNZVnFH9sCTkQ0U8pO3pCnYU7rUX5HkpEHEidwcjtiRToj7wp m2YaIVncoK9o7LXFNgxbf026zX9os+bW2VKrpYMbSwGyEajTIjclp3MkKpWXGMBudd0WjvOBg nBAha9mDaTqBiikZdWSsdmIILgXg4zCo2gtwbmVYrvsL1+/vL4+4S3a7+8+3TCln5cckMa+Do 2W5Tk40tqsJ5Ddrh1pqW3ZFL4sxtdGz84RTw8n6qdMnAg5RaDXiZ5AcoRv6LlEsfINnpyapRk xd10oNGBzUJwX224wDpA3hQ6pBrxa1+rswZXUND6oKIbMxfJyb94pyFRYe8aycRIbnEWp+11Y 01K9wWKFLQ6D7ZSPjAL9MbUeN7++uppbPFjCcB9nUiXQi3hMx8nQEn+SnjbDmk4ka3G5kaS/h ljTa2NWVsdWYmNZwwdu6ONy2zjpvJebKxVLkgae8yRwN9BGVkbKLDJePddmMsyHoqdumnj8kC v3IcCiSKl7hJ+2qub7Q5I4tJPvPx+YExHcC3FNwtPVzNkqgBvfVNCgOkHq4qXaFSwQ1mytMCD h2DGfATdLgfSGoP8ELf7daDugRaKsemlnFSbXZinzRamIdFdxpgWtrWtIib6L+JbLhrljiCZf UmQElt+0yWnlBvHpkJxhN5fQtYkuzsOBQ8fgZTOvyRy2YKC4i0= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 212.227.126.187 Subject: [Qemu-devel] [PATCH v9 9/9] hw/m68k: define Macintosh Quadra 800 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Kevin Wolf , qemu-block@nongnu.org, Thomas Huth , Jason Wang , Mark Cave-Ayland , "Dr . David Alan Gilbert" , Max Reitz , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Gerd Hoffmann , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Paolo Bonzini , Aurelien Jarno , Laurent Vivier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" If you want to test the machine, it doesn't yet boot a MacROM, but you can boot a linux kernel from the command line. You can install your own disk using debian-installer with: ./qemu-system-m68k \ -M q800 \ -serial none -serial mon:stdio \ -m 1000M -drive file=3Dm68k.qcow2,format=3Dqcow2 \ -net nic,model=3Ddp83932,addr=3D09:00:07:12:34:57 \ -append "console=3DttyS0 vga=3Doff" \ -kernel vmlinux-4.15.0-2-m68k \ -initrd initrd.gz \ -drive file=3Ddebian-9.0-m68k-NETINST-1.iso \ -drive file=3Dm68k.qcow2,format=3Dqcow2 \ -nographic If you use a graphic adapter instead of "-nographic", you can use "-g" to s= et the size of the display (I use "-g 1600x800x24"). Co-developed-by: Mark Cave-Ayland Signed-off-by: Mark Cave-Ayland Signed-off-by: Laurent Vivier --- MAINTAINERS | 14 ++ default-configs/m68k-softmmu.mak | 1 + hw/m68k/Kconfig | 12 + hw/m68k/Makefile.objs | 1 + hw/m68k/bootinfo.h | 114 +++++++++ hw/m68k/q800.c | 382 +++++++++++++++++++++++++++++++ 6 files changed, 524 insertions(+) create mode 100644 hw/m68k/bootinfo.h create mode 100644 hw/m68k/q800.c diff --git a/MAINTAINERS b/MAINTAINERS index 50eaf005f4..3c71dbb3a3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -917,6 +917,20 @@ F: hw/m68k/next-*.c F: hw/display/next-fb.c F: include/hw/m68k/next-cube.h =20 +q800 +M: Laurent Vivier +S: Maintained +F: hw/block/swim.c +F: hw/m68k/bootinfo.h +F: hw/display/macfb.c +F: hw/m68k/q800.c +F: hw/misc/mac_via.c +F: hw/nubus/* +F: include/hw/block/swim.h +F: include/hw/display/macfb.h +F: include/hw/misc/mac_via.h +F: include/hw/nubus/* + MicroBlaze Machines ------------------- petalogix_s3adsp1800 diff --git a/default-configs/m68k-softmmu.mak b/default-configs/m68k-softmm= u.mak index d67ab8b96d..6629fd2aa3 100644 --- a/default-configs/m68k-softmmu.mak +++ b/default-configs/m68k-softmmu.mak @@ -7,3 +7,4 @@ CONFIG_SEMIHOSTING=3Dy CONFIG_AN5206=3Dy CONFIG_MCF5208=3Dy CONFIG_NEXTCUBE=3Dy +CONFIG_Q800=3Dy diff --git a/hw/m68k/Kconfig b/hw/m68k/Kconfig index a74fac5abd..f782210b92 100644 --- a/hw/m68k/Kconfig +++ b/hw/m68k/Kconfig @@ -12,3 +12,15 @@ config NEXTCUBE bool select FRAMEBUFFER select ESCC + +config Q800 + bool + select FRAMEBUFFER + select ADB + select MAC_VIA + select ESCC + select ESP + select MACFB + select NUBUS + select DP8393X + select SWIM diff --git a/hw/m68k/Makefile.objs b/hw/m68k/Makefile.objs index f25854730d..b2c9e5ab12 100644 --- a/hw/m68k/Makefile.objs +++ b/hw/m68k/Makefile.objs @@ -1,3 +1,4 @@ obj-$(CONFIG_AN5206) +=3D an5206.o mcf5206.o obj-$(CONFIG_MCF5208) +=3D mcf5208.o mcf_intc.o obj-$(CONFIG_NEXTCUBE) +=3D next-kbd.o next-cube.o +obj-$(CONFIG_Q800) +=3D q800.o diff --git a/hw/m68k/bootinfo.h b/hw/m68k/bootinfo.h new file mode 100644 index 0000000000..5f8ded2686 --- /dev/null +++ b/hw/m68k/bootinfo.h @@ -0,0 +1,114 @@ +/* + * SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note + * + * Bootinfo tags from linux bootinfo.h and bootinfo-mac.h: + * This is an easily parsable and extendable structure containing all + * information to be passed from the bootstrap to the kernel + * + * This structure is copied right after the kernel by the bootstrap + * routine. + */ + +#ifndef HW_M68K_BOOTINFO_H +#define HW_M68K_BOOTINFO_H +struct bi_record { + uint16_t tag; /* tag ID */ + uint16_t size; /* size of record */ + uint32_t data[0]; /* data */ +}; + +/* machine independent tags */ + +#define BI_LAST 0x0000 /* last record */ +#define BI_MACHTYPE 0x0001 /* machine type (u_long) */ +#define BI_CPUTYPE 0x0002 /* cpu type (u_long) */ +#define BI_FPUTYPE 0x0003 /* fpu type (u_long) */ +#define BI_MMUTYPE 0x0004 /* mmu type (u_long) */ +#define BI_MEMCHUNK 0x0005 /* memory chunk address and size */ + /* (struct mem_info) */ +#define BI_RAMDISK 0x0006 /* ramdisk address and size */ + /* (struct mem_info) */ +#define BI_COMMAND_LINE 0x0007 /* kernel command line parameters */ + /* (string) */ + +/* Macintosh-specific tags (all u_long) */ + +#define BI_MAC_MODEL 0x8000 /* Mac Gestalt ID (model type) */ +#define BI_MAC_VADDR 0x8001 /* Mac video base address */ +#define BI_MAC_VDEPTH 0x8002 /* Mac video depth */ +#define BI_MAC_VROW 0x8003 /* Mac video rowbytes */ +#define BI_MAC_VDIM 0x8004 /* Mac video dimensions */ +#define BI_MAC_VLOGICAL 0x8005 /* Mac video logical base */ +#define BI_MAC_SCCBASE 0x8006 /* Mac SCC base address */ +#define BI_MAC_BTIME 0x8007 /* Mac boot time */ +#define BI_MAC_GMTBIAS 0x8008 /* Mac GMT timezone offset */ +#define BI_MAC_MEMSIZE 0x8009 /* Mac RAM size (sanity check) */ +#define BI_MAC_CPUID 0x800a /* Mac CPU type (sanity check) */ +#define BI_MAC_ROMBASE 0x800b /* Mac system ROM base address */ + +/* Macintosh hardware profile data */ + +#define BI_MAC_VIA1BASE 0x8010 /* Mac VIA1 base address (always present) = */ +#define BI_MAC_VIA2BASE 0x8011 /* Mac VIA2 base address (type varies) */ +#define BI_MAC_VIA2TYPE 0x8012 /* Mac VIA2 type (VIA, RBV, OSS) */ +#define BI_MAC_ADBTYPE 0x8013 /* Mac ADB interface type */ +#define BI_MAC_ASCBASE 0x8014 /* Mac Apple Sound Chip base address */ +#define BI_MAC_SCSI5380 0x8015 /* Mac NCR 5380 SCSI (base address, multi)= */ +#define BI_MAC_SCSIDMA 0x8016 /* Mac SCSI DMA (base address) */ +#define BI_MAC_SCSI5396 0x8017 /* Mac NCR 53C96 SCSI (base address, multi= ) */ +#define BI_MAC_IDETYPE 0x8018 /* Mac IDE interface type */ +#define BI_MAC_IDEBASE 0x8019 /* Mac IDE interface base address */ +#define BI_MAC_NUBUS 0x801a /* Mac Nubus type (none, regular, pseudo) = */ +#define BI_MAC_SLOTMASK 0x801b /* Mac Nubus slots present */ +#define BI_MAC_SCCTYPE 0x801c /* Mac SCC serial type (normal, IOP) */ +#define BI_MAC_ETHTYPE 0x801d /* Mac builtin ethernet type (Sonic, MACE = */ +#define BI_MAC_ETHBASE 0x801e /* Mac builtin ethernet base address */ +#define BI_MAC_PMU 0x801f /* Mac power management / poweroff hardwar= e */ +#define BI_MAC_IOP_SWIM 0x8020 /* Mac SWIM floppy IOP */ +#define BI_MAC_IOP_ADB 0x8021 /* Mac ADB IOP */ + +#define BOOTINFO0(as, base, id) \ + do { \ + stw_phys(as, base, id); \ + base +=3D 2; \ + stw_phys(as, base, sizeof(struct bi_record)); \ + base +=3D 2; \ + } while (0) + +#define BOOTINFO1(as, base, id, value) \ + do { \ + stw_phys(as, base, id); \ + base +=3D 2; \ + stw_phys(as, base, sizeof(struct bi_record) + 4); \ + base +=3D 2; \ + stl_phys(as, base, value); \ + base +=3D 4; \ + } while (0) + +#define BOOTINFO2(as, base, id, value1, value2) \ + do { \ + stw_phys(as, base, id); \ + base +=3D 2; \ + stw_phys(as, base, sizeof(struct bi_record) + 8); \ + base +=3D 2; \ + stl_phys(as, base, value1); \ + base +=3D 4; \ + stl_phys(as, base, value2); \ + base +=3D 4; \ + } while (0) + +#define BOOTINFOSTR(as, base, id, string) \ + do { \ + int i; \ + stw_phys(as, base, id); \ + base +=3D 2; \ + stw_phys(as, base, \ + (sizeof(struct bi_record) + strlen(string) + 2) & ~1); \ + base +=3D 2; \ + for (i =3D 0; string[i]; i++) { \ + stb_phys(as, base++, string[i]); \ + } \ + stb_phys(as, base++, 0); \ + base =3D (parameters_base + 1) & ~1; \ + } while (0) +#endif diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c new file mode 100644 index 0000000000..8e0389e050 --- /dev/null +++ b/hw/m68k/q800.c @@ -0,0 +1,382 @@ +/* + * QEMU Motorla 680x0 Macintosh hardware System Emulator + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "sysemu/sysemu.h" +#include "cpu.h" +#include "hw/hw.h" +#include "hw/boards.h" +#include "hw/irq.h" +#include "elf.h" +#include "hw/loader.h" +#include "ui/console.h" +#include "exec/address-spaces.h" +#include "hw/char/escc.h" +#include "hw/sysbus.h" +#include "hw/scsi/esp.h" +#include "bootinfo.h" +#include "hw/misc/mac_via.h" +#include "hw/input/adb.h" +#include "hw/nubus/mac-nubus-bridge.h" +#include "hw/display/macfb.h" +#include "hw/block/swim.h" +#include "net/net.h" +#include "qapi/error.h" +#include "sysemu/qtest.h" +#include "sysemu/runstate.h" +#include "sysemu/reset.h" + +#define MACROM_ADDR 0x40000000 +#define MACROM_SIZE 0x00100000 + +#define MACROM_FILENAME "MacROM.bin" + +#define Q800_MACHINE_ID 35 +#define Q800_CPU_ID (1 << 2) +#define Q800_FPU_ID (1 << 2) +#define Q800_MMU_ID (1 << 2) + +#define MACH_MAC 3 +#define Q800_MAC_CPU_ID 2 + +#define VIA_BASE 0x50f00000 +#define SONIC_PROM_BASE 0x50f08000 +#define SONIC_BASE 0x50f0a000 +#define SCC_BASE 0x50f0c020 +#define ESP_BASE 0x50f10000 +#define ESP_PDMA 0x50f10100 +#define ASC_BASE 0x50F14000 +#define SWIM_BASE 0x50F1E000 +#define NUBUS_SUPER_SLOT_BASE 0x60000000 +#define NUBUS_SLOT_BASE 0xf0000000 + +/* + * the video base, whereas it a Nubus address, + * is needed by the kernel to have early display and + * thus provided by the bootloader + */ +#define VIDEO_BASE 0xf9001000 + +#define MAC_CLOCK 3686418 + +/* + * The GLUE (General Logic Unit) is an Apple custom integrated circuit chip + * that performs a variety of functions (RAM management, clock generation,= ...). + * The GLUE chip receives interrupt requests from various devices, + * assign priority to each, and asserts one or more interrupt line to the + * CPU. + */ + +typedef struct { + M68kCPU *cpu; + uint8_t ipr; +} GLUEState; + +static void GLUE_set_irq(void *opaque, int irq, int level) +{ + GLUEState *s =3D opaque; + int i; + + if (level) { + s->ipr |=3D 1 << irq; + } else { + s->ipr &=3D ~(1 << irq); + } + + for (i =3D 7; i >=3D 0; i--) { + if ((s->ipr >> i) & 1) { + m68k_set_irq_level(s->cpu, i + 1, i + 25); + return; + } + } + m68k_set_irq_level(s->cpu, 0, 0); +} + +static void main_cpu_reset(void *opaque) +{ + M68kCPU *cpu =3D opaque; + CPUState *cs =3D CPU(cpu); + + cpu_reset(cs); + cpu->env.aregs[7] =3D ldl_phys(cs->as, 0); + cpu->env.pc =3D ldl_phys(cs->as, 4); +} + +static void q800_init(MachineState *machine) +{ + M68kCPU *cpu =3D NULL; + int linux_boot; + int32_t kernel_size; + uint64_t elf_entry; + char *filename; + int bios_size; + ram_addr_t initrd_base; + int32_t initrd_size; + MemoryRegion *rom; + MemoryRegion *ram; + ram_addr_t ram_size =3D machine->ram_size; + const char *kernel_filename =3D machine->kernel_filename; + const char *initrd_filename =3D machine->initrd_filename; + const char *kernel_cmdline =3D machine->kernel_cmdline; + hwaddr parameters_base; + CPUState *cs; + DeviceState *dev; + DeviceState *via_dev; + SysBusESPState *sysbus_esp; + ESPState *esp; + SysBusDevice *sysbus; + BusState *adb_bus; + NubusBus *nubus; + GLUEState *irq; + qemu_irq *pic; + + linux_boot =3D (kernel_filename !=3D NULL); + + /* init CPUs */ + cpu =3D M68K_CPU(cpu_create(machine->cpu_type)); + qemu_register_reset(main_cpu_reset, cpu); + + ram =3D g_malloc(sizeof(*ram)); + memory_region_init_ram(ram, NULL, "m68k_mac.ram", ram_size, &error_abo= rt); + memory_region_add_subregion(get_system_memory(), 0, ram); + + /* IRQ Glue */ + + irq =3D g_new0(GLUEState, 1); + irq->cpu =3D cpu; + pic =3D qemu_allocate_irqs(GLUE_set_irq, irq, 8); + + /* VIA */ + + via_dev =3D qdev_create(NULL, TYPE_MAC_VIA); + qdev_init_nofail(via_dev); + sysbus =3D SYS_BUS_DEVICE(via_dev); + sysbus_mmio_map(sysbus, 0, VIA_BASE); + qdev_connect_gpio_out_named(DEVICE(sysbus), "irq", 0, pic[0]); + qdev_connect_gpio_out_named(DEVICE(sysbus), "irq", 1, pic[1]); + + + adb_bus =3D qdev_get_child_bus(via_dev, "adb.0"); + dev =3D qdev_create(adb_bus, TYPE_ADB_KEYBOARD); + qdev_init_nofail(dev); + dev =3D qdev_create(adb_bus, TYPE_ADB_MOUSE); + qdev_init_nofail(dev); + + /* MACSONIC */ + + if (nb_nics > 1) { + error_report("q800 can only have one ethernet interface"); + exit(1); + } + + qemu_check_nic_model(&nd_table[0], "dp83932"); + + /* + * MacSonic driver needs an Apple MAC address + * Valid prefix are: + * 00:05:02 Apple + * 00:80:19 Dayna Communications, Inc. + * 00:A0:40 Apple + * 08:00:07 Apple + * (Q800 use the last one) + */ + nd_table[0].macaddr.a[0] =3D 0x08; + nd_table[0].macaddr.a[1] =3D 0x00; + nd_table[0].macaddr.a[2] =3D 0x07; + + dev =3D qdev_create(NULL, "dp8393x"); + qdev_set_nic_properties(dev, &nd_table[0]); + qdev_prop_set_uint8(dev, "it_shift", 2); + qdev_prop_set_bit(dev, "big_endian", true); + qdev_prop_set_ptr(dev, "dma_mr", get_system_memory()); + qdev_init_nofail(dev); + sysbus =3D SYS_BUS_DEVICE(dev); + sysbus_mmio_map(sysbus, 0, SONIC_BASE); + sysbus_mmio_map(sysbus, 1, SONIC_PROM_BASE); + sysbus_connect_irq(sysbus, 0, pic[2]); + + /* SCC */ + + dev =3D qdev_create(NULL, TYPE_ESCC); + qdev_prop_set_uint32(dev, "disabled", 0); + qdev_prop_set_uint32(dev, "frequency", MAC_CLOCK); + qdev_prop_set_uint32(dev, "it_shift", 1); + qdev_prop_set_bit(dev, "bit_swap", true); + qdev_prop_set_chr(dev, "chrA", serial_hd(0)); + qdev_prop_set_chr(dev, "chrB", serial_hd(1)); + qdev_prop_set_uint32(dev, "chnBtype", 0); + qdev_prop_set_uint32(dev, "chnAtype", 0); + qdev_init_nofail(dev); + sysbus =3D SYS_BUS_DEVICE(dev); + sysbus_connect_irq(sysbus, 0, pic[3]); + sysbus_connect_irq(sysbus, 1, pic[3]); + sysbus_mmio_map(sysbus, 0, SCC_BASE); + + /* SCSI */ + + dev =3D qdev_create(NULL, TYPE_ESP); + sysbus_esp =3D ESP_STATE(dev); + esp =3D &sysbus_esp->esp; + esp->dma_memory_read =3D NULL; + esp->dma_memory_write =3D NULL; + esp->dma_opaque =3D NULL; + sysbus_esp->it_shift =3D 4; + esp->dma_enabled =3D 1; + qdev_init_nofail(dev); + + sysbus =3D SYS_BUS_DEVICE(dev); + sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in_named(via_dev, + "via2-irq", + VIA2_IRQ_SCSI_BIT= )); + sysbus_connect_irq(sysbus, 1, + qdev_get_gpio_in_named(via_dev, "via2-irq", + VIA2_IRQ_SCSI_DATA_BIT)); + sysbus_mmio_map(sysbus, 0, ESP_BASE); + sysbus_mmio_map(sysbus, 1, ESP_PDMA); + + scsi_bus_legacy_handle_cmdline(&esp->bus); + + /* SWIM floppy controller */ + + dev =3D qdev_create(NULL, TYPE_SWIM); + qdev_init_nofail(dev); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, SWIM_BASE); + + /* NuBus */ + + dev =3D qdev_create(NULL, TYPE_MAC_NUBUS_BRIDGE); + qdev_init_nofail(dev); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, NUBUS_SUPER_SLOT_BASE); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, NUBUS_SLOT_BASE); + + nubus =3D MAC_NUBUS_BRIDGE(dev)->bus; + + /* framebuffer in nubus slot #9 */ + + dev =3D qdev_create(BUS(nubus), TYPE_NUBUS_MACFB); + qdev_prop_set_uint32(dev, "width", graphic_width); + qdev_prop_set_uint32(dev, "height", graphic_height); + qdev_prop_set_uint8(dev, "depth", graphic_depth); + qdev_init_nofail(dev); + + cs =3D CPU(cpu); + if (linux_boot) { + uint64_t high; + kernel_size =3D load_elf(kernel_filename, NULL, NULL, NULL, + &elf_entry, NULL, &high, 1, + EM_68K, 0, 0); + if (kernel_size < 0) { + error_report("could not load kernel '%s'", kernel_filename); + exit(1); + } + stl_phys(cs->as, 4, elf_entry); /* reset initial PC */ + parameters_base =3D (high + 1) & ~1; + + BOOTINFO1(cs->as, parameters_base, BI_MACHTYPE, MACH_MAC); + BOOTINFO1(cs->as, parameters_base, BI_FPUTYPE, Q800_FPU_ID); + BOOTINFO1(cs->as, parameters_base, BI_MMUTYPE, Q800_MMU_ID); + BOOTINFO1(cs->as, parameters_base, BI_CPUTYPE, Q800_CPU_ID); + BOOTINFO1(cs->as, parameters_base, BI_MAC_CPUID, Q800_MAC_CPU_ID); + BOOTINFO1(cs->as, parameters_base, BI_MAC_MODEL, Q800_MACHINE_ID); + BOOTINFO1(cs->as, parameters_base, + BI_MAC_MEMSIZE, ram_size >> 20); /* in MB */ + BOOTINFO2(cs->as, parameters_base, BI_MEMCHUNK, 0, ram_size); + BOOTINFO1(cs->as, parameters_base, BI_MAC_VADDR, VIDEO_BASE); + BOOTINFO1(cs->as, parameters_base, BI_MAC_VDEPTH, graphic_depth); + BOOTINFO1(cs->as, parameters_base, BI_MAC_VDIM, + (graphic_height << 16) | graphic_width); + BOOTINFO1(cs->as, parameters_base, BI_MAC_VROW, + (graphic_width * graphic_depth + 7) / 8); + BOOTINFO1(cs->as, parameters_base, BI_MAC_SCCBASE, SCC_BASE); + + if (kernel_cmdline) { + BOOTINFOSTR(cs->as, parameters_base, BI_COMMAND_LINE, + kernel_cmdline); + } + + /* load initrd */ + if (initrd_filename) { + initrd_size =3D get_image_size(initrd_filename); + if (initrd_size < 0) { + error_report("could not load initial ram disk '%s'", + initrd_filename); + exit(1); + } + + initrd_base =3D (ram_size - initrd_size) & TARGET_PAGE_MASK; + load_image_targphys(initrd_filename, initrd_base, + ram_size - initrd_base); + BOOTINFO2(cs->as, parameters_base, BI_RAMDISK, initrd_base, + initrd_size); + } else { + initrd_base =3D 0; + initrd_size =3D 0; + } + BOOTINFO0(cs->as, parameters_base, BI_LAST); + } else { + uint8_t *ptr; + /* allocate and load BIOS */ + rom =3D g_malloc(sizeof(*rom)); + memory_region_init_ram(rom, NULL, "m68k_mac.rom", MACROM_SIZE, + &error_abort); + if (bios_name =3D=3D NULL) { + bios_name =3D MACROM_FILENAME; + } + filename =3D qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); + memory_region_set_readonly(rom, true); + memory_region_add_subregion(get_system_memory(), MACROM_ADDR, rom); + + /* Load MacROM binary */ + if (filename) { + bios_size =3D load_image_targphys(filename, MACROM_ADDR, MACRO= M_SIZE); + g_free(filename); + } else { + bios_size =3D -1; + } + + /* Remove qtest_enabled() check once firmware files are in the tre= e */ + if (!qtest_enabled()) { + if (bios_size < 0 || bios_size > MACROM_SIZE) { + error_report("could not load MacROM '%s'", bios_name); + exit(1); + } + + ptr =3D rom_ptr(MACROM_ADDR, MACROM_SIZE); + stl_phys(cs->as, 0, ldl_p(ptr)); /* reset initial SP */ + stl_phys(cs->as, 4, + MACROM_ADDR + ldl_p(ptr + 4)); /* reset initial PC */ + } + } +} + +static void q800_machine_init(MachineClass *mc) +{ + mc->desc =3D "Macintosh Quadra 800"; + mc->init =3D q800_init; + mc->default_cpu_type =3D M68K_CPU_TYPE_NAME("m68040"); + mc->max_cpus =3D 1; + mc->is_default =3D 0; + mc->block_default_type =3D IF_SCSI; +} + +DEFINE_MACHINE("q800", q800_machine_init) --=20 2.21.0