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Fri, 06 Sep 2019 13:26:40 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: peter.maydell@linaro.org Date: Fri, 6 Sep 2019 21:26:34 +0100 Message-Id: <20190906202636.28642-4-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190906202636.28642-1-alex.bennee@linaro.org> References: <20190906202636.28642-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [PATCH v4 3/4] target/arm: remove run time semihosting checks X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Now we do all our checking and use a common EXCP_SEMIHOST for semihosting operations we can make helper code a lot simpler. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- v2 - fix re-base conflicts - hoist EXCP_SEMIHOST check - comment cleanups v5 - move CONFIG_TCG ifdefs --- target/arm/helper.c | 96 +++++++++++---------------------------------- 1 file changed, 22 insertions(+), 74 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 507026c9154..a87ae6d46a1 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8339,88 +8339,32 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *= cs) new_el, env->pc, pstate_read(env)); } =20 -static inline bool check_for_semihosting(CPUState *cs) -{ +/* + * Do semihosting call and set the appropriate return value. All the + * permission and validity checks have been done at translate time. + * + * We only see semihosting exceptions in TCG only as they are not + * trapped to the hypervisor in KVM. + */ #ifdef CONFIG_TCG - /* Check whether this exception is a semihosting call; if so - * then handle it and return true; otherwise return false. - */ +static void handle_semihosting(CPUState *cs) +{ ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; =20 if (is_a64(env)) { - if (cs->exception_index =3D=3D EXCP_SEMIHOST) { - /* This is always the 64-bit semihosting exception. - * The "is this usermode" and "is semihosting enabled" - * checks have been done at translate time. - */ - qemu_log_mask(CPU_LOG_INT, - "...handling as semihosting call 0x%" PRIx64 "\n= ", - env->xregs[0]); - env->xregs[0] =3D do_arm_semihosting(env); - return true; - } - return false; + qemu_log_mask(CPU_LOG_INT, + "...handling as semihosting call 0x%" PRIx64 "\n", + env->xregs[0]); + env->xregs[0] =3D do_arm_semihosting(env); } else { - uint32_t imm; - - /* Only intercept calls from privileged modes, to provide some - * semblance of security. - */ - if (cs->exception_index !=3D EXCP_SEMIHOST && - (!semihosting_enabled() || - ((env->uncached_cpsr & CPSR_M) =3D=3D ARM_CPU_MODE_USR))) { - return false; - } - - switch (cs->exception_index) { - case EXCP_SEMIHOST: - /* This is always a semihosting call; the "is this usermode" - * and "is semihosting enabled" checks have been done at - * translate time. - */ - break; - case EXCP_SWI: - /* Check for semihosting interrupt. */ - if (env->thumb) { - imm =3D arm_lduw_code(env, env->regs[15] - 2, arm_sctlr_b(= env)) - & 0xff; - if (imm =3D=3D 0xab) { - break; - } - } else { - imm =3D arm_ldl_code(env, env->regs[15] - 4, arm_sctlr_b(e= nv)) - & 0xffffff; - if (imm =3D=3D 0x123456) { - break; - } - } - return false; - case EXCP_BKPT: - /* See if this is a semihosting syscall. */ - if (env->thumb) { - imm =3D arm_lduw_code(env, env->regs[15], arm_sctlr_b(env)) - & 0xff; - if (imm =3D=3D 0xab) { - env->regs[15] +=3D 2; - break; - } - } - return false; - default: - return false; - } - qemu_log_mask(CPU_LOG_INT, "...handling as semihosting call 0x%x\n", env->regs[0]); env->regs[0] =3D do_arm_semihosting(env); - return true; } -#else - return false; -#endif } +#endif =20 /* Handle a CPU exception for A and R profile CPUs. * Do any appropriate logging, handle PSCI calls, and then hand off @@ -8451,13 +8395,17 @@ void arm_cpu_do_interrupt(CPUState *cs) return; } =20 - /* Semihosting semantics depend on the register width of the - * code that caused the exception, not the target exception level, - * so must be handled here. + /* + * Semihosting semantics depend on the register width of the code + * that caused the exception, not the target exception level, so + * must be handled here. */ - if (check_for_semihosting(cs)) { +#ifdef CONFIG_TCG + if (cs->exception_index =3D=3D EXCP_SEMIHOST) { + handle_semihosting(cs); return; } +#endif =20 /* Hooks may change global state so BQL should be held, also the * BQL needs to be held for any modification of --=20 2.20.1