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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id n66sm8104610pfn.90.2019.09.04.13.45.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 13:45:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ahxD9fosMvb1g5phzerFB+P0cZoPHlkyqtQ2Wc64cSg=; b=fQ9FYqH0+U7b2+59Xv0YlyCWmlmeVKSyKcAKW+mIO17JQL4fX7nyAh7Z7BJkBbTtb/ KlSgoGbFQBU3zmyx78NTo0bKVaG5SZZKVSjasbysVpXjAle8ai5UIRWppS5d1truVhlL vpRvkTYyI+ISAEA9Ni1c28nAACxWclFvPe5wO7osJTpsBBRl5c55LSpmTFPEyBi7a+2g dFQK0dGFRS9iljNoPCTPXwTQ6a74LC9ZT1Yb9tyLOdCJz2C/bcNM46MjKj8HNcF1jvx4 s0s8zY98+Qtxeyww/Xo+OsxOFhJb8WypaaRClK4WzJekivVbQNIzurcwjCdeKuuKl0pD lrYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ahxD9fosMvb1g5phzerFB+P0cZoPHlkyqtQ2Wc64cSg=; b=CcKNdCoeqh7N9U9GCaWOskDtKJpeWmdsR38mApjGMTmrEi0G+owOyN3Ld0maPiDSgE t4rNqoqCIrEPMFd1qC3HiudLnZBoU3EgLguZG7KXqn3fymZ1yhNfsiVUYESOh4NCtFR9 rMVMOFo96fA9FOraIADK1vEogdKcs9LIndUKNIJb7sE/FB5qWyKEYbzOC5KK45deFsjJ QCkKcgmmKKWX4UAXhOOTyfuZnNWMaDeXwKEh3VreQum8ac3s+vquXuIjjJjRYg0hNIWB AaVZ7Gxvi5yIK9mGqqXZdnpeUlJqZMBS6bvatI9lV8t8jaqeFrjccinv/HqdOsNrthDQ CLWw== X-Gm-Message-State: APjAAAWwOl/VNfEGmyA4b5Kgkuwoa0yapFKDylIyM+eQPYeHMF48cwAh HQ3/pNJNRbCe4LyTysqCaQ31wMpETi4= X-Google-Smtp-Source: APXvYqzVDdznNGhxI6HXwg8kfm6VmFGRRxG0mAalqnGeV3RgS++n1NGZ5gqgvODJnLVuTLnRXrHaig== X-Received: by 2002:a62:e80e:: with SMTP id c14mr47206pfi.4.1567629910311; Wed, 04 Sep 2019 13:45:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 13:44:55 -0700 Message-Id: <20190904204507.32457-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904204507.32457-1-richard.henderson@linaro.org> References: <20190904204507.32457-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PULL 01/13] target/openrisc: Add DisasContext parameter to check_r0_write X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We will need this context in the next patch. Reviewed-by: Stafford Horne Signed-off-by: Richard Henderson --- target/openrisc/translate.c | 96 +++++++++++++++++++------------------ 1 file changed, 49 insertions(+), 47 deletions(-) diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index b189c506c5..8d72edf9b7 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -163,14 +163,16 @@ static void check_ov64s(DisasContext *dc) } #endif*/ =20 -/* We're about to write to REG. On the off-chance that the user is - writing to R0, re-instate the architectural register. */ -#define check_r0_write(reg) \ - do { \ - if (unlikely(reg =3D=3D 0)) { \ - cpu_R[0] =3D cpu_R0; \ - } \ - } while (0) +/* + * We're about to write to REG. On the off-chance that the user is + * writing to R0, re-instate the architectural register. + */ +static void check_r0_write(DisasContext *dc, int reg) +{ + if (unlikely(reg =3D=3D 0)) { + cpu_R[0] =3D cpu_R0; + } +} =20 static void gen_ove_cy(DisasContext *dc) { @@ -436,98 +438,98 @@ static void gen_msbu(DisasContext *dc, TCGv srca, TCG= v srcb) =20 static bool trans_l_add(DisasContext *dc, arg_dab *a) { - check_r0_write(a->d); + check_r0_write(dc, a->d); gen_add(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; } =20 static bool trans_l_addc(DisasContext *dc, arg_dab *a) { - check_r0_write(a->d); + check_r0_write(dc, a->d); gen_addc(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; } =20 static bool trans_l_sub(DisasContext *dc, arg_dab *a) { - check_r0_write(a->d); + check_r0_write(dc, a->d); gen_sub(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; } =20 static bool trans_l_and(DisasContext *dc, arg_dab *a) { - check_r0_write(a->d); + check_r0_write(dc, a->d); tcg_gen_and_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; } =20 static bool trans_l_or(DisasContext *dc, arg_dab *a) { - check_r0_write(a->d); + check_r0_write(dc, a->d); tcg_gen_or_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; } =20 static bool trans_l_xor(DisasContext *dc, arg_dab *a) { - check_r0_write(a->d); + check_r0_write(dc, a->d); tcg_gen_xor_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; } =20 static bool trans_l_sll(DisasContext *dc, arg_dab *a) { - check_r0_write(a->d); + check_r0_write(dc, a->d); tcg_gen_shl_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; } =20 static bool trans_l_srl(DisasContext *dc, arg_dab *a) { - check_r0_write(a->d); + check_r0_write(dc, a->d); tcg_gen_shr_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; } =20 static bool trans_l_sra(DisasContext *dc, arg_dab *a) { - check_r0_write(a->d); + check_r0_write(dc, a->d); tcg_gen_sar_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; } =20 static bool trans_l_ror(DisasContext *dc, arg_dab *a) { - check_r0_write(a->d); + check_r0_write(dc, a->d); tcg_gen_rotr_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; } =20 static bool trans_l_exths(DisasContext *dc, arg_da *a) { - check_r0_write(a->d); + check_r0_write(dc, a->d); tcg_gen_ext16s_tl(cpu_R[a->d], cpu_R[a->a]); return true; } =20 static bool trans_l_extbs(DisasContext *dc, arg_da *a) { - check_r0_write(a->d); + check_r0_write(dc, a->d); tcg_gen_ext8s_tl(cpu_R[a->d], cpu_R[a->a]); return true; } =20 static bool trans_l_exthz(DisasContext *dc, arg_da *a) { - check_r0_write(a->d); + check_r0_write(dc, a->d); tcg_gen_ext16u_tl(cpu_R[a->d], cpu_R[a->a]); return true; } =20 static bool trans_l_extbz(DisasContext *dc, arg_da *a) { - check_r0_write(a->d); + check_r0_write(dc, a->d); tcg_gen_ext8u_tl(cpu_R[a->d], cpu_R[a->a]); return true; } @@ -536,7 +538,7 @@ static bool trans_l_cmov(DisasContext *dc, arg_dab *a) { TCGv zero; =20 - check_r0_write(a->d); + check_r0_write(dc, a->d); zero =3D tcg_const_tl(0); tcg_gen_movcond_tl(TCG_COND_NE, cpu_R[a->d], cpu_sr_f, zero, cpu_R[a->a], cpu_R[a->b]); @@ -546,7 +548,7 @@ static bool trans_l_cmov(DisasContext *dc, arg_dab *a) =20 static bool trans_l_ff1(DisasContext *dc, arg_da *a) { - check_r0_write(a->d); + check_r0_write(dc, a->d); tcg_gen_ctzi_tl(cpu_R[a->d], cpu_R[a->a], -1); tcg_gen_addi_tl(cpu_R[a->d], cpu_R[a->d], 1); return true; @@ -554,7 +556,7 @@ static bool trans_l_ff1(DisasContext *dc, arg_da *a) =20 static bool trans_l_fl1(DisasContext *dc, arg_da *a) { - check_r0_write(a->d); + check_r0_write(dc, a->d); tcg_gen_clzi_tl(cpu_R[a->d], cpu_R[a->a], TARGET_LONG_BITS); tcg_gen_subfi_tl(cpu_R[a->d], TARGET_LONG_BITS, cpu_R[a->d]); return true; @@ -562,28 +564,28 @@ static bool trans_l_fl1(DisasContext *dc, arg_da *a) =20 static bool trans_l_mul(DisasContext *dc, arg_dab *a) { - check_r0_write(a->d); + check_r0_write(dc, a->d); gen_mul(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; } =20 static bool trans_l_mulu(DisasContext *dc, arg_dab *a) { - check_r0_write(a->d); + check_r0_write(dc, a->d); gen_mulu(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; } =20 static bool trans_l_div(DisasContext *dc, arg_dab *a) { - check_r0_write(a->d); + check_r0_write(dc, a->d); gen_div(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; } =20 static bool trans_l_divu(DisasContext *dc, arg_dab *a) { - check_r0_write(a->d); + check_r0_write(dc, a->d); gen_divu(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; } @@ -671,7 +673,7 @@ static bool trans_l_lwa(DisasContext *dc, arg_load *a) { TCGv ea; =20 - check_r0_write(a->d); + check_r0_write(dc, a->d); ea =3D tcg_temp_new(); tcg_gen_addi_tl(ea, cpu_R[a->a], a->i); tcg_gen_qemu_ld_tl(cpu_R[a->d], ea, dc->mem_idx, MO_TEUL); @@ -685,7 +687,7 @@ static void do_load(DisasContext *dc, arg_load *a, MemO= p mop) { TCGv ea; =20 - check_r0_write(a->d); + check_r0_write(dc, a->d); ea =3D tcg_temp_new(); tcg_gen_addi_tl(ea, cpu_R[a->a], a->i); tcg_gen_qemu_ld_tl(cpu_R[a->d], ea, dc->mem_idx, mop); @@ -798,7 +800,7 @@ static bool trans_l_addi(DisasContext *dc, arg_rri *a) { TCGv t0; =20 - check_r0_write(a->d); + check_r0_write(dc, a->d); t0 =3D tcg_const_tl(a->i); gen_add(dc, cpu_R[a->d], cpu_R[a->a], t0); tcg_temp_free(t0); @@ -809,7 +811,7 @@ static bool trans_l_addic(DisasContext *dc, arg_rri *a) { TCGv t0; =20 - check_r0_write(a->d); + check_r0_write(dc, a->d); t0 =3D tcg_const_tl(a->i); gen_addc(dc, cpu_R[a->d], cpu_R[a->a], t0); tcg_temp_free(t0); @@ -820,7 +822,7 @@ static bool trans_l_muli(DisasContext *dc, arg_rri *a) { TCGv t0; =20 - check_r0_write(a->d); + check_r0_write(dc, a->d); t0 =3D tcg_const_tl(a->i); gen_mul(dc, cpu_R[a->d], cpu_R[a->a], t0); tcg_temp_free(t0); @@ -839,28 +841,28 @@ static bool trans_l_maci(DisasContext *dc, arg_l_maci= *a) =20 static bool trans_l_andi(DisasContext *dc, arg_rrk *a) { - check_r0_write(a->d); + check_r0_write(dc, a->d); tcg_gen_andi_tl(cpu_R[a->d], cpu_R[a->a], a->k); return true; } =20 static bool trans_l_ori(DisasContext *dc, arg_rrk *a) { - check_r0_write(a->d); + check_r0_write(dc, a->d); tcg_gen_ori_tl(cpu_R[a->d], cpu_R[a->a], a->k); return true; } =20 static bool trans_l_xori(DisasContext *dc, arg_rri *a) { - check_r0_write(a->d); + check_r0_write(dc, a->d); tcg_gen_xori_tl(cpu_R[a->d], cpu_R[a->a], a->i); return true; } =20 static bool trans_l_mfspr(DisasContext *dc, arg_l_mfspr *a) { - check_r0_write(a->d); + check_r0_write(dc, a->d); =20 if (is_user(dc)) { gen_illegal_exception(dc); @@ -927,42 +929,42 @@ static bool trans_l_msbu(DisasContext *dc, arg_ab *a) =20 static bool trans_l_slli(DisasContext *dc, arg_dal *a) { - check_r0_write(a->d); + check_r0_write(dc, a->d); tcg_gen_shli_tl(cpu_R[a->d], cpu_R[a->a], a->l & (TARGET_LONG_BITS - 1= )); return true; } =20 static bool trans_l_srli(DisasContext *dc, arg_dal *a) { - check_r0_write(a->d); + check_r0_write(dc, a->d); tcg_gen_shri_tl(cpu_R[a->d], cpu_R[a->a], a->l & (TARGET_LONG_BITS - 1= )); return true; } =20 static bool trans_l_srai(DisasContext *dc, arg_dal *a) { - check_r0_write(a->d); + check_r0_write(dc, a->d); tcg_gen_sari_tl(cpu_R[a->d], cpu_R[a->a], a->l & (TARGET_LONG_BITS - 1= )); return true; } =20 static bool trans_l_rori(DisasContext *dc, arg_dal *a) { - check_r0_write(a->d); + check_r0_write(dc, a->d); tcg_gen_rotri_tl(cpu_R[a->d], cpu_R[a->a], a->l & (TARGET_LONG_BITS - = 1)); return true; } =20 static bool trans_l_movhi(DisasContext *dc, arg_l_movhi *a) { - check_r0_write(a->d); + check_r0_write(dc, a->d); tcg_gen_movi_tl(cpu_R[a->d], a->k << 16); return true; } =20 static bool trans_l_macrc(DisasContext *dc, arg_l_macrc *a) { - check_r0_write(a->d); + check_r0_write(dc, a->d); tcg_gen_trunc_i64_tl(cpu_R[a->d], cpu_mac); tcg_gen_movi_i64(cpu_mac, 0); return true; @@ -1134,7 +1136,7 @@ static bool trans_l_rfe(DisasContext *dc, arg_l_rfe *= a) static void do_fp2(DisasContext *dc, arg_da *a, void (*fn)(TCGv, TCGv_env, TCGv)) { - check_r0_write(a->d); + check_r0_write(dc, a->d); fn(cpu_R[a->d], cpu_env, cpu_R[a->a]); gen_helper_update_fpcsr(cpu_env); } @@ -1142,7 +1144,7 @@ static void do_fp2(DisasContext *dc, arg_da *a, static void do_fp3(DisasContext *dc, arg_dab *a, void (*fn)(TCGv, TCGv_env, TCGv, TCGv)) { - check_r0_write(a->d); + check_r0_write(dc, a->d); fn(cpu_R[a->d], cpu_env, cpu_R[a->a], cpu_R[a->b]); gen_helper_update_fpcsr(cpu_env); } @@ -1206,7 +1208,7 @@ static bool trans_lf_ftoi_s(DisasContext *dc, arg_da = *a) =20 static bool trans_lf_madd_s(DisasContext *dc, arg_dab *a) { - check_r0_write(a->d); + check_r0_write(dc, a->d); gen_helper_float_madd_s(cpu_R[a->d], cpu_env, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); gen_helper_update_fpcsr(cpu_env); --=20 2.17.1 From nobody Mon May 6 11:48:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id n66sm8104610pfn.90.2019.09.04.13.45.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 13:45:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=0GH6PQWyMN8qVVsEVdWkb1w1xlZ3eBiDk1i7JQaCd9s=; b=NGKbyIa8i/mejaB6g9tVBqTY2aMMO2i1tyzgM5rBUP9rsX7PBILhlqYX8ZjUkRHoQR QCRNcp6NY4bj10ZQNzkF17TQgcCU6Do3YzsU4XLz7j00PWBtY7qGvnvBVyLUFJpE1E4d 8ZD01VMcBZydHxFnGizWFz+ynsqwoWyBkykfQOwF8KFdrVovSSTrWLAscD94tX/ZjCqo Nz48651yft867dbCcuRZ7N1p2ppCxeTQ2enEzB8TVBCC7SC4up8dSl2riTqGmiQterKk xQcMpHX4XeSYaN9oY0bRhQbrDkxiOFatJb18XacKLNqf0W4B4Eieway0ZTXB7uxop3Nk t5dw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=0GH6PQWyMN8qVVsEVdWkb1w1xlZ3eBiDk1i7JQaCd9s=; b=rgbPP4TFwwu5+sq2nKVoVUPcPWPlVE6SwlySTWMysVs/Rp/qiN0xJ00AshqEBgflKk tPuO+qLS4ON3fDpFjnsPFhUqsgk3PfhvsrbfD965NdBsFj7UXkVCVHfEn+kEm5Eanqg9 V1MNtEOmQJx71Sal4ukzQMfzmmW7i9K9U8TcQNZCLRr2YhSHQ0vhvxTA8MpKnlEG8J5b qCkYqDmXHY67DuOasiIfatRkIJ0nStXMcLAHKJ3evkpbIHJ6i1+LBqwXx+jMRITaiCrF sxgN8OtrjUOfwZGcZoovRNicqxvE/uSYkIPegfZmbgheNYu/kpSDF+3uNyVNwm0apeRp CShg== X-Gm-Message-State: APjAAAWOBrVvkL3HgPXj3hNFW4adJKX8yq/uwMNb4yV6ejKxxoafbkkX NMI+5IPLYqAJe4wfD5mi5hebDkyFiic= X-Google-Smtp-Source: APXvYqxLFnBhzEweirub4bd8Os8ABFJaKhnaLzgRpS3AOQZ2PklrEYZhev6kXnEnU9JA9qwNE77RRA== X-Received: by 2002:aa7:998f:: with SMTP id k15mr34792670pfh.203.1567629911497; Wed, 04 Sep 2019 13:45:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 13:44:56 -0700 Message-Id: <20190904204507.32457-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904204507.32457-1-richard.henderson@linaro.org> References: <20190904204507.32457-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PULL 02/13] target/openrisc: Replace cpu register array with a function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The writes to cpu_R[0] are now a race across threads, now that we do code generation in parallel. Stage the change by introducing a function to return the temp for R0. Reviewed-by: Stafford Horne Signed-off-by: Richard Henderson --- target/openrisc/translate.c | 213 ++++++++++++++++++++---------------- 1 file changed, 116 insertions(+), 97 deletions(-) diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 8d72edf9b7..d635a46f7e 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -63,7 +63,7 @@ static inline bool is_user(DisasContext *dc) #include "decode.inc.c" =20 static TCGv cpu_sr; -static TCGv cpu_R[32]; +static TCGv cpu_regs[32]; static TCGv cpu_R0; static TCGv cpu_pc; static TCGv jmp_pc; /* l.jr/l.jalr temp pc */ @@ -117,12 +117,12 @@ void openrisc_translate_init(void) offsetof(CPUOpenRISCState, mac), "mac"); for (i =3D 0; i < 32; i++) { - cpu_R[i] =3D tcg_global_mem_new(cpu_env, - offsetof(CPUOpenRISCState, - shadow_gpr[0][i]), - regnames[i]); + cpu_regs[i] =3D tcg_global_mem_new(cpu_env, + offsetof(CPUOpenRISCState, + shadow_gpr[0][i]), + regnames[i]); } - cpu_R0 =3D cpu_R[0]; + cpu_R0 =3D cpu_regs[0]; } =20 static void gen_exception(DisasContext *dc, unsigned int excp) @@ -163,6 +163,11 @@ static void check_ov64s(DisasContext *dc) } #endif*/ =20 +static TCGv cpu_R(DisasContext *dc, int reg) +{ + return cpu_regs[reg]; +} + /* * We're about to write to REG. On the off-chance that the user is * writing to R0, re-instate the architectural register. @@ -170,7 +175,7 @@ static void check_ov64s(DisasContext *dc) static void check_r0_write(DisasContext *dc, int reg) { if (unlikely(reg =3D=3D 0)) { - cpu_R[0] =3D cpu_R0; + cpu_regs[0] =3D cpu_R0; } } =20 @@ -439,98 +444,98 @@ static void gen_msbu(DisasContext *dc, TCGv srca, TCG= v srcb) static bool trans_l_add(DisasContext *dc, arg_dab *a) { check_r0_write(dc, a->d); - gen_add(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); + gen_add(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); return true; } =20 static bool trans_l_addc(DisasContext *dc, arg_dab *a) { check_r0_write(dc, a->d); - gen_addc(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); + gen_addc(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); return true; } =20 static bool trans_l_sub(DisasContext *dc, arg_dab *a) { check_r0_write(dc, a->d); - gen_sub(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); + gen_sub(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); return true; } =20 static bool trans_l_and(DisasContext *dc, arg_dab *a) { check_r0_write(dc, a->d); - tcg_gen_and_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); + tcg_gen_and_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); return true; } =20 static bool trans_l_or(DisasContext *dc, arg_dab *a) { check_r0_write(dc, a->d); - tcg_gen_or_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); + tcg_gen_or_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); return true; } =20 static bool trans_l_xor(DisasContext *dc, arg_dab *a) { check_r0_write(dc, a->d); - tcg_gen_xor_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); + tcg_gen_xor_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); return true; } =20 static bool trans_l_sll(DisasContext *dc, arg_dab *a) { check_r0_write(dc, a->d); - tcg_gen_shl_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); + tcg_gen_shl_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); return true; } =20 static bool trans_l_srl(DisasContext *dc, arg_dab *a) { check_r0_write(dc, a->d); - tcg_gen_shr_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); + tcg_gen_shr_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); return true; } =20 static bool trans_l_sra(DisasContext *dc, arg_dab *a) { check_r0_write(dc, a->d); - tcg_gen_sar_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); + tcg_gen_sar_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); return true; } =20 static bool trans_l_ror(DisasContext *dc, arg_dab *a) { check_r0_write(dc, a->d); - tcg_gen_rotr_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); + tcg_gen_rotr_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); return true; } =20 static bool trans_l_exths(DisasContext *dc, arg_da *a) { check_r0_write(dc, a->d); - tcg_gen_ext16s_tl(cpu_R[a->d], cpu_R[a->a]); + tcg_gen_ext16s_tl(cpu_R(dc, a->d), cpu_R(dc, a->a)); return true; } =20 static bool trans_l_extbs(DisasContext *dc, arg_da *a) { check_r0_write(dc, a->d); - tcg_gen_ext8s_tl(cpu_R[a->d], cpu_R[a->a]); + tcg_gen_ext8s_tl(cpu_R(dc, a->d), cpu_R(dc, a->a)); return true; } =20 static bool trans_l_exthz(DisasContext *dc, arg_da *a) { check_r0_write(dc, a->d); - tcg_gen_ext16u_tl(cpu_R[a->d], cpu_R[a->a]); + tcg_gen_ext16u_tl(cpu_R(dc, a->d), cpu_R(dc, a->a)); return true; } =20 static bool trans_l_extbz(DisasContext *dc, arg_da *a) { check_r0_write(dc, a->d); - tcg_gen_ext8u_tl(cpu_R[a->d], cpu_R[a->a]); + tcg_gen_ext8u_tl(cpu_R(dc, a->d), cpu_R(dc, a->a)); return true; } =20 @@ -540,8 +545,8 @@ static bool trans_l_cmov(DisasContext *dc, arg_dab *a) =20 check_r0_write(dc, a->d); zero =3D tcg_const_tl(0); - tcg_gen_movcond_tl(TCG_COND_NE, cpu_R[a->d], cpu_sr_f, zero, - cpu_R[a->a], cpu_R[a->b]); + tcg_gen_movcond_tl(TCG_COND_NE, cpu_R(dc, a->d), cpu_sr_f, zero, + cpu_R(dc, a->a), cpu_R(dc, a->b)); tcg_temp_free(zero); return true; } @@ -549,56 +554,56 @@ static bool trans_l_cmov(DisasContext *dc, arg_dab *a) static bool trans_l_ff1(DisasContext *dc, arg_da *a) { check_r0_write(dc, a->d); - tcg_gen_ctzi_tl(cpu_R[a->d], cpu_R[a->a], -1); - tcg_gen_addi_tl(cpu_R[a->d], cpu_R[a->d], 1); + tcg_gen_ctzi_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), -1); + tcg_gen_addi_tl(cpu_R(dc, a->d), cpu_R(dc, a->d), 1); return true; } =20 static bool trans_l_fl1(DisasContext *dc, arg_da *a) { check_r0_write(dc, a->d); - tcg_gen_clzi_tl(cpu_R[a->d], cpu_R[a->a], TARGET_LONG_BITS); - tcg_gen_subfi_tl(cpu_R[a->d], TARGET_LONG_BITS, cpu_R[a->d]); + tcg_gen_clzi_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), TARGET_LONG_BITS); + tcg_gen_subfi_tl(cpu_R(dc, a->d), TARGET_LONG_BITS, cpu_R(dc, a->d)); return true; } =20 static bool trans_l_mul(DisasContext *dc, arg_dab *a) { check_r0_write(dc, a->d); - gen_mul(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); + gen_mul(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); return true; } =20 static bool trans_l_mulu(DisasContext *dc, arg_dab *a) { check_r0_write(dc, a->d); - gen_mulu(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); + gen_mulu(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); return true; } =20 static bool trans_l_div(DisasContext *dc, arg_dab *a) { check_r0_write(dc, a->d); - gen_div(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); + gen_div(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); return true; } =20 static bool trans_l_divu(DisasContext *dc, arg_dab *a) { check_r0_write(dc, a->d); - gen_divu(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); + gen_divu(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); return true; } =20 static bool trans_l_muld(DisasContext *dc, arg_ab *a) { - gen_muld(dc, cpu_R[a->a], cpu_R[a->b]); + gen_muld(dc, cpu_R(dc, a->a), cpu_R(dc, a->b)); return true; } =20 static bool trans_l_muldu(DisasContext *dc, arg_ab *a) { - gen_muldu(dc, cpu_R[a->a], cpu_R[a->b]); + gen_muldu(dc, cpu_R(dc, a->a), cpu_R(dc, a->b)); return true; } =20 @@ -617,7 +622,7 @@ static bool trans_l_jal(DisasContext *dc, arg_l_jal *a) target_ulong tmp_pc =3D dc->base.pc_next + a->n * 4; target_ulong ret_pc =3D dc->base.pc_next + 8; =20 - tcg_gen_movi_tl(cpu_R[9], ret_pc); + tcg_gen_movi_tl(cpu_regs[9], ret_pc); /* Optimize jal being used to load the PC for PIC. */ if (tmp_pc !=3D ret_pc) { tcg_gen_movi_tl(jmp_pc, tmp_pc); @@ -656,15 +661,15 @@ static bool trans_l_bnf(DisasContext *dc, arg_l_bf *a) =20 static bool trans_l_jr(DisasContext *dc, arg_l_jr *a) { - tcg_gen_mov_tl(jmp_pc, cpu_R[a->b]); + tcg_gen_mov_tl(jmp_pc, cpu_R(dc, a->b)); dc->delayed_branch =3D 2; return true; } =20 static bool trans_l_jalr(DisasContext *dc, arg_l_jalr *a) { - tcg_gen_mov_tl(jmp_pc, cpu_R[a->b]); - tcg_gen_movi_tl(cpu_R[9], dc->base.pc_next + 8); + tcg_gen_mov_tl(jmp_pc, cpu_R(dc, a->b)); + tcg_gen_movi_tl(cpu_regs[9], dc->base.pc_next + 8); dc->delayed_branch =3D 2; return true; } @@ -675,10 +680,10 @@ static bool trans_l_lwa(DisasContext *dc, arg_load *a) =20 check_r0_write(dc, a->d); ea =3D tcg_temp_new(); - tcg_gen_addi_tl(ea, cpu_R[a->a], a->i); - tcg_gen_qemu_ld_tl(cpu_R[a->d], ea, dc->mem_idx, MO_TEUL); + tcg_gen_addi_tl(ea, cpu_R(dc, a->a), a->i); + tcg_gen_qemu_ld_tl(cpu_R(dc, a->d), ea, dc->mem_idx, MO_TEUL); tcg_gen_mov_tl(cpu_lock_addr, ea); - tcg_gen_mov_tl(cpu_lock_value, cpu_R[a->d]); + tcg_gen_mov_tl(cpu_lock_value, cpu_R(dc, a->d)); tcg_temp_free(ea); return true; } @@ -689,8 +694,8 @@ static void do_load(DisasContext *dc, arg_load *a, MemO= p mop) =20 check_r0_write(dc, a->d); ea =3D tcg_temp_new(); - tcg_gen_addi_tl(ea, cpu_R[a->a], a->i); - tcg_gen_qemu_ld_tl(cpu_R[a->d], ea, dc->mem_idx, mop); + tcg_gen_addi_tl(ea, cpu_R(dc, a->a), a->i); + tcg_gen_qemu_ld_tl(cpu_R(dc, a->d), ea, dc->mem_idx, mop); tcg_temp_free(ea); } =20 @@ -736,13 +741,13 @@ static bool trans_l_swa(DisasContext *dc, arg_store *= a) TCGLabel *lab_fail, *lab_done; =20 ea =3D tcg_temp_new(); - tcg_gen_addi_tl(ea, cpu_R[a->a], a->i); + tcg_gen_addi_tl(ea, cpu_R(dc, a->a), a->i); =20 /* For TB_FLAGS_R0_0, the branch below invalidates the temporary assig= ned - to cpu_R[0]. Since l.swa is quite often immediately followed by a + to cpu_regs[0]. Since l.swa is quite often immediately followed by= a branch, don't bother reallocating; finish the TB using the "real" R= 0. This also takes care of RB input across the branch. */ - cpu_R[0] =3D cpu_R0; + cpu_regs[0] =3D cpu_R0; =20 lab_fail =3D gen_new_label(); lab_done =3D gen_new_label(); @@ -751,7 +756,7 @@ static bool trans_l_swa(DisasContext *dc, arg_store *a) =20 val =3D tcg_temp_new(); tcg_gen_atomic_cmpxchg_tl(val, cpu_lock_addr, cpu_lock_value, - cpu_R[a->b], dc->mem_idx, MO_TEUL); + cpu_regs[a->b], dc->mem_idx, MO_TEUL); tcg_gen_setcond_tl(TCG_COND_EQ, cpu_sr_f, val, cpu_lock_value); tcg_temp_free(val); =20 @@ -768,8 +773,8 @@ static bool trans_l_swa(DisasContext *dc, arg_store *a) static void do_store(DisasContext *dc, arg_store *a, MemOp mop) { TCGv t0 =3D tcg_temp_new(); - tcg_gen_addi_tl(t0, cpu_R[a->a], a->i); - tcg_gen_qemu_st_tl(cpu_R[a->b], t0, dc->mem_idx, mop); + tcg_gen_addi_tl(t0, cpu_R(dc, a->a), a->i); + tcg_gen_qemu_st_tl(cpu_R(dc, a->b), t0, dc->mem_idx, mop); tcg_temp_free(t0); } =20 @@ -802,7 +807,7 @@ static bool trans_l_addi(DisasContext *dc, arg_rri *a) =20 check_r0_write(dc, a->d); t0 =3D tcg_const_tl(a->i); - gen_add(dc, cpu_R[a->d], cpu_R[a->a], t0); + gen_add(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), t0); tcg_temp_free(t0); return true; } @@ -813,7 +818,7 @@ static bool trans_l_addic(DisasContext *dc, arg_rri *a) =20 check_r0_write(dc, a->d); t0 =3D tcg_const_tl(a->i); - gen_addc(dc, cpu_R[a->d], cpu_R[a->a], t0); + gen_addc(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), t0); tcg_temp_free(t0); return true; } @@ -824,7 +829,7 @@ static bool trans_l_muli(DisasContext *dc, arg_rri *a) =20 check_r0_write(dc, a->d); t0 =3D tcg_const_tl(a->i); - gen_mul(dc, cpu_R[a->d], cpu_R[a->a], t0); + gen_mul(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), t0); tcg_temp_free(t0); return true; } @@ -834,7 +839,7 @@ static bool trans_l_maci(DisasContext *dc, arg_l_maci *= a) TCGv t0; =20 t0 =3D tcg_const_tl(a->i); - gen_mac(dc, cpu_R[a->a], t0); + gen_mac(dc, cpu_R(dc, a->a), t0); tcg_temp_free(t0); return true; } @@ -842,21 +847,21 @@ static bool trans_l_maci(DisasContext *dc, arg_l_maci= *a) static bool trans_l_andi(DisasContext *dc, arg_rrk *a) { check_r0_write(dc, a->d); - tcg_gen_andi_tl(cpu_R[a->d], cpu_R[a->a], a->k); + tcg_gen_andi_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), a->k); return true; } =20 static bool trans_l_ori(DisasContext *dc, arg_rrk *a) { check_r0_write(dc, a->d); - tcg_gen_ori_tl(cpu_R[a->d], cpu_R[a->a], a->k); + tcg_gen_ori_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), a->k); return true; } =20 static bool trans_l_xori(DisasContext *dc, arg_rri *a) { check_r0_write(dc, a->d); - tcg_gen_xori_tl(cpu_R[a->d], cpu_R[a->a], a->i); + tcg_gen_xori_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), a->i); return true; } =20 @@ -868,8 +873,8 @@ static bool trans_l_mfspr(DisasContext *dc, arg_l_mfspr= *a) gen_illegal_exception(dc); } else { TCGv spr =3D tcg_temp_new(); - tcg_gen_ori_tl(spr, cpu_R[a->a], a->k); - gen_helper_mfspr(cpu_R[a->d], cpu_env, cpu_R[a->d], spr); + tcg_gen_ori_tl(spr, cpu_R(dc, a->a), a->k); + gen_helper_mfspr(cpu_R(dc, a->d), cpu_env, cpu_R(dc, a->d), spr); tcg_temp_free(spr); } return true; @@ -896,8 +901,8 @@ static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr= *a) dc->base.is_jmp =3D DISAS_EXIT; =20 spr =3D tcg_temp_new(); - tcg_gen_ori_tl(spr, cpu_R[a->a], a->k); - gen_helper_mtspr(cpu_env, spr, cpu_R[a->b]); + tcg_gen_ori_tl(spr, cpu_R(dc, a->a), a->k); + gen_helper_mtspr(cpu_env, spr, cpu_R(dc, a->b)); tcg_temp_free(spr); } return true; @@ -905,188 +910,202 @@ static bool trans_l_mtspr(DisasContext *dc, arg_l_m= tspr *a) =20 static bool trans_l_mac(DisasContext *dc, arg_ab *a) { - gen_mac(dc, cpu_R[a->a], cpu_R[a->b]); + gen_mac(dc, cpu_R(dc, a->a), cpu_R(dc, a->b)); return true; } =20 static bool trans_l_msb(DisasContext *dc, arg_ab *a) { - gen_msb(dc, cpu_R[a->a], cpu_R[a->b]); + gen_msb(dc, cpu_R(dc, a->a), cpu_R(dc, a->b)); return true; } =20 static bool trans_l_macu(DisasContext *dc, arg_ab *a) { - gen_macu(dc, cpu_R[a->a], cpu_R[a->b]); + gen_macu(dc, cpu_R(dc, a->a), cpu_R(dc, a->b)); return true; } =20 static bool trans_l_msbu(DisasContext *dc, arg_ab *a) { - gen_msbu(dc, cpu_R[a->a], cpu_R[a->b]); + gen_msbu(dc, cpu_R(dc, a->a), cpu_R(dc, a->b)); return true; } =20 static bool trans_l_slli(DisasContext *dc, arg_dal *a) { check_r0_write(dc, a->d); - tcg_gen_shli_tl(cpu_R[a->d], cpu_R[a->a], a->l & (TARGET_LONG_BITS - 1= )); + tcg_gen_shli_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), + a->l & (TARGET_LONG_BITS - 1)); return true; } =20 static bool trans_l_srli(DisasContext *dc, arg_dal *a) { check_r0_write(dc, a->d); - tcg_gen_shri_tl(cpu_R[a->d], cpu_R[a->a], a->l & (TARGET_LONG_BITS - 1= )); + tcg_gen_shri_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), + a->l & (TARGET_LONG_BITS - 1)); return true; } =20 static bool trans_l_srai(DisasContext *dc, arg_dal *a) { check_r0_write(dc, a->d); - tcg_gen_sari_tl(cpu_R[a->d], cpu_R[a->a], a->l & (TARGET_LONG_BITS - 1= )); + tcg_gen_sari_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), + a->l & (TARGET_LONG_BITS - 1)); return true; } =20 static bool trans_l_rori(DisasContext *dc, arg_dal *a) { check_r0_write(dc, a->d); - tcg_gen_rotri_tl(cpu_R[a->d], cpu_R[a->a], a->l & (TARGET_LONG_BITS - = 1)); + tcg_gen_rotri_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), + a->l & (TARGET_LONG_BITS - 1)); return true; } =20 static bool trans_l_movhi(DisasContext *dc, arg_l_movhi *a) { check_r0_write(dc, a->d); - tcg_gen_movi_tl(cpu_R[a->d], a->k << 16); + tcg_gen_movi_tl(cpu_R(dc, a->d), a->k << 16); return true; } =20 static bool trans_l_macrc(DisasContext *dc, arg_l_macrc *a) { check_r0_write(dc, a->d); - tcg_gen_trunc_i64_tl(cpu_R[a->d], cpu_mac); + tcg_gen_trunc_i64_tl(cpu_R(dc, a->d), cpu_mac); tcg_gen_movi_i64(cpu_mac, 0); return true; } =20 static bool trans_l_sfeq(DisasContext *dc, arg_ab *a) { - tcg_gen_setcond_tl(TCG_COND_EQ, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); + tcg_gen_setcond_tl(TCG_COND_EQ, cpu_sr_f, + cpu_R(dc, a->a), cpu_R(dc, a->b)); return true; } =20 static bool trans_l_sfne(DisasContext *dc, arg_ab *a) { - tcg_gen_setcond_tl(TCG_COND_NE, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); + tcg_gen_setcond_tl(TCG_COND_NE, cpu_sr_f, + cpu_R(dc, a->a), cpu_R(dc, a->b)); return true; } =20 static bool trans_l_sfgtu(DisasContext *dc, arg_ab *a) { - tcg_gen_setcond_tl(TCG_COND_GTU, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); + tcg_gen_setcond_tl(TCG_COND_GTU, cpu_sr_f, + cpu_R(dc, a->a), cpu_R(dc, a->b)); return true; } =20 static bool trans_l_sfgeu(DisasContext *dc, arg_ab *a) { - tcg_gen_setcond_tl(TCG_COND_GEU, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); + tcg_gen_setcond_tl(TCG_COND_GEU, cpu_sr_f, + cpu_R(dc, a->a), cpu_R(dc, a->b)); return true; } =20 static bool trans_l_sfltu(DisasContext *dc, arg_ab *a) { - tcg_gen_setcond_tl(TCG_COND_LTU, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); + tcg_gen_setcond_tl(TCG_COND_LTU, cpu_sr_f, + cpu_R(dc, a->a), cpu_R(dc, a->b)); return true; } =20 static bool trans_l_sfleu(DisasContext *dc, arg_ab *a) { - tcg_gen_setcond_tl(TCG_COND_LEU, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); + tcg_gen_setcond_tl(TCG_COND_LEU, cpu_sr_f, + cpu_R(dc, a->a), cpu_R(dc, a->b)); return true; } =20 static bool trans_l_sfgts(DisasContext *dc, arg_ab *a) { - tcg_gen_setcond_tl(TCG_COND_GT, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); + tcg_gen_setcond_tl(TCG_COND_GT, cpu_sr_f, + cpu_R(dc, a->a), cpu_R(dc, a->b)); return true; } =20 static bool trans_l_sfges(DisasContext *dc, arg_ab *a) { - tcg_gen_setcond_tl(TCG_COND_GE, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); + tcg_gen_setcond_tl(TCG_COND_GE, cpu_sr_f, + cpu_R(dc, a->a), cpu_R(dc, a->b)); return true; } =20 static bool trans_l_sflts(DisasContext *dc, arg_ab *a) { - tcg_gen_setcond_tl(TCG_COND_LT, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); + tcg_gen_setcond_tl(TCG_COND_LT, cpu_sr_f, + cpu_R(dc, a->a), cpu_R(dc, a->b)); return true; } =20 static bool trans_l_sfles(DisasContext *dc, arg_ab *a) { - tcg_gen_setcond_tl(TCG_COND_LE, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); + tcg_gen_setcond_tl(TCG_COND_LE, + cpu_sr_f, cpu_R(dc, a->a), cpu_R(dc, a->b)); return true; } =20 static bool trans_l_sfeqi(DisasContext *dc, arg_ai *a) { - tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_sr_f, cpu_R[a->a], a->i); + tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_sr_f, cpu_R(dc, a->a), a->i); return true; } =20 static bool trans_l_sfnei(DisasContext *dc, arg_ai *a) { - tcg_gen_setcondi_tl(TCG_COND_NE, cpu_sr_f, cpu_R[a->a], a->i); + tcg_gen_setcondi_tl(TCG_COND_NE, cpu_sr_f, cpu_R(dc, a->a), a->i); return true; } =20 static bool trans_l_sfgtui(DisasContext *dc, arg_ai *a) { - tcg_gen_setcondi_tl(TCG_COND_GTU, cpu_sr_f, cpu_R[a->a], a->i); + tcg_gen_setcondi_tl(TCG_COND_GTU, cpu_sr_f, cpu_R(dc, a->a), a->i); return true; } =20 static bool trans_l_sfgeui(DisasContext *dc, arg_ai *a) { - tcg_gen_setcondi_tl(TCG_COND_GEU, cpu_sr_f, cpu_R[a->a], a->i); + tcg_gen_setcondi_tl(TCG_COND_GEU, cpu_sr_f, cpu_R(dc, a->a), a->i); return true; } =20 static bool trans_l_sfltui(DisasContext *dc, arg_ai *a) { - tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_sr_f, cpu_R[a->a], a->i); + tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_sr_f, cpu_R(dc, a->a), a->i); return true; } =20 static bool trans_l_sfleui(DisasContext *dc, arg_ai *a) { - tcg_gen_setcondi_tl(TCG_COND_LEU, cpu_sr_f, cpu_R[a->a], a->i); + tcg_gen_setcondi_tl(TCG_COND_LEU, cpu_sr_f, cpu_R(dc, a->a), a->i); return true; } =20 static bool trans_l_sfgtsi(DisasContext *dc, arg_ai *a) { - tcg_gen_setcondi_tl(TCG_COND_GT, cpu_sr_f, cpu_R[a->a], a->i); + tcg_gen_setcondi_tl(TCG_COND_GT, cpu_sr_f, cpu_R(dc, a->a), a->i); return true; } =20 static bool trans_l_sfgesi(DisasContext *dc, arg_ai *a) { - tcg_gen_setcondi_tl(TCG_COND_GE, cpu_sr_f, cpu_R[a->a], a->i); + tcg_gen_setcondi_tl(TCG_COND_GE, cpu_sr_f, cpu_R(dc, a->a), a->i); return true; } =20 static bool trans_l_sfltsi(DisasContext *dc, arg_ai *a) { - tcg_gen_setcondi_tl(TCG_COND_LT, cpu_sr_f, cpu_R[a->a], a->i); + tcg_gen_setcondi_tl(TCG_COND_LT, cpu_sr_f, cpu_R(dc, a->a), a->i); return true; } =20 static bool trans_l_sflesi(DisasContext *dc, arg_ai *a) { - tcg_gen_setcondi_tl(TCG_COND_LE, cpu_sr_f, cpu_R[a->a], a->i); + tcg_gen_setcondi_tl(TCG_COND_LE, cpu_sr_f, cpu_R(dc, a->a), a->i); return true; } =20 @@ -1137,7 +1156,7 @@ static void do_fp2(DisasContext *dc, arg_da *a, void (*fn)(TCGv, TCGv_env, TCGv)) { check_r0_write(dc, a->d); - fn(cpu_R[a->d], cpu_env, cpu_R[a->a]); + fn(cpu_R(dc, a->d), cpu_env, cpu_R(dc, a->a)); gen_helper_update_fpcsr(cpu_env); } =20 @@ -1145,7 +1164,7 @@ static void do_fp3(DisasContext *dc, arg_dab *a, void (*fn)(TCGv, TCGv_env, TCGv, TCGv)) { check_r0_write(dc, a->d); - fn(cpu_R[a->d], cpu_env, cpu_R[a->a], cpu_R[a->b]); + fn(cpu_R(dc, a->d), cpu_env, cpu_R(dc, a->a), cpu_R(dc, a->b)); gen_helper_update_fpcsr(cpu_env); } =20 @@ -1154,9 +1173,9 @@ static void do_fpcmp(DisasContext *dc, arg_ab *a, bool inv, bool swap) { if (swap) { - fn(cpu_sr_f, cpu_env, cpu_R[a->b], cpu_R[a->a]); + fn(cpu_sr_f, cpu_env, cpu_R(dc, a->b), cpu_R(dc, a->a)); } else { - fn(cpu_sr_f, cpu_env, cpu_R[a->a], cpu_R[a->b]); + fn(cpu_sr_f, cpu_env, cpu_R(dc, a->a), cpu_R(dc, a->b)); } if (inv) { tcg_gen_xori_tl(cpu_sr_f, cpu_sr_f, 1); @@ -1209,8 +1228,8 @@ static bool trans_lf_ftoi_s(DisasContext *dc, arg_da = *a) static bool trans_lf_madd_s(DisasContext *dc, arg_dab *a) { check_r0_write(dc, a->d); - gen_helper_float_madd_s(cpu_R[a->d], cpu_env, cpu_R[a->d], - cpu_R[a->a], cpu_R[a->b]); + gen_helper_float_madd_s(cpu_R(dc, a->d), cpu_env, cpu_R(dc, a->d), + cpu_R(dc, a->a), cpu_R(dc, a->b)); gen_helper_update_fpcsr(cpu_env); return true; } @@ -1273,9 +1292,9 @@ static void openrisc_tr_tb_start(DisasContextBase *db= , CPUState *cs) /* Allow the TCG optimizer to see that R0 =3D=3D 0, when it's true, which is the common case. */ if (dc->tb_flags & TB_FLAGS_R0_0) { - cpu_R[0] =3D tcg_const_tl(0); + cpu_regs[0] =3D tcg_const_tl(0); } else { - cpu_R[0] =3D cpu_R0; + cpu_regs[0] =3D cpu_R0; } } =20 --=20 2.17.1 From nobody Mon May 6 11:48:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567633008; cv=none; d=zoho.com; s=zohoarc; b=LyHiMny6VAOBqItcDg2PBLsMjt13zx84fpazGPPCHSsulcgQfIzciRU4oujElg8rC8u0HkzhjCMQlBZRlXXUZFy7diew7MiSbPp/OBVa52XXZbW0v2ayzkTih24Gr3gExVSbeSIXe2AmhzhBW6zEF/pSOTwOuj9f8Cj35dtnN0U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567633008; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id n66sm8104610pfn.90.2019.09.04.13.45.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 13:45:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=l5xF9L8hbrVx8UtpucRjuAJTrSqlDemzuCm3zQWWOUA=; b=JW+pzhK42qd7ZaM/De0bYUfVsqrtMjydtLu+17e6vIm9sCVJ67WhqV6xjeWbHBJfru oAfF+N9qgd07TYsTJYos9VWhofoiK3sTV6/acDN/DqEz4gTS2m0tVzkrG15c3x1uj5ca uKjQYvJE8EvzOVo4LOc8ZhNxTBUOy+FhI5hhrLhSfajeeFNqQQ5iTu4k5PrBwrhCwPtF zTV/uF0Z6+3yx963+O+TDNvVEM79qOVOnP+VnHyQ+U4Q7F0ULcSZb52BQ1MlORv0cYuQ 6syqOTTV7MeXyURbkSbrbquDxT8wpKZIZ/pY/uCOF6Ftr9Tn3p6rsHTC+tggIZssccmg Mclg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=l5xF9L8hbrVx8UtpucRjuAJTrSqlDemzuCm3zQWWOUA=; b=JOwZlD3M3qob65ojoq3cFS2TrH51fiu23PuC1Ya74gvNNnp79wtOL+XZK7yFIPzSjp NcbTwsi4/aRS+61U5bUuSHa0aThcs9nrxJwQoJUaaiSQyKAQ3shoQG11Qo1l+4K8DZ0u GSg/u6RmJmdWVFy6o+GkoK7fA6NDMIloZIdEMPNahE/xuj/nqmy4gaScpi/9wDnCUu77 po3qCiqKVVl2bU/uv69HICF8EYmAr3vYNNmZQrgImqvw41AUn2uLqPPLuP6kyJ6HMxcr lCpna9s+tG3RFJCrcRx6X0oXUblVl56+YmFzFz/qaWMYpATa6OUSHqJ7S+fN4JktySsU ysGA== X-Gm-Message-State: APjAAAX6KD7rgIYfNBYdYIuEazsc16Ky5UeVWmyuFiqXgl2dP6M5/Clr nnMqZadu7JlnM2Y2XmJdjm/I+RNVGUY= X-Google-Smtp-Source: APXvYqxa2ffNY0VInWY4UjXYWJpvSMMlCir5V6CJhZV2ypydJqhz+dyVTkK8gpzuDt+1+kW7zg+Swg== X-Received: by 2002:a63:484d:: with SMTP id x13mr71294pgk.122.1567629913011; Wed, 04 Sep 2019 13:45:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 13:44:57 -0700 Message-Id: <20190904204507.32457-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904204507.32457-1-richard.henderson@linaro.org> References: <20190904204507.32457-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::42a Subject: [Qemu-devel] [PULL 03/13] target/openrisc: Cache R0 in DisasContext X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Finish the race condition fix from the previous patch. Reviewed-by: Stafford Horne Signed-off-by: Richard Henderson --- target/openrisc/translate.c | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index d635a46f7e..341f923864 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -48,6 +48,9 @@ typedef struct DisasContext { =20 /* If not -1, jmp_pc contains this value and so is a direct jump. */ target_ulong jmp_pc_imm; + + /* The temporary corresponding to register 0 for this compilation. */ + TCGv R0; } DisasContext; =20 static inline bool is_user(DisasContext *dc) @@ -64,7 +67,6 @@ static inline bool is_user(DisasContext *dc) =20 static TCGv cpu_sr; static TCGv cpu_regs[32]; -static TCGv cpu_R0; static TCGv cpu_pc; static TCGv jmp_pc; /* l.jr/l.jalr temp pc */ static TCGv cpu_ppc; @@ -122,7 +124,6 @@ void openrisc_translate_init(void) shadow_gpr[0][i]), regnames[i]); } - cpu_R0 =3D cpu_regs[0]; } =20 static void gen_exception(DisasContext *dc, unsigned int excp) @@ -165,7 +166,11 @@ static void check_ov64s(DisasContext *dc) =20 static TCGv cpu_R(DisasContext *dc, int reg) { - return cpu_regs[reg]; + if (reg =3D=3D 0) { + return dc->R0; + } else { + return cpu_regs[reg]; + } } =20 /* @@ -175,7 +180,7 @@ static TCGv cpu_R(DisasContext *dc, int reg) static void check_r0_write(DisasContext *dc, int reg) { if (unlikely(reg =3D=3D 0)) { - cpu_regs[0] =3D cpu_R0; + dc->R0 =3D cpu_regs[0]; } } =20 @@ -747,7 +752,7 @@ static bool trans_l_swa(DisasContext *dc, arg_store *a) to cpu_regs[0]. Since l.swa is quite often immediately followed by= a branch, don't bother reallocating; finish the TB using the "real" R= 0. This also takes care of RB input across the branch. */ - cpu_regs[0] =3D cpu_R0; + dc->R0 =3D cpu_regs[0]; =20 lab_fail =3D gen_new_label(); lab_done =3D gen_new_label(); @@ -1292,9 +1297,9 @@ static void openrisc_tr_tb_start(DisasContextBase *db= , CPUState *cs) /* Allow the TCG optimizer to see that R0 =3D=3D 0, when it's true, which is the common case. */ if (dc->tb_flags & TB_FLAGS_R0_0) { - cpu_regs[0] =3D tcg_const_tl(0); + dc->R0 =3D tcg_const_tl(0); } else { - cpu_regs[0] =3D cpu_R0; + dc->R0 =3D cpu_regs[0]; } } =20 --=20 2.17.1 From nobody Mon May 6 11:48:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567631702; cv=none; d=zoho.com; s=zohoarc; b=h0jK6WEaHfQX0zfBp5P0KllQpK8w8MPYFkeWS1GLBe4uqk3I54iOlcbZ1y59C7CYixXcQ36/rN470QTZhhT2lO/FmpsFrh9FgZPWiwXfmUiCj4Ca3oa6eVkcFY9zEm6YsAXaMQzyGWbnSmz7GBaxMYgp8rvpNccaEwWmSMTj/Og= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567631702; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=NUB/rqkFfUKu2v7QerAjMtUtZI3FXJ/o9W4GMo7Gy60=; b=aVqnhV0rJcMUQ9xUXFBWpVKbZTKCPNZJ6JNXWbaUj5k2ZcXfWzNhPqgoms+S6urs6+3Atem70Ml2dODqY/bSK4bxcG6wWG+O727vhoiPETnRisMgLTv1RHtP9j83ruOVaMewhwaGEH2GS2hLwbinrCP9jg+j7BIrloog8I1VvgM= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 156763170256184.87362030939835; Wed, 4 Sep 2019 14:15:02 -0700 (PDT) Received: from localhost ([::1]:39976 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5ccG-0004O2-BP for importer@patchew.org; Wed, 04 Sep 2019 17:15:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52808) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5c9V-00065W-Ov for qemu-devel@nongnu.org; Wed, 04 Sep 2019 16:45:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5c9U-0006ix-6T for qemu-devel@nongnu.org; Wed, 04 Sep 2019 16:45:17 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]:41274) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i5c9T-0006i9-Si for qemu-devel@nongnu.org; Wed, 04 Sep 2019 16:45:16 -0400 Received: by mail-pl1-x633.google.com with SMTP id m9so89326pls.8 for ; Wed, 04 Sep 2019 13:45:15 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id n66sm8104610pfn.90.2019.09.04.13.45.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 13:45:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=NUB/rqkFfUKu2v7QerAjMtUtZI3FXJ/o9W4GMo7Gy60=; b=rJ71HQIaqEkUSz+KMQTIDAlS5TDNBjaTyZSB+VAlpy6Zv5f4wCKn4afr6ClPGN/X98 W/vLXrqavlnupmZaz6G7zNdCUx1ts/J54iqRSBbRSqqqeLnbYgFVSrmrrfQ/nLBbXsPf vgAOo/L6FB/7QcQEaNGWssDg67zAfSKvXnL0FIXLu2WcpkDWFWzIAeuLVGNaQM8RZu/R K7hye+ej+wRFHkZpAWEh2Vd/VhyO1vqmCRcQNcAllLzkgN8GUp8ryCM8TmS565F6V47I UsOUVlVQnUmV4pEc4zC/vJC3rN/LUvVEJg8cg9ygGw+VV2Jt2kS+VT8p7OHlPRUY1otK hNSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=NUB/rqkFfUKu2v7QerAjMtUtZI3FXJ/o9W4GMo7Gy60=; b=uoDkX4Of/MVKvbqNCFbNV1cFvLH5ykQ3p34LLcg4TlQji+zvKiBFDju0tB4XYkIbdH +kh9Bu1ZUW4db/k9eIgPhKHfyEiMBD4Vbvg9bX3EbusqWjhDTw764+B6vKM/0v6fuzui ASGxFXslQ/nKQJY4GLuELNfMf8K1+g5vzNK+9CChTaPSDrP1jT3Z4QyD1kf0KAUAUSqn 5UrgSwBurGkCk2x6bXcRQkV7y4BWPndYttsb9hlHNz1OhcrkRaNjwJ5PabBNqw7Klz5n TnEpcLHwy2PiRSQ1ZeyMDtq02nCzUr4g0m0vW84ikbe1KQiuqENN0iGfUCjeAp2xxNRS fTZA== X-Gm-Message-State: APjAAAX6oDTC2+fdg2PIxNLq4Zb2Bm8AlJW7/2pLuYAGDbypICXFK5Kv xbrVUxXdfDbM+Qy4MdqeT11t4NXQUu4= X-Google-Smtp-Source: APXvYqxwESrnler3/xq6dF7Eag8X9MvmJxWRbEN6Uwe25yJSt8pElJ79FUbcpwERgizPMnVzsAX6hQ== X-Received: by 2002:a17:902:a415:: with SMTP id p21mr18702282plq.319.1567629914328; Wed, 04 Sep 2019 13:45:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 13:44:58 -0700 Message-Id: <20190904204507.32457-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904204507.32457-1-richard.henderson@linaro.org> References: <20190904204507.32457-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::633 Subject: [Qemu-devel] [PULL 04/13] target/openrisc: Make VR and PPC read-only X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" These SPRs are read-only. The writes can simply be ignored, as we already do for other read-only (or missing) registers. There is no reason to mask the value in env->vr. Reviewed-by: Stafford Horne Signed-off-by: Richard Henderson --- target/openrisc/cpu.h | 3 --- target/openrisc/sys_helper.c | 10 +--------- 2 files changed, 1 insertion(+), 12 deletions(-) diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 561f0f7fad..755282f95d 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -68,9 +68,6 @@ enum { (reg) |=3D ((v & 0x1f) << 2);\ } while (0) =20 -/* Version Register */ -#define SPR_VR 0xFFFF003F - /* Interrupt */ #define NR_IRQS 32 =20 diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 1053409a04..d20f48b659 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -39,10 +39,6 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong s= pr, target_ulong rb) int idx; =20 switch (spr) { - case TO_SPR(0, 0): /* VR */ - env->vr =3D rb; - break; - case TO_SPR(0, 11): /* EVBAR */ env->evbar =3D rb; break; @@ -62,10 +58,6 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong s= pr, target_ulong rb) cpu_set_sr(env, rb); break; =20 - case TO_SPR(0, 18): /* PPC */ - env->ppc =3D rb; - break; - case TO_SPR(0, 32): /* EPCR */ env->epcr =3D rb; break; @@ -204,7 +196,7 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, targe= t_ulong rd, =20 switch (spr) { case TO_SPR(0, 0): /* VR */ - return env->vr & SPR_VR; + return env->vr; =20 case TO_SPR(0, 1): /* UPR */ return env->upr; /* TT, DM, IM, UP present */ --=20 2.17.1 From nobody Mon May 6 11:48:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567632772; cv=none; d=zoho.com; s=zohoarc; b=grS8aejFG9Ia0ri7uohjychhkGnezGOlgXwRWtbnRrBfKOs1UmgkyvEMBPPYpH+MIgwtSanjn4pYR/x8rUs5Yg99k6jRL07ou3LvBjPblc8hofEBfMamlICG8gMe34iEiqB0ayKPeyhwn/c3aF8M9ORON4dS2Nev4RLZsMqyORo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567632772; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=X84RCb73PaG8DYKiAA5H6xWmANPHPCwHIMuwva50q5I=; b=HS3Q5bh8KcVMi1vEt/sZEapzUvrt3ZLMsoAsYbB6FMs8tAAfJR3x2lem3UegHUUg7fsNe0DYjbngwmv+hqqfVck3XIxL5xPBDK07haeOgWUtL9gRJ1NPP+DO9BXdtgwPWPyPcnlHZV/5X2g+7Sm6+YFMTJwQS5MUPOg/oSKT7UM= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567632772092194.77321911281228; Wed, 4 Sep 2019 14:32:52 -0700 (PDT) Received: from localhost ([::1]:40244 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5ctW-0006j3-Cw for importer@patchew.org; Wed, 04 Sep 2019 17:32:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52826) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5c9X-00068U-7C for qemu-devel@nongnu.org; Wed, 04 Sep 2019 16:45:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5c9V-0006kY-Cr for qemu-devel@nongnu.org; Wed, 04 Sep 2019 16:45:18 -0400 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]:43598) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i5c9V-0006jK-1W for qemu-devel@nongnu.org; Wed, 04 Sep 2019 16:45:17 -0400 Received: by mail-pf1-x436.google.com with SMTP id d15so20792pfo.10 for ; Wed, 04 Sep 2019 13:45:16 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id n66sm8104610pfn.90.2019.09.04.13.45.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 13:45:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=X84RCb73PaG8DYKiAA5H6xWmANPHPCwHIMuwva50q5I=; b=pNzuBxGZqrLq9bInFa6+M5/RLw6wnLbVE0xKvLdxGmzWOqhkYmjaTSw5G4vHuj5HhH yNyT3qJPb6yyZeH3+VcTZOtCacIkIsThtGNnsHNjv9z+WodiyXY5khA3bKtRdhCvbyzl 9HL+hKEhGq1VapTU7t2e9ToOlpFDsjlNGYMvOIfTCtDCnRnHRKasdHw56ySu8nnOCaAG 7dNXDPYJYlQ/i4oTmmmB0GvaNvVPu0NG50z+Ykv0yBivpQGiED9RS3/ES8KQMfq54hbh MnL2S8gauIGw2U7F9cR06+HcvTZkmQID8onsJ/bzzgVO6ZWHdfX6MGCze+8gvegLKHty plxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=X84RCb73PaG8DYKiAA5H6xWmANPHPCwHIMuwva50q5I=; b=b9o2lNg4iZiv9f00kr/kcUimAIztl2cKkLvDFohpEKPIQmwwK/ObtmGwSmYvRoD+mA smZFvx34jmFqoyVH3zBHJEijWgGD5P1PXDO0LeO3qBWl/R6EKifRZHiVx9oK5gQ7/fsj 7lVgXzna96SgJtt2U7xid9eEBXWZQM0VpYPF4TfG+63ACCqMkXftcgAfVBo/B1P7DNKP TJUhz8TjoCStA93amSUIk5qt6PkaWP7LL2+RnILF6e1TMt1hBcYEQM7PlA2bzGKoS9Sg zkAhOpjBt2EqJjwB4HzXCs05XwodjXudAzSqEQLIseyeHph1UqyDUwcu5Id2lIqSSH1g zCrg== X-Gm-Message-State: APjAAAWMhg35OOaFFEh34PomPqvySGKYHEuqWEH/2sKLxc9mbYCzbNI8 b5ItG02AHmxtUCee1XnZNyLS+3VMygw= X-Google-Smtp-Source: APXvYqz2BLlXUHLeKO2V3Etx6n7EpxOH5+nrlzfVb8a+qaZohPfdEYcbi/de2gd2//VTYDPzM0oDPg== X-Received: by 2002:a63:6c46:: with SMTP id h67mr67660pgc.248.1567629915524; Wed, 04 Sep 2019 13:45:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 13:44:59 -0700 Message-Id: <20190904204507.32457-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904204507.32457-1-richard.henderson@linaro.org> References: <20190904204507.32457-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::436 Subject: [Qemu-devel] [PULL 05/13] target/openrisc: Move VR, UPR, DMMCFGR, IMMCFGR to cpu init X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" These registers are read-only and implementation specific. Initiailize VR for the first time; take the OR1200 values from the verilog source. Note that moving fields within CPUOpenRISCState does not affect migration. Reviewed-by: Stafford Horne Signed-off-by: Richard Henderson --- target/openrisc/cpu.h | 8 ++++---- target/openrisc/cpu.c | 23 ++++++++++++++++------- target/openrisc/sys_helper.c | 4 ++-- 3 files changed, 22 insertions(+), 13 deletions(-) diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 755282f95d..18d7445e74 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -260,10 +260,6 @@ typedef struct CPUOpenRISCState { target_ulong sr_cy; /* the SR_CY bit, values 0, 1. */ target_long sr_ov; /* the SR_OV bit (in the sign bit only) */ uint32_t sr; /* Supervisor register, without SR_{F,CY,OV}= */ - uint32_t vr; /* Version register */ - uint32_t upr; /* Unit presence register */ - uint32_t dmmucfgr; /* DMMU configure register */ - uint32_t immucfgr; /* IMMU configure register */ uint32_t esr; /* Exception supervisor register */ uint32_t evbar; /* Exception vector base address register */ uint32_t pmr; /* Power Management Register */ @@ -283,7 +279,11 @@ typedef struct CPUOpenRISCState { struct {} end_reset_fields; =20 /* Fields from here on are preserved across CPU reset. */ + uint32_t vr; /* Version register */ + uint32_t upr; /* Unit presence register */ uint32_t cpucfgr; /* CPU configure register */ + uint32_t dmmucfgr; /* DMMU configure register */ + uint32_t immucfgr; /* IMMU configure register */ =20 #ifndef CONFIG_USER_ONLY QEMUTimer *timer; diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index f19e482a55..d9f447e90c 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -56,13 +56,6 @@ static void openrisc_cpu_reset(CPUState *s) cpu->env.lock_addr =3D -1; s->exception_index =3D -1; =20 - cpu->env.upr =3D UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | - UPR_PMP; - cpu->env.dmmucfgr =3D (DMMUCFGR_NTW & (0 << 2)) - | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); - cpu->env.immucfgr =3D (IMMUCFGR_NTW & (0 << 2)) - | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); - #ifndef CONFIG_USER_ONLY cpu->env.picmr =3D 0x00000000; cpu->env.picsr =3D 0x00000000; @@ -117,15 +110,31 @@ static void or1200_initfn(Object *obj) { OpenRISCCPU *cpu =3D OPENRISC_CPU(obj); =20 + cpu->env.vr =3D 0x13000008; + cpu->env.upr =3D UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR= _PMP; cpu->env.cpucfgr =3D CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S | CPUCFGR_EVBARP; + + /* 1Way, TLB_SIZE entries. */ + cpu->env.dmmucfgr =3D (DMMUCFGR_NTW & (0 << 2)) + | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); + cpu->env.immucfgr =3D (IMMUCFGR_NTW & (0 << 2)) + | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); } =20 static void openrisc_any_initfn(Object *obj) { OpenRISCCPU *cpu =3D OPENRISC_CPU(obj); =20 + cpu->env.vr =3D 0x13000000; + cpu->env.upr =3D UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR= _PMP; cpu->env.cpucfgr =3D CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_EVBARP; + + /* 1Way, TLB_SIZE entries. */ + cpu->env.dmmucfgr =3D (DMMUCFGR_NTW & (0 << 2)) + | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); + cpu->env.immucfgr =3D (IMMUCFGR_NTW & (0 << 2)) + | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); } =20 static void openrisc_cpu_class_init(ObjectClass *oc, void *data) diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index d20f48b659..a2b1f52294 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -199,13 +199,13 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, tar= get_ulong rd, return env->vr; =20 case TO_SPR(0, 1): /* UPR */ - return env->upr; /* TT, DM, IM, UP present */ + return env->upr; =20 case TO_SPR(0, 2): /* CPUCFGR */ return env->cpucfgr; =20 case TO_SPR(0, 3): /* DMMUCFGR */ - return env->dmmucfgr; /* 1Way, 64 entries */ + return env->dmmucfgr; =20 case TO_SPR(0, 4): /* IMMUCFGR */ return env->immucfgr; --=20 2.17.1 From nobody Mon May 6 11:48:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567631966; cv=none; d=zoho.com; s=zohoarc; b=CkDwGpFLKP4ZaY7Z2guWKSczdio5FT7jYZ6UhIXOxOF69prQoLouipKysagdEtzF9kfxy2DCgWzYpXR/IbE04Qcqg9QVY58klklmkQKJqkS1A+qGvrXEJci1V0kOEgKiiyH5J0aeaXuOYP/oOe+64rjfimezJp5Tl2E0ApPshOU= ARC-Message-Signature: i=1; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id n66sm8104610pfn.90.2019.09.04.13.45.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 13:45:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ddiXQUCU6+mV9b5HLraEW0nl5fo+95ic0hgqPUZ1sNk=; b=MSddaqDmsvrs+IxiQ14B8VDMy7wNo0Vt2EYZJek1dggV55FDVT0x5GlL6VdgzTMJbF MZ6ITu1ZxAt5wF9NnqfKZpC6cXe4iABpMf06vO7spIL72gfM9Lc6mRq/0qL5rz7Zta8o uU/E/rUhTLzMwppzep0CN4Jr40qIEdDorlKLqkavJ17VNaBxRLyhEXDlQGvmDKc3Vcw3 ktnpyndyd+qQQ53KAKQZScG1vw2/ljECNAYMposijavMiD6+tdYUJ52B/bxkPVy8195T fgPqz5owYB9BVfwXfz7Dri6xE9W0MTkUMexTNelWBJOjUo8Gh078podmqKKDxF5PGfwp HvEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ddiXQUCU6+mV9b5HLraEW0nl5fo+95ic0hgqPUZ1sNk=; b=pj1aJHC05FpLTjxWuJVl0gt2t60+F516VfNwyPv1L79maAOPcGm893l0K+h8ZGwIIl etFkfO1qb6GB52a49Lk4uVgXGSLF6Pl/mw6T5sFiDjpLw/owAW4K6b0W7VSR21/gLciW 5F+Ve0L0QSdwWJJ6j1SzBbymcSqaTQMy8JGKGaaAYqAmYSKYJTqpggaW5o0NdlGq1DE5 GZFLIOZzcIpZ4IaTFr/TgOdEV2ig5LZl3rfMJdR3nNk5fEZ4dmefVxEAtkGHyQj7ApCU 7xBeMyExOAiA2/NN84IpPAW3hgda8/N6TJQFx1V/z9CsDiVJQPgC5uB6sQEkWFPXsQcJ 2WpQ== X-Gm-Message-State: APjAAAVxuVCRGAQHVLz2r1eIbjZ1uaASHYjg0mrfa2gCLW+ms5in0VtU SkVkG5UFp+JbWTQ4FEo7SLlh3SE1KUg= X-Google-Smtp-Source: APXvYqwkZjoiyyWMGTdG56oMaWgURYtLJW7ZrM7zvQcaTbXF+PbxrKS8lAM0gaOySDvqIJp7lpZ+pQ== X-Received: by 2002:a17:902:ab96:: with SMTP id f22mr43907220plr.147.1567629916793; Wed, 04 Sep 2019 13:45:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 13:45:00 -0700 Message-Id: <20190904204507.32457-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904204507.32457-1-richard.henderson@linaro.org> References: <20190904204507.32457-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::630 Subject: [Qemu-devel] [PULL 06/13] target/openrisc: Add VR2 and AVR special processor registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Update the CPUCFG bits to arch v1.3. Include support for AVRP for cpu "any". Signed-off-by: Richard Henderson --- target/openrisc/cpu.h | 11 +++++++---- target/openrisc/cpu.c | 8 ++++++-- target/openrisc/sys_helper.c | 6 ++++++ 3 files changed, 19 insertions(+), 6 deletions(-) diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 18d7445e74..71c5959828 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -96,11 +96,12 @@ enum { CPUCFGR_OF32S =3D (1 << 7), CPUCFGR_OF64S =3D (1 << 8), CPUCFGR_OV64S =3D (1 << 9), - /* CPUCFGR_ND =3D (1 << 10), */ - /* CPUCFGR_AVRP =3D (1 << 11), */ + CPUCFGR_ND =3D (1 << 10), + CPUCFGR_AVRP =3D (1 << 11), CPUCFGR_EVBARP =3D (1 << 12), - /* CPUCFGR_ISRP =3D (1 << 13), */ - /* CPUCFGR_AECSRP =3D (1 << 14), */ + CPUCFGR_ISRP =3D (1 << 13), + CPUCFGR_AECSRP =3D (1 << 14), + CPUCFGR_OF64A32S =3D (1 << 15), }; =20 /* DMMU configure register */ @@ -280,6 +281,8 @@ typedef struct CPUOpenRISCState { =20 /* Fields from here on are preserved across CPU reset. */ uint32_t vr; /* Version register */ + uint32_t vr2; /* Version register 2 */ + uint32_t avr; /* Architecture version register */ uint32_t upr; /* Unit presence register */ uint32_t cpucfgr; /* CPU configure register */ uint32_t dmmucfgr; /* DMMU configure register */ diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index d9f447e90c..9f566ad883 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -126,9 +126,13 @@ static void openrisc_any_initfn(Object *obj) { OpenRISCCPU *cpu =3D OPENRISC_CPU(obj); =20 - cpu->env.vr =3D 0x13000000; + cpu->env.vr =3D 0x13000040; /* Obsolete VER + UVRP for new SPRs */ + cpu->env.vr2 =3D 0; /* No version specific id */ + cpu->env.avr =3D 0x01010000; /* Architecture v1.1 */ + cpu->env.upr =3D UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR= _PMP; - cpu->env.cpucfgr =3D CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_EVBARP; + cpu->env.cpucfgr =3D CPUCFGR_NSGF | CPUCFGR_OB32S | + CPUCFGR_AVRP | CPUCFGR_EVBARP; =20 /* 1Way, TLB_SIZE entries. */ cpu->env.dmmucfgr =3D (DMMUCFGR_NTW & (0 << 2)) diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index a2b1f52294..cf8e637b08 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -210,6 +210,12 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, targ= et_ulong rd, case TO_SPR(0, 4): /* IMMUCFGR */ return env->immucfgr; =20 + case TO_SPR(0, 9): /* VR2 */ + return env->vr2; + + case TO_SPR(0, 10): /* AVR */ + return env->avr; + case TO_SPR(0, 11): /* EVBAR */ return env->evbar; =20 --=20 2.17.1 From nobody Mon May 6 11:48:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567632152; cv=none; d=zoho.com; s=zohoarc; b=jqX0vi5kOax5vB0a0qeFUXyf56wem8BOQtYNLi3P/cVebwSSCC6rCY1ylI37dETex53QjTrqkYSZbfgSY7kNMNtr1hZ9+9llKnrFon9lWg09nKtzr2wM/Yh9JERxSY65rwQqvunEFqrxvE2Iov8nIjbwdyu4ekmsFcieKeVvMBw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id n66sm8104610pfn.90.2019.09.04.13.45.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 13:45:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=DCUh3pxo77uhgP+ZJoHLASbE9LI4j7qaNhsFo5dJ8X8=; b=X2bi62r7E6W+ANGD6dXapnAAlHBs1N3/il/xLnEE7kwqaqLsgvdMHhI2V1TnDsM9ch Gaz9tPsxLcbwTnHCZ40PstdFNm7Xcer9TwuSq/UAaZmbLXOM+Y2wKxaULda82NniwX3J qKsVxJROJUlSrkl+Uca9oK/RPc5d4U/u9TyzA9rN/LEfMVoWRA3IIwG29DYGnRbcdtcd ZWnSlctUGaRdwj4vNgjEy2VnQL99SbYwBBbvotgGzbseMv/9ZvIvBbC6UvxEl9zdPOCq Rjh3RyW84hJ2Fc5Tr0Ylhs0wSdGOMFHZeAS9GalIvjXSMsi7Rbv9fz+3yQSUWegjROaq 9vHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=DCUh3pxo77uhgP+ZJoHLASbE9LI4j7qaNhsFo5dJ8X8=; b=ghMnbdi0RMyMqytOgqdXpAn162jqyj3tjU21KMajXIG3P/sX/Gz8WowsVCxyW3g5n6 CNObnsrOu7zX1qpAKSbs4Jy+3wiBWI+ypJijAv909BQMWFlcT5Scol12gAhpavbKMK9V TQg/ul5yvAUViur9t0OYY+zzaHxmA/hyYgc6YjcZ20dTvgjNIsBXEFbK4pDxi5lQkOq5 9RfdKF4PrkUg7VZ1Bp+DVO9lYWuBwp1Yc1nuXV7Rd46jKofxSnhcZYLyZcF/7lmhTlpG nHTe6VAFAsVfhaW5qI7lYz/JrmUok/seFYxEcXt9bKQAHznRJDXHs/+nxSWekzRDu9GL jsJg== X-Gm-Message-State: APjAAAX0ud7aSvVk4rw8Ou2Vmyy8uZZOFZyhe3Z5+lAK3vhD5xY4OrjV hPppApSW4jc15TCD2E1mKHi87eOqiRI= X-Google-Smtp-Source: APXvYqx5v94WzMwOFVmCtMSSiRpoGce2IzOWju5lW9w/pBOonHhRzFJ9SKEqlCDzxaIuqdxUHSVIlQ== X-Received: by 2002:a17:902:44c:: with SMTP id 70mr41774517ple.225.1567629917984; Wed, 04 Sep 2019 13:45:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 13:45:01 -0700 Message-Id: <20190904204507.32457-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904204507.32457-1-richard.henderson@linaro.org> References: <20190904204507.32457-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::633 Subject: [Qemu-devel] [PULL 07/13] target/openrisc: Fix lf.ftoi.s X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The specification of this insn is round-to-zero. Reviewed-by: Stafford Horne Signed-off-by: Richard Henderson --- target/openrisc/fpu_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/openrisc/fpu_helper.c b/target/openrisc/fpu_helper.c index b9d2ebbb8c..4cc5b297c5 100644 --- a/target/openrisc/fpu_helper.c +++ b/target/openrisc/fpu_helper.c @@ -78,7 +78,7 @@ uint64_t HELPER(ftoid)(CPUOpenRISCState *env, uint64_t va= l) =20 uint32_t HELPER(ftois)(CPUOpenRISCState *env, uint32_t val) { - return float32_to_int32(val, &env->fp_status); + return float32_to_int32_round_to_zero(val, &env->fp_status); } =20 #define FLOAT_CALC(name) \ --=20 2.17.1 From nobody Mon May 6 11:48:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567633182; cv=none; d=zoho.com; s=zohoarc; b=AqYzNb7Ajz+HtxrW54wCSoMvZvePKGYm8cs/+kLFB/dJwptRJgy31m/OKjjbfEaS25CKnru2YF0yGMA9JHmrit78VpA7yhBkXKkErz+DK2+p/AmETy+JPtmsLNN1OjSBAArE45OhqFltNWZPKzZEdyQZhsWu0tLiazxcqrF6a2U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567633182; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=2GGld3+nyB6RGdDPwst4M2bW/fcpfjsi762a3svN9NQ=; b=VaAU3vjRmuPPPEm4nn9DuTCisfPk8IyG8JFmkGslC4GAkO8MQS4HqPEOaLbuGqY33uDuYkMMu+xxYhOXoP4sSAIm8KsdnzcLOatZVC532fjQWqOjrln3gMrNKooQwD8wcj1Ucx5L7NX+hQa66LdSL9xaswcfqMqDIVt0o7pgz4c= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567633181987732.9421903922998; Wed, 4 Sep 2019 14:39:41 -0700 (PDT) Received: from localhost ([::1]:40360 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5d08-0006C0-7s for importer@patchew.org; Wed, 04 Sep 2019 17:39:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52869) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5c9a-0006Ec-Kr for qemu-devel@nongnu.org; Wed, 04 Sep 2019 16:45:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5c9Y-0006nK-RQ for qemu-devel@nongnu.org; Wed, 04 Sep 2019 16:45:22 -0400 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]:39602) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i5c9Y-0006m5-IX for qemu-devel@nongnu.org; Wed, 04 Sep 2019 16:45:20 -0400 Received: by mail-pl1-x62d.google.com with SMTP id bd8so95431plb.6 for ; Wed, 04 Sep 2019 13:45:20 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id n66sm8104610pfn.90.2019.09.04.13.45.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 13:45:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=2GGld3+nyB6RGdDPwst4M2bW/fcpfjsi762a3svN9NQ=; b=Z+SNo1wQyA7Jh9KTwQTDa0Yn97hxRYfVBnO2a2HeEa9+B0baYabNxPUDzs/hXdRL+h W9H7qrvdyOfy0fB+gRKIL92Gh3jk+X0SE7p/nxEhjZlNHjVhPJpw2kSm3em8LqGalscP hv/Nl7gisyCf+2TRufDdiKM7ly3f9srfFm2Qbv6xRPoWlyr+P9F6Z3mp9GuzVHJqPV8j QrAjtYRNzQWUreGTLBsTnONNdBRA6r659ohCjBLdFVJP6yp5Hy1X6gB8RWxetptBXjSC uZ2/CvAt2PPtuclOck0C+tz+3imOQC2MhPS9JsFEHYqBYxLa6/xvZTTv1Ur3cLQSFWrt G5Zg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=2GGld3+nyB6RGdDPwst4M2bW/fcpfjsi762a3svN9NQ=; b=pwAHwZMsmt3FUx+onxGxinB+o2BStTdBlqpLRlCH1Mn2aZZYDWEW2vJoqXcbhpykJc uLSk7dB+4p1tvEly/bYLGVmSaeHvzV4UlVlC/z/hycOc5rhguy9C53AJl+UZUjkoSh94 et2w/gf4Le14OnOAo6cHP1/415Va9WfhoY3PxY8/yeuaDlxE2fzQbpOmVl+geMI8ae+e IbPdhxU6EVfR36dfg5Dz1Zdo5HIz6fhadHMjPRjq7YCX7xX4E2z3ItDvwAtP4XJL/Ha0 5A1qtem7CXz4gqW0RD4swr9b5DRcm7WcdKzDIUccD+1VLCWGggqiabVeCfbwhR6wG34B GipQ== X-Gm-Message-State: APjAAAXgZ+2cExkBwI+0mW51lLu+UPtbVhu0zqC1IPJ9L7hDZdXx5WvM H9zOWJL+Jig5U++toE1OClyaiT3AFrs= X-Google-Smtp-Source: APXvYqyOfhts/Q6lFkYINDoNBbvgXEvqOv+hDoryAFpeQZoi1j8mp0qZD9wkZiWM6r7vTUM5Xevn2A== X-Received: by 2002:a17:902:9347:: with SMTP id g7mr7611218plp.0.1567629919179; Wed, 04 Sep 2019 13:45:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 13:45:02 -0700 Message-Id: <20190904204507.32457-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904204507.32457-1-richard.henderson@linaro.org> References: <20190904204507.32457-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::62d Subject: [Qemu-devel] [PULL 08/13] target/openrisc: Check CPUCFG_OF32S for float insns X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Make sure the OF32S insns are enabled before allowing execution. Include the missing bit for cpu "any". Reviewed-by: Stafford Horne Signed-off-by: Richard Henderson --- target/openrisc/cpu.c | 2 +- target/openrisc/translate.c | 84 ++++++++++++++++--------------------- 2 files changed, 36 insertions(+), 50 deletions(-) diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 9f566ad883..f3c8134531 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -131,7 +131,7 @@ static void openrisc_any_initfn(Object *obj) cpu->env.avr =3D 0x01010000; /* Architecture v1.1 */ =20 cpu->env.upr =3D UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR= _PMP; - cpu->env.cpucfgr =3D CPUCFGR_NSGF | CPUCFGR_OB32S | + cpu->env.cpucfgr =3D CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S | CPUCFGR_AVRP | CPUCFGR_EVBARP; =20 /* 1Way, TLB_SIZE entries. */ diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 341f923864..2f5c969f21 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -45,6 +45,7 @@ typedef struct DisasContext { uint32_t mem_idx; uint32_t tb_flags; uint32_t delayed_branch; + uint32_t cpucfgr; =20 /* If not -1, jmp_pc contains this value and so is a direct jump. */ target_ulong jmp_pc_imm; @@ -140,30 +141,11 @@ static void gen_illegal_exception(DisasContext *dc) dc->base.is_jmp =3D DISAS_NORETURN; } =20 -/* not used yet, open it when we need or64. */ -/*#ifdef TARGET_OPENRISC64 -static void check_ob64s(DisasContext *dc) +static bool check_of32s(DisasContext *dc) { - if (!(dc->flags & CPUCFGR_OB64S)) { - gen_illegal_exception(dc); - } + return dc->cpucfgr & CPUCFGR_OF32S; } =20 -static void check_of64s(DisasContext *dc) -{ - if (!(dc->flags & CPUCFGR_OF64S)) { - gen_illegal_exception(dc); - } -} - -static void check_ov64s(DisasContext *dc) -{ - if (!(dc->flags & CPUCFGR_OV64S)) { - gen_illegal_exception(dc); - } -} -#endif*/ - static TCGv cpu_R(DisasContext *dc, int reg) { if (reg =3D=3D 0) { @@ -1157,26 +1139,37 @@ static bool trans_l_rfe(DisasContext *dc, arg_l_rfe= *a) return true; } =20 -static void do_fp2(DisasContext *dc, arg_da *a, +static bool do_fp2(DisasContext *dc, arg_da *a, void (*fn)(TCGv, TCGv_env, TCGv)) { + if (!check_of32s(dc)) { + return false; + } check_r0_write(dc, a->d); fn(cpu_R(dc, a->d), cpu_env, cpu_R(dc, a->a)); gen_helper_update_fpcsr(cpu_env); + return true; } =20 -static void do_fp3(DisasContext *dc, arg_dab *a, +static bool do_fp3(DisasContext *dc, arg_dab *a, void (*fn)(TCGv, TCGv_env, TCGv, TCGv)) { + if (!check_of32s(dc)) { + return false; + } check_r0_write(dc, a->d); fn(cpu_R(dc, a->d), cpu_env, cpu_R(dc, a->a), cpu_R(dc, a->b)); gen_helper_update_fpcsr(cpu_env); + return true; } =20 -static void do_fpcmp(DisasContext *dc, arg_ab *a, +static bool do_fpcmp(DisasContext *dc, arg_ab *a, void (*fn)(TCGv, TCGv_env, TCGv, TCGv), bool inv, bool swap) { + if (!check_of32s(dc)) { + return false; + } if (swap) { fn(cpu_sr_f, cpu_env, cpu_R(dc, a->b), cpu_R(dc, a->a)); } else { @@ -1186,52 +1179,50 @@ static void do_fpcmp(DisasContext *dc, arg_ab *a, tcg_gen_xori_tl(cpu_sr_f, cpu_sr_f, 1); } gen_helper_update_fpcsr(cpu_env); + return true; } =20 static bool trans_lf_add_s(DisasContext *dc, arg_dab *a) { - do_fp3(dc, a, gen_helper_float_add_s); - return true; + return do_fp3(dc, a, gen_helper_float_add_s); } =20 static bool trans_lf_sub_s(DisasContext *dc, arg_dab *a) { - do_fp3(dc, a, gen_helper_float_sub_s); - return true; + return do_fp3(dc, a, gen_helper_float_sub_s); } =20 static bool trans_lf_mul_s(DisasContext *dc, arg_dab *a) { - do_fp3(dc, a, gen_helper_float_mul_s); - return true; + return do_fp3(dc, a, gen_helper_float_mul_s); } =20 static bool trans_lf_div_s(DisasContext *dc, arg_dab *a) { - do_fp3(dc, a, gen_helper_float_div_s); - return true; + return do_fp3(dc, a, gen_helper_float_div_s); } =20 static bool trans_lf_rem_s(DisasContext *dc, arg_dab *a) { - do_fp3(dc, a, gen_helper_float_rem_s); + return do_fp3(dc, a, gen_helper_float_rem_s); return true; } =20 static bool trans_lf_itof_s(DisasContext *dc, arg_da *a) { - do_fp2(dc, a, gen_helper_itofs); - return true; + return do_fp2(dc, a, gen_helper_itofs); } =20 static bool trans_lf_ftoi_s(DisasContext *dc, arg_da *a) { - do_fp2(dc, a, gen_helper_ftois); - return true; + return do_fp2(dc, a, gen_helper_ftois); } =20 static bool trans_lf_madd_s(DisasContext *dc, arg_dab *a) { + if (!check_of32s(dc)) { + return false; + } check_r0_write(dc, a->d); gen_helper_float_madd_s(cpu_R(dc, a->d), cpu_env, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); @@ -1241,38 +1232,32 @@ static bool trans_lf_madd_s(DisasContext *dc, arg_d= ab *a) =20 static bool trans_lf_sfeq_s(DisasContext *dc, arg_ab *a) { - do_fpcmp(dc, a, gen_helper_float_eq_s, false, false); - return true; + return do_fpcmp(dc, a, gen_helper_float_eq_s, false, false); } =20 static bool trans_lf_sfne_s(DisasContext *dc, arg_ab *a) { - do_fpcmp(dc, a, gen_helper_float_eq_s, true, false); - return true; + return do_fpcmp(dc, a, gen_helper_float_eq_s, true, false); } =20 static bool trans_lf_sfgt_s(DisasContext *dc, arg_ab *a) { - do_fpcmp(dc, a, gen_helper_float_lt_s, false, true); - return true; + return do_fpcmp(dc, a, gen_helper_float_lt_s, false, true); } =20 static bool trans_lf_sfge_s(DisasContext *dc, arg_ab *a) { - do_fpcmp(dc, a, gen_helper_float_le_s, false, true); - return true; + return do_fpcmp(dc, a, gen_helper_float_le_s, false, true); } =20 static bool trans_lf_sflt_s(DisasContext *dc, arg_ab *a) { - do_fpcmp(dc, a, gen_helper_float_lt_s, false, false); - return true; + return do_fpcmp(dc, a, gen_helper_float_lt_s, false, false); } =20 static bool trans_lf_sfle_s(DisasContext *dc, arg_ab *a) { - do_fpcmp(dc, a, gen_helper_float_le_s, false, false); - return true; + return do_fpcmp(dc, a, gen_helper_float_le_s, false, false); } =20 static void openrisc_tr_init_disas_context(DisasContextBase *dcb, CPUState= *cs) @@ -1284,6 +1269,7 @@ static void openrisc_tr_init_disas_context(DisasConte= xtBase *dcb, CPUState *cs) dc->mem_idx =3D cpu_mmu_index(env, false); dc->tb_flags =3D dc->base.tb->flags; dc->delayed_branch =3D (dc->tb_flags & TB_FLAGS_DFLAG) !=3D 0; + dc->cpucfgr =3D env->cpucfgr; dc->jmp_pc_imm =3D -1; =20 bound =3D -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; --=20 2.17.1 From nobody Mon May 6 11:48:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::635 Subject: [Qemu-devel] [PULL 09/13] target/openrisc: Add support for ORFPX64A32 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is hardware support for double-precision floating-point using pairs of 32-bit registers. Fix latent bugs in the heretofore unused helper_itofd and helper_ftoid. Include the bit for cpu "any". Change the default cpu for linux-user to "any". Reviewed-by: Stafford Horne Signed-off-by: Richard Henderson --- linux-user/openrisc/target_elf.h | 2 +- target/openrisc/helper.h | 2 + target/openrisc/cpu.c | 2 +- target/openrisc/disas.c | 56 ++++++++ target/openrisc/fpu_helper.c | 14 +- target/openrisc/translate.c | 230 +++++++++++++++++++++++++++++++ target/openrisc/insns.decode | 31 +++++ 7 files changed, 333 insertions(+), 4 deletions(-) diff --git a/linux-user/openrisc/target_elf.h b/linux-user/openrisc/target_= elf.h index 40ceb025c9..265ecd3079 100644 --- a/linux-user/openrisc/target_elf.h +++ b/linux-user/openrisc/target_elf.h @@ -9,6 +9,6 @@ #define OPENRISC_TARGET_ELF_H static inline const char *cpu_get_model(uint32_t eflags) { - return "or1200"; + return "any"; } #endif diff --git a/target/openrisc/helper.h b/target/openrisc/helper.h index 96d79a8113..94b823580e 100644 --- a/target/openrisc/helper.h +++ b/target/openrisc/helper.h @@ -30,6 +30,8 @@ DEF_HELPER_FLAGS_2(itofd, TCG_CALL_NO_RWG, i64, env, i64) DEF_HELPER_FLAGS_2(itofs, TCG_CALL_NO_RWG, i32, env, i32) DEF_HELPER_FLAGS_2(ftoid, TCG_CALL_NO_RWG, i64, env, i64) DEF_HELPER_FLAGS_2(ftois, TCG_CALL_NO_RWG, i32, env, i32) +DEF_HELPER_FLAGS_2(stod, TCG_CALL_NO_RWG, i64, env, i32) +DEF_HELPER_FLAGS_2(dtos, TCG_CALL_NO_RWG, i32, env, i64) =20 DEF_HELPER_FLAGS_4(float_madd_s, TCG_CALL_NO_RWG, i32, env, i32, i32, i32) DEF_HELPER_FLAGS_4(float_madd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index f3c8134531..b931605e62 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -132,7 +132,7 @@ static void openrisc_any_initfn(Object *obj) =20 cpu->env.upr =3D UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR= _PMP; cpu->env.cpucfgr =3D CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S | - CPUCFGR_AVRP | CPUCFGR_EVBARP; + CPUCFGR_AVRP | CPUCFGR_EVBARP | CPUCFGR_OF64A32S; =20 /* 1Way, TLB_SIZE entries. */ cpu->env.dmmucfgr =3D (DMMUCFGR_NTW & (0 << 2)) diff --git a/target/openrisc/disas.c b/target/openrisc/disas.c index 7091832347..4de5c632de 100644 --- a/target/openrisc/disas.c +++ b/target/openrisc/disas.c @@ -166,3 +166,59 @@ FP_INSN(sfgt, s, "r%d, r%d", a->a, a->b) FP_INSN(sfge, s, "r%d, r%d", a->a, a->b) FP_INSN(sflt, s, "r%d, r%d", a->a, a->b) FP_INSN(sfle, s, "r%d, r%d", a->a, a->b) + +FP_INSN(add, d, "r%d,r%d, r%d,r%d, r%d,r%d", + a->d, a->d + a->dp + 1, + a->a, a->a + a->ap + 1, + a->b, a->b + a->bp + 1) +FP_INSN(sub, d, "r%d,r%d, r%d,r%d, r%d,r%d", + a->d, a->d + a->dp + 1, + a->a, a->a + a->ap + 1, + a->b, a->b + a->bp + 1) +FP_INSN(mul, d, "r%d,r%d, r%d,r%d, r%d,r%d", + a->d, a->d + a->dp + 1, + a->a, a->a + a->ap + 1, + a->b, a->b + a->bp + 1) +FP_INSN(div, d, "r%d,r%d, r%d,r%d, r%d,r%d", + a->d, a->d + a->dp + 1, + a->a, a->a + a->ap + 1, + a->b, a->b + a->bp + 1) +FP_INSN(rem, d, "r%d,r%d, r%d,r%d, r%d,r%d", + a->d, a->d + a->dp + 1, + a->a, a->a + a->ap + 1, + a->b, a->b + a->bp + 1) +FP_INSN(madd, d, "r%d,r%d, r%d,r%d, r%d,r%d", + a->d, a->d + a->dp + 1, + a->a, a->a + a->ap + 1, + a->b, a->b + a->bp + 1) + +FP_INSN(itof, d, "r%d,r%d, r%d,r%d", + a->d, a->d + a->dp + 1, + a->a, a->a + a->ap + 1) +FP_INSN(ftoi, d, "r%d,r%d, r%d,r%d", + a->d, a->d + a->dp + 1, + a->a, a->a + a->ap + 1) + +FP_INSN(stod, d, "r%d,r%d, r%d", + a->d, a->d + a->dp + 1, a->a) +FP_INSN(dtos, d, "r%d r%d,r%d", + a->d, a->a, a->a + a->ap + 1) + +FP_INSN(sfeq, d, "r%d,r%d, r%d,r%d", + a->a, a->a + a->ap + 1, + a->b, a->b + a->bp + 1) +FP_INSN(sfne, d, "r%d,r%d, r%d,r%d", + a->a, a->a + a->ap + 1, + a->b, a->b + a->bp + 1) +FP_INSN(sfgt, d, "r%d,r%d, r%d,r%d", + a->a, a->a + a->ap + 1, + a->b, a->b + a->bp + 1) +FP_INSN(sfge, d, "r%d,r%d, r%d,r%d", + a->a, a->a + a->ap + 1, + a->b, a->b + a->bp + 1) +FP_INSN(sflt, d, "r%d,r%d, r%d,r%d", + a->a, a->a + a->ap + 1, + a->b, a->b + a->bp + 1) +FP_INSN(sfle, d, "r%d,r%d, r%d,r%d", + a->a, a->a + a->ap + 1, + a->b, a->b + a->bp + 1) diff --git a/target/openrisc/fpu_helper.c b/target/openrisc/fpu_helper.c index 4cc5b297c5..9d7dfc0fb9 100644 --- a/target/openrisc/fpu_helper.c +++ b/target/openrisc/fpu_helper.c @@ -63,7 +63,7 @@ void HELPER(update_fpcsr)(CPUOpenRISCState *env) =20 uint64_t HELPER(itofd)(CPUOpenRISCState *env, uint64_t val) { - return int32_to_float64(val, &env->fp_status); + return int64_to_float64(val, &env->fp_status); } =20 uint32_t HELPER(itofs)(CPUOpenRISCState *env, uint32_t val) @@ -73,7 +73,7 @@ uint32_t HELPER(itofs)(CPUOpenRISCState *env, uint32_t va= l) =20 uint64_t HELPER(ftoid)(CPUOpenRISCState *env, uint64_t val) { - return float32_to_int64(val, &env->fp_status); + return float64_to_int64_round_to_zero(val, &env->fp_status); } =20 uint32_t HELPER(ftois)(CPUOpenRISCState *env, uint32_t val) @@ -81,6 +81,16 @@ uint32_t HELPER(ftois)(CPUOpenRISCState *env, uint32_t v= al) return float32_to_int32_round_to_zero(val, &env->fp_status); } =20 +uint64_t HELPER(stod)(CPUOpenRISCState *env, uint32_t val) +{ + return float32_to_float64(val, &env->fp_status); +} + +uint32_t HELPER(dtos)(CPUOpenRISCState *env, uint64_t val) +{ + return float64_to_float32(val, &env->fp_status); +} + #define FLOAT_CALC(name) \ uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \ uint64_t fdt0, uint64_t fdt1) \ diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 2f5c969f21..b8ef485903 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -146,6 +146,11 @@ static bool check_of32s(DisasContext *dc) return dc->cpucfgr & CPUCFGR_OF32S; } =20 +static bool check_of64a32s(DisasContext *dc) +{ + return dc->cpucfgr & CPUCFGR_OF64A32S; +} + static TCGv cpu_R(DisasContext *dc, int reg) { if (reg =3D=3D 0) { @@ -1260,6 +1265,231 @@ static bool trans_lf_sfle_s(DisasContext *dc, arg_a= b *a) return do_fpcmp(dc, a, gen_helper_float_le_s, false, false); } =20 +static bool check_pair(DisasContext *dc, int r, int p) +{ + return r + 1 + p < 32; +} + +static void load_pair(DisasContext *dc, TCGv_i64 t, int r, int p) +{ + tcg_gen_concat_i32_i64(t, cpu_R(dc, r + 1 + p), cpu_R(dc, r)); +} + +static void save_pair(DisasContext *dc, TCGv_i64 t, int r, int p) +{ + tcg_gen_extr_i64_i32(cpu_R(dc, r + 1 + p), cpu_R(dc, r), t); +} + +static bool do_dp3(DisasContext *dc, arg_dab_pair *a, + void (*fn)(TCGv_i64, TCGv_env, TCGv_i64, TCGv_i64)) +{ + TCGv_i64 t0, t1; + + if (!check_of64a32s(dc) || + !check_pair(dc, a->a, a->ap) || + !check_pair(dc, a->b, a->bp) || + !check_pair(dc, a->d, a->dp)) { + return false; + } + check_r0_write(dc, a->d); + + t0 =3D tcg_temp_new_i64(); + t1 =3D tcg_temp_new_i64(); + load_pair(dc, t0, a->a, a->ap); + load_pair(dc, t1, a->b, a->bp); + fn(t0, cpu_env, t0, t1); + save_pair(dc, t0, a->d, a->dp); + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); + + gen_helper_update_fpcsr(cpu_env); + return true; +} + +static bool do_dp2(DisasContext *dc, arg_da_pair *a, + void (*fn)(TCGv_i64, TCGv_env, TCGv_i64)) +{ + TCGv_i64 t0; + + if (!check_of64a32s(dc) || + !check_pair(dc, a->a, a->ap) || + !check_pair(dc, a->d, a->dp)) { + return false; + } + check_r0_write(dc, a->d); + + t0 =3D tcg_temp_new_i64(); + load_pair(dc, t0, a->a, a->ap); + fn(t0, cpu_env, t0); + save_pair(dc, t0, a->d, a->dp); + tcg_temp_free_i64(t0); + + gen_helper_update_fpcsr(cpu_env); + return true; +} + +static bool do_dpcmp(DisasContext *dc, arg_ab_pair *a, + void (*fn)(TCGv, TCGv_env, TCGv_i64, TCGv_i64), + bool inv, bool swap) +{ + TCGv_i64 t0, t1; + + if (!check_of64a32s(dc) || + !check_pair(dc, a->a, a->ap) || + !check_pair(dc, a->b, a->bp)) { + return false; + } + + t0 =3D tcg_temp_new_i64(); + t1 =3D tcg_temp_new_i64(); + load_pair(dc, t0, a->a, a->ap); + load_pair(dc, t1, a->b, a->bp); + if (swap) { + fn(cpu_sr_f, cpu_env, t1, t0); + } else { + fn(cpu_sr_f, cpu_env, t0, t1); + } + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); + + if (inv) { + tcg_gen_xori_tl(cpu_sr_f, cpu_sr_f, 1); + } + gen_helper_update_fpcsr(cpu_env); + return true; +} + +static bool trans_lf_add_d(DisasContext *dc, arg_dab_pair *a) +{ + return do_dp3(dc, a, gen_helper_float_add_d); +} + +static bool trans_lf_sub_d(DisasContext *dc, arg_dab_pair *a) +{ + return do_dp3(dc, a, gen_helper_float_sub_d); +} + +static bool trans_lf_mul_d(DisasContext *dc, arg_dab_pair *a) +{ + return do_dp3(dc, a, gen_helper_float_mul_d); +} + +static bool trans_lf_div_d(DisasContext *dc, arg_dab_pair *a) +{ + return do_dp3(dc, a, gen_helper_float_div_d); +} + +static bool trans_lf_rem_d(DisasContext *dc, arg_dab_pair *a) +{ + return do_dp3(dc, a, gen_helper_float_rem_d); +} + +static bool trans_lf_itof_d(DisasContext *dc, arg_da_pair *a) +{ + return do_dp2(dc, a, gen_helper_itofd); +} + +static bool trans_lf_ftoi_d(DisasContext *dc, arg_da_pair *a) +{ + return do_dp2(dc, a, gen_helper_ftoid); +} + +static bool trans_lf_stod_d(DisasContext *dc, arg_lf_stod_d *a) +{ + TCGv_i64 t0; + + if (!check_of64a32s(dc) || + !check_pair(dc, a->d, a->dp)) { + return false; + } + check_r0_write(dc, a->d); + + t0 =3D tcg_temp_new_i64(); + gen_helper_stod(t0, cpu_env, cpu_R(dc, a->a)); + save_pair(dc, t0, a->d, a->dp); + tcg_temp_free_i64(t0); + + gen_helper_update_fpcsr(cpu_env); + return true; +} + +static bool trans_lf_dtos_d(DisasContext *dc, arg_lf_dtos_d *a) +{ + TCGv_i64 t0; + + if (!check_of64a32s(dc) || + !check_pair(dc, a->a, a->ap)) { + return false; + } + check_r0_write(dc, a->d); + + t0 =3D tcg_temp_new_i64(); + load_pair(dc, t0, a->a, a->ap); + gen_helper_dtos(cpu_R(dc, a->d), cpu_env, t0); + tcg_temp_free_i64(t0); + + gen_helper_update_fpcsr(cpu_env); + return true; +} + +static bool trans_lf_madd_d(DisasContext *dc, arg_dab_pair *a) +{ + TCGv_i64 t0, t1, t2; + + if (!check_of64a32s(dc) || + !check_pair(dc, a->a, a->ap) || + !check_pair(dc, a->b, a->bp) || + !check_pair(dc, a->d, a->dp)) { + return false; + } + check_r0_write(dc, a->d); + + t0 =3D tcg_temp_new_i64(); + t1 =3D tcg_temp_new_i64(); + t2 =3D tcg_temp_new_i64(); + load_pair(dc, t0, a->d, a->dp); + load_pair(dc, t1, a->a, a->ap); + load_pair(dc, t2, a->b, a->bp); + gen_helper_float_madd_d(t0, cpu_env, t0, t1, t2); + save_pair(dc, t0, a->d, a->dp); + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); + tcg_temp_free_i64(t2); + + gen_helper_update_fpcsr(cpu_env); + return true; +} + +static bool trans_lf_sfeq_d(DisasContext *dc, arg_ab_pair *a) +{ + return do_dpcmp(dc, a, gen_helper_float_eq_d, false, false); +} + +static bool trans_lf_sfne_d(DisasContext *dc, arg_ab_pair *a) +{ + return do_dpcmp(dc, a, gen_helper_float_eq_d, true, false); +} + +static bool trans_lf_sfgt_d(DisasContext *dc, arg_ab_pair *a) +{ + return do_dpcmp(dc, a, gen_helper_float_lt_d, false, true); +} + +static bool trans_lf_sfge_d(DisasContext *dc, arg_ab_pair *a) +{ + return do_dpcmp(dc, a, gen_helper_float_le_d, false, true); +} + +static bool trans_lf_sflt_d(DisasContext *dc, arg_ab_pair *a) +{ + return do_dpcmp(dc, a, gen_helper_float_lt_d, false, false); +} + +static bool trans_lf_sfle_d(DisasContext *dc, arg_ab_pair *a) +{ + return do_dpcmp(dc, a, gen_helper_float_le_d, false, false); +} + static void openrisc_tr_init_disas_context(DisasContextBase *dcb, CPUState= *cs) { DisasContext *dc =3D container_of(dcb, DisasContext, base); diff --git a/target/openrisc/insns.decode b/target/openrisc/insns.decode index 7df81c1f22..334d4e9668 100644 --- a/target/openrisc/insns.decode +++ b/target/openrisc/insns.decode @@ -22,6 +22,9 @@ &ab a b &dal d a l &ai a i +&dab_pair d a b dp ap bp +&ab_pair a b ap bp +&da_pair d a dp ap =20 #### # System Instructions @@ -187,3 +190,31 @@ lf_sfgt_s 110010 ----- a:5 b:5 --- 00001010 lf_sfge_s 110010 ----- a:5 b:5 --- 00001011 lf_sflt_s 110010 ----- a:5 b:5 --- 00001100 lf_sfle_s 110010 ----- a:5 b:5 --- 00001101 + +#### +# DP Instructions +#### + +@dab_pair ...... d:5 a:5 b:5 dp:1 ap:1 bp:1 ........ &dab_pair +@ab_pair ...... ..... a:5 b:5 . ap:1 bp:1 ........ &ab_pair +@da_pair ...... d:5 a:5 ..... dp:1 ap:1 . ........ &da_pair + +lf_add_d 110010 ..... ..... ..... ... 00010000 @dab_pair +lf_sub_d 110010 ..... ..... ..... ... 00010001 @dab_pair +lf_mul_d 110010 ..... ..... ..... ... 00010010 @dab_pair +lf_div_d 110010 ..... ..... ..... ... 00010011 @dab_pair +lf_rem_d 110010 ..... ..... ..... ... 00010110 @dab_pair +lf_madd_d 110010 ..... ..... ..... ... 00010111 @dab_pair + +lf_itof_d 110010 ..... ..... 00000 ..0 00010100 @da_pair +lf_ftoi_d 110010 ..... ..... 00000 ..0 00010101 @da_pair + +lf_stod_d 110010 d:5 a:5 00000 dp:1 0 0 00110100 +lf_dtos_d 110010 d:5 a:5 00000 0 ap:1 0 00110101 + +lf_sfeq_d 110010 00000 ..... ..... 0.. 00011000 @ab_pair +lf_sfne_d 110010 00000 ..... ..... 0.. 00011001 @ab_pair +lf_sfgt_d 110010 00000 ..... ..... 0.. 00011010 @ab_pair +lf_sfge_d 110010 00000 ..... ..... 0.. 00011011 @ab_pair +lf_sflt_d 110010 00000 ..... ..... 0.. 00011100 @ab_pair +lf_sfle_d 110010 00000 ..... ..... 0.. 00011101 @ab_pair --=20 2.17.1 From nobody Mon May 6 11:48:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id n66sm8104610pfn.90.2019.09.04.13.45.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 13:45:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=slEwt35AByzjU9Ubr6zMEmDVhlGjx8ZzwD/PYybphKw=; b=UMnStrVYvd/RNYanNLDF9REk42LeewIj8RBhxFMm9wS+KyxQXrllGOm/d7j+khGdLg dPbbRfM+mqAjUsJzOQ8HOrZHxnlo4VMvUlFc7ju/SfaQ3FuDCt4d6cpJ0qKL84GKPOc9 INq0MxB/BJENzLalp6LH7QTtPhz9QPksOOaViLI+gO/Lf/swUphHGUqptg7Qsgj56BZF qeVnN0WsCKz3jwM9M648Vj4WYIYPnMEQU6f7fA0zLgbAsxnKGLZlXwaVR2PK0JDlHTgZ MRClU4ITUO+s2WhBE3PwfU4pBOqQ4wCQyXJliw+IGVnMDI7Jx5t9Es7lDIYZ1WAmfKS+ uaBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=slEwt35AByzjU9Ubr6zMEmDVhlGjx8ZzwD/PYybphKw=; b=eSF20GWxQknqJ217zn8c32mqd2CGA+2HxjgycFceHZRMvIke5uTLcxWNJSUeLsP0J8 iaHnkwsJXCF8N6OFHuWoW6HNwytivk+qsvCydNwpj6s9FLoBjVdZ32LU2JLqaAJSMwO+ DuDWF4moFz457ya3zoSF3ALY9Bf4Wej0NhcGXJRY62LZapK3Wm/G71e8t26AgPz60urj w/zC1MQhkqNDsW0JZHksExzL5veEprncOggJBnhd7hTqeHc577PHXfcDHcQ71k28nztD UxFhVN2399GU+rVxg6HydhO+hg/cLjEmbQH/8dDjL8tBz51wXaNCGyZ5I27z3G/yhWnN NQAA== X-Gm-Message-State: APjAAAWg3JJpQ7jP0S01NtR7HR9BNkddlsFmDxy5s9FkdUhr9dRP0ITf w4OQlOiboxBpPLSZhDnzPP7rKunOWIc= X-Google-Smtp-Source: APXvYqyyA0nIi9efCgUCgecygo2myZ3ti58mF5EZbcBFW6PnwpSrP4aFvHTyEhdB6avFnLMV7AAbqg== X-Received: by 2002:aa7:93a8:: with SMTP id x8mr15781391pff.151.1567629921841; Wed, 04 Sep 2019 13:45:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 13:45:04 -0700 Message-Id: <20190904204507.32457-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904204507.32457-1-richard.henderson@linaro.org> References: <20190904204507.32457-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::430 Subject: [Qemu-devel] [PULL 10/13] target/openrisc: Implement unordered fp comparisons X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" These were added to the 1.3 spec. For OF32S, validate AVR. But OF64A32 is itself new to 1.3 so no extra check needed. Reviewed-by: Stafford Horne Signed-off-by: Richard Henderson --- target/openrisc/helper.h | 4 ++ target/openrisc/disas.c | 24 ++++++++++ target/openrisc/fpu_helper.c | 20 +++++++++ target/openrisc/translate.c | 85 ++++++++++++++++++++++++++++++++++++ target/openrisc/insns.decode | 12 +++++ 5 files changed, 145 insertions(+) diff --git a/target/openrisc/helper.h b/target/openrisc/helper.h index 94b823580e..d847814a28 100644 --- a/target/openrisc/helper.h +++ b/target/openrisc/helper.h @@ -52,6 +52,10 @@ DEF_HELPER_FLAGS_3(float_ ## op ## _d, TCG_CALL_NO_RWG, = tl, env, i64, i64) FOP_CMP(eq) FOP_CMP(lt) FOP_CMP(le) +FOP_CMP(un) +FOP_CMP(ueq) +FOP_CMP(ule) +FOP_CMP(ult) #undef FOP_CMP =20 /* interrupt */ diff --git a/target/openrisc/disas.c b/target/openrisc/disas.c index 4de5c632de..e51cbb24c6 100644 --- a/target/openrisc/disas.c +++ b/target/openrisc/disas.c @@ -166,6 +166,12 @@ FP_INSN(sfgt, s, "r%d, r%d", a->a, a->b) FP_INSN(sfge, s, "r%d, r%d", a->a, a->b) FP_INSN(sflt, s, "r%d, r%d", a->a, a->b) FP_INSN(sfle, s, "r%d, r%d", a->a, a->b) +FP_INSN(sfun, s, "r%d, r%d", a->a, a->b) +FP_INSN(sfueq, s, "r%d, r%d", a->a, a->b) +FP_INSN(sfuge, s, "r%d, r%d", a->a, a->b) +FP_INSN(sfugt, s, "r%d, r%d", a->a, a->b) +FP_INSN(sfule, s, "r%d, r%d", a->a, a->b) +FP_INSN(sfult, s, "r%d, r%d", a->a, a->b) =20 FP_INSN(add, d, "r%d,r%d, r%d,r%d, r%d,r%d", a->d, a->d + a->dp + 1, @@ -222,3 +228,21 @@ FP_INSN(sflt, d, "r%d,r%d, r%d,r%d", FP_INSN(sfle, d, "r%d,r%d, r%d,r%d", a->a, a->a + a->ap + 1, a->b, a->b + a->bp + 1) +FP_INSN(sfun, d, "r%d,r%d, r%d,r%d", + a->a, a->a + a->ap + 1, + a->b, a->b + a->bp + 1) +FP_INSN(sfueq, d, "r%d,r%d, r%d,r%d", + a->a, a->a + a->ap + 1, + a->b, a->b + a->bp + 1) +FP_INSN(sfuge, d, "r%d,r%d, r%d,r%d", + a->a, a->a + a->ap + 1, + a->b, a->b + a->bp + 1) +FP_INSN(sfugt, d, "r%d,r%d, r%d,r%d", + a->a, a->a + a->ap + 1, + a->b, a->b + a->bp + 1) +FP_INSN(sfule, d, "r%d,r%d, r%d,r%d", + a->a, a->a + a->ap + 1, + a->b, a->b + a->bp + 1) +FP_INSN(sfult, d, "r%d,r%d, r%d,r%d", + a->a, a->a + a->ap + 1, + a->b, a->b + a->bp + 1) diff --git a/target/openrisc/fpu_helper.c b/target/openrisc/fpu_helper.c index 9d7dfc0fb9..7bcef9dc53 100644 --- a/target/openrisc/fpu_helper.c +++ b/target/openrisc/fpu_helper.c @@ -135,4 +135,24 @@ target_ulong helper_float_ ## name ## _s(CPUOpenRISCSt= ate *env, \ FLOAT_CMP(le, le) FLOAT_CMP(lt, lt) FLOAT_CMP(eq, eq_quiet) +FLOAT_CMP(un, unordered_quiet) #undef FLOAT_CMP + +#define FLOAT_UCMP(name, expr) \ +target_ulong helper_float_ ## name ## _d(CPUOpenRISCState *env, \ + uint64_t fdt0, uint64_t fdt1) \ +{ \ + int r =3D float64_compare_quiet(fdt0, fdt1, &env->fp_status); = \ + return expr; \ +} \ +target_ulong helper_float_ ## name ## _s(CPUOpenRISCState *env, \ + uint32_t fdt0, uint32_t fdt1) \ +{ \ + int r =3D float32_compare_quiet(fdt0, fdt1, &env->fp_status); = \ + return expr; \ +} + +FLOAT_UCMP(ueq, r =3D=3D float_relation_equal || r =3D=3D float_relation_u= nordered) +FLOAT_UCMP(ult, r =3D=3D float_relation_less || r =3D=3D float_relation_un= ordered) +FLOAT_UCMP(ule, r !=3D float_relation_greater) +#undef FLOAT_UCMP diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index b8ef485903..6e8bc23568 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -46,6 +46,7 @@ typedef struct DisasContext { uint32_t tb_flags; uint32_t delayed_branch; uint32_t cpucfgr; + uint32_t avr; =20 /* If not -1, jmp_pc contains this value and so is a direct jump. */ target_ulong jmp_pc_imm; @@ -141,6 +142,11 @@ static void gen_illegal_exception(DisasContext *dc) dc->base.is_jmp =3D DISAS_NORETURN; } =20 +static bool check_v1_3(DisasContext *dc) +{ + return dc->avr >=3D 0x01030000; +} + static bool check_of32s(DisasContext *dc) { return dc->cpucfgr & CPUCFGR_OF32S; @@ -1265,6 +1271,54 @@ static bool trans_lf_sfle_s(DisasContext *dc, arg_ab= *a) return do_fpcmp(dc, a, gen_helper_float_le_s, false, false); } =20 +static bool trans_lf_sfueq_s(DisasContext *dc, arg_ab *a) +{ + if (!check_v1_3(dc)) { + return false; + } + return do_fpcmp(dc, a, gen_helper_float_ueq_s, false, false); +} + +static bool trans_lf_sfult_s(DisasContext *dc, arg_ab *a) +{ + if (!check_v1_3(dc)) { + return false; + } + return do_fpcmp(dc, a, gen_helper_float_ult_s, false, false); +} + +static bool trans_lf_sfugt_s(DisasContext *dc, arg_ab *a) +{ + if (!check_v1_3(dc)) { + return false; + } + return do_fpcmp(dc, a, gen_helper_float_ult_s, false, true); +} + +static bool trans_lf_sfule_s(DisasContext *dc, arg_ab *a) +{ + if (!check_v1_3(dc)) { + return false; + } + return do_fpcmp(dc, a, gen_helper_float_ule_s, false, false); +} + +static bool trans_lf_sfuge_s(DisasContext *dc, arg_ab *a) +{ + if (!check_v1_3(dc)) { + return false; + } + return do_fpcmp(dc, a, gen_helper_float_ule_s, false, true); +} + +static bool trans_lf_sfun_s(DisasContext *dc, arg_ab *a) +{ + if (!check_v1_3(dc)) { + return false; + } + return do_fpcmp(dc, a, gen_helper_float_un_s, false, false); +} + static bool check_pair(DisasContext *dc, int r, int p) { return r + 1 + p < 32; @@ -1490,6 +1544,36 @@ static bool trans_lf_sfle_d(DisasContext *dc, arg_ab= _pair *a) return do_dpcmp(dc, a, gen_helper_float_le_d, false, false); } =20 +static bool trans_lf_sfueq_d(DisasContext *dc, arg_ab_pair *a) +{ + return do_dpcmp(dc, a, gen_helper_float_ueq_d, false, false); +} + +static bool trans_lf_sfule_d(DisasContext *dc, arg_ab_pair *a) +{ + return do_dpcmp(dc, a, gen_helper_float_ule_d, false, false); +} + +static bool trans_lf_sfuge_d(DisasContext *dc, arg_ab_pair *a) +{ + return do_dpcmp(dc, a, gen_helper_float_ule_d, false, true); +} + +static bool trans_lf_sfult_d(DisasContext *dc, arg_ab_pair *a) +{ + return do_dpcmp(dc, a, gen_helper_float_ult_d, false, false); +} + +static bool trans_lf_sfugt_d(DisasContext *dc, arg_ab_pair *a) +{ + return do_dpcmp(dc, a, gen_helper_float_ult_d, false, true); +} + +static bool trans_lf_sfun_d(DisasContext *dc, arg_ab_pair *a) +{ + return do_dpcmp(dc, a, gen_helper_float_un_d, false, false); +} + static void openrisc_tr_init_disas_context(DisasContextBase *dcb, CPUState= *cs) { DisasContext *dc =3D container_of(dcb, DisasContext, base); @@ -1500,6 +1584,7 @@ static void openrisc_tr_init_disas_context(DisasConte= xtBase *dcb, CPUState *cs) dc->tb_flags =3D dc->base.tb->flags; dc->delayed_branch =3D (dc->tb_flags & TB_FLAGS_DFLAG) !=3D 0; dc->cpucfgr =3D env->cpucfgr; + dc->avr =3D env->avr; dc->jmp_pc_imm =3D -1; =20 bound =3D -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; diff --git a/target/openrisc/insns.decode b/target/openrisc/insns.decode index 334d4e9668..71e0d740db 100644 --- a/target/openrisc/insns.decode +++ b/target/openrisc/insns.decode @@ -190,6 +190,12 @@ lf_sfgt_s 110010 ----- a:5 b:5 --- 00001010 lf_sfge_s 110010 ----- a:5 b:5 --- 00001011 lf_sflt_s 110010 ----- a:5 b:5 --- 00001100 lf_sfle_s 110010 ----- a:5 b:5 --- 00001101 +lf_sfueq_s 110010 ----- a:5 b:5 --- 00101000 +lf_sfuge_s 110010 ----- a:5 b:5 --- 00101011 +lf_sfugt_s 110010 ----- a:5 b:5 --- 00101010 +lf_sfule_s 110010 ----- a:5 b:5 --- 00101101 +lf_sfult_s 110010 ----- a:5 b:5 --- 00101100 +lf_sfun_s 110010 ----- a:5 b:5 --- 00101110 =20 #### # DP Instructions @@ -218,3 +224,9 @@ lf_sfgt_d 110010 00000 ..... ..... 0.. 00011010 = @ab_pair lf_sfge_d 110010 00000 ..... ..... 0.. 00011011 @ab_pair lf_sflt_d 110010 00000 ..... ..... 0.. 00011100 @ab_pair lf_sfle_d 110010 00000 ..... ..... 0.. 00011101 @ab_pair +lf_sfueq_d 110010 00000 ..... ..... 0.. 00111000 @ab_pair +lf_sfuge_d 110010 00000 ..... ..... 0.. 00111011 @ab_pair +lf_sfugt_d 110010 00000 ..... ..... 0.. 00111010 @ab_pair +lf_sfule_d 110010 00000 ..... ..... 0.. 00111101 @ab_pair +lf_sfult_d 110010 00000 ..... ..... 0.. 00111100 @ab_pair +lf_sfun_d 110010 00000 ..... ..... 0.. 00111110 @ab_pair --=20 2.17.1 From nobody Mon May 6 11:48:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::630 Subject: [Qemu-devel] [PULL 11/13] target/openrisc: Implement move to/from FPCSR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Stafford Horne Signed-off-by: Richard Henderson --- target/openrisc/cpu.h | 2 ++ target/openrisc/cpu.c | 1 + target/openrisc/fpu_helper.c | 13 +++++++++++++ target/openrisc/machine.c | 11 +++++++++++ target/openrisc/sys_helper.c | 18 ++++++++++++------ 5 files changed, 39 insertions(+), 6 deletions(-) diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 71c5959828..0ad02eab79 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -413,6 +413,8 @@ static inline void cpu_set_sr(CPUOpenRISCState *env, ui= nt32_t val) env->sr =3D (val & ~(SR_F | SR_CY | SR_OV)) | SR_FO; } =20 +void cpu_set_fpcsr(CPUOpenRISCState *env, uint32_t val); + #define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_INT_0 =20 #endif /* OPENRISC_CPU_H */ diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index b931605e62..f96a69e278 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -55,6 +55,7 @@ static void openrisc_cpu_reset(CPUState *s) cpu->env.sr =3D SR_FO | SR_SM; cpu->env.lock_addr =3D -1; s->exception_index =3D -1; + cpu_set_fpcsr(&cpu->env, 0); =20 #ifndef CONFIG_USER_ONLY cpu->env.picmr =3D 0x00000000; diff --git a/target/openrisc/fpu_helper.c b/target/openrisc/fpu_helper.c index 7bcef9dc53..59e1413279 100644 --- a/target/openrisc/fpu_helper.c +++ b/target/openrisc/fpu_helper.c @@ -61,6 +61,19 @@ void HELPER(update_fpcsr)(CPUOpenRISCState *env) } } =20 +void cpu_set_fpcsr(CPUOpenRISCState *env, uint32_t val) +{ + static const int rm_to_sf[] =3D { + float_round_nearest_even, + float_round_to_zero, + float_round_up, + float_round_down + }; + + env->fpcsr =3D val & 0x7ff; + set_float_rounding_mode(rm_to_sf[extract32(val, 1, 2)], &env->fp_statu= s); +} + uint64_t HELPER(itofd)(CPUOpenRISCState *env, uint64_t val) { return int64_to_float64(val, &env->fp_status); diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c index 0a96404dc6..b92985d99b 100644 --- a/target/openrisc/machine.c +++ b/target/openrisc/machine.c @@ -121,10 +121,21 @@ static const VMStateDescription vmstate_env =3D { } }; =20 +static int cpu_post_load(void *opaque, int version_id) +{ + OpenRISCCPU *cpu =3D opaque; + CPUOpenRISCState *env =3D &cpu->env; + + /* Update env->fp_status to match env->fpcsr. */ + cpu_set_fpcsr(env, env->fpcsr); + return 0; +} + const VMStateDescription vmstate_openrisc_cpu =3D { .name =3D "cpu", .version_id =3D 1, .minimum_version_id =3D 1, + .post_load =3D cpu_post_load, .fields =3D (VMStateField[]) { VMSTATE_CPU(), VMSTATE_STRUCT(env, OpenRISCCPU, 1, vmstate_env, CPUOpenRISCState), diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index cf8e637b08..d9fe6c5948 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -37,8 +37,10 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong s= pr, target_ulong rb) CPUState *cs =3D env_cpu(env); target_ulong mr; int idx; +#endif =20 switch (spr) { +#ifndef CONFIG_USER_ONLY case TO_SPR(0, 11): /* EVBAR */ env->evbar =3D rb; break; @@ -179,10 +181,12 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulon= g spr, target_ulong rb) } cpu_openrisc_timer_update(cpu); break; - default: +#endif + + case TO_SPR(0, 20): /* FPCSR */ + cpu_set_fpcsr(env, rb); break; } -#endif } =20 target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd, @@ -193,8 +197,10 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, targ= et_ulong rd, OpenRISCCPU *cpu =3D env_archcpu(env); CPUState *cs =3D env_cpu(env); int idx; +#endif =20 switch (spr) { +#ifndef CONFIG_USER_ONLY case TO_SPR(0, 0): /* VR */ return env->vr; =20 @@ -303,12 +309,12 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, tar= get_ulong rd, case TO_SPR(10, 1): /* TTCR */ cpu_openrisc_count_update(cpu); return cpu_openrisc_count_get(cpu); - - default: - break; - } #endif =20 + case TO_SPR(0, 20): /* FPCSR */ + return env->fpcsr; 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X-Received-From: 2607:f8b0:4864:20::432 Subject: [Qemu-devel] [PULL 12/13] target/openrisc: Implement l.adrp X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This was added to the 1.3 spec. Reviewed-by: Stafford Horne Signed-off-by: Richard Henderson --- target/openrisc/disas.c | 1 + target/openrisc/translate.c | 13 +++++++++++++ target/openrisc/insns.decode | 2 ++ 3 files changed, 16 insertions(+) diff --git a/target/openrisc/disas.c b/target/openrisc/disas.c index e51cbb24c6..ce112640b9 100644 --- a/target/openrisc/disas.c +++ b/target/openrisc/disas.c @@ -98,6 +98,7 @@ INSN(sw, "%d(r%d), r%d", a->i, a->a, a->b) INSN(sb, "%d(r%d), r%d", a->i, a->a, a->b) INSN(sh, "%d(r%d), r%d", a->i, a->a, a->b) INSN(nop, "") +INSN(adrp, "r%d, %d", a->d, a->i) INSN(addi, "r%d, r%d, %d", a->d, a->a, a->i) INSN(addic, "r%d, r%d, %d", a->d, a->a, a->i) INSN(muli, "r%d, r%d, %d", a->d, a->a, a->i) diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 6e8bc23568..6addbac8d6 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -799,6 +799,19 @@ static bool trans_l_nop(DisasContext *dc, arg_l_nop *a) return true; } =20 +static bool trans_l_adrp(DisasContext *dc, arg_l_adrp *a) +{ + if (!check_v1_3(dc)) { + return false; + } + check_r0_write(dc, a->d); + + tcg_gen_movi_i32(cpu_R(dc, a->d), + (dc->base.pc_next & TARGET_PAGE_MASK) + + ((target_long)a->i << TARGET_PAGE_BITS)); + return true; +} + static bool trans_l_addi(DisasContext *dc, arg_rri *a) { TCGv t0; diff --git a/target/openrisc/insns.decode b/target/openrisc/insns.decode index 71e0d740db..0d6f7c29f8 100644 --- a/target/openrisc/insns.decode +++ b/target/openrisc/insns.decode @@ -102,6 +102,8 @@ l_maci 010011 ----- a:5 i:s16 l_movhi 000110 d:5 ----0 k:16 l_macrc 000110 d:5 ----1 00000000 00000000 =20 +l_adrp 000010 d:5 i:s21 + #### # Arithmetic Instructions #### --=20 2.17.1 From nobody Mon May 6 11:48:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567632231; cv=none; d=zoho.com; s=zohoarc; b=cdhEkmrzpZzolLFOjiGZmHnveBt9F6ZM68HPI/03/ZMhs27vmCdMzT/NIqdRm7DZgS7beKwCcDwTFVBk+VTkxffsTWS6sFCwDlnHkxKuBBAafpVm9KVnSTI8vrvrFjMe8EXrWSUMcp8Y6ORPj+U7mGsAD9QcB61/hEpM1NphwVM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567632231; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=1viOu5GL1Auv3D+RvMLd1iNczsL4mRxNizWgcflzx+Q=; b=gh93HaBrrHqB0LuflBQS3JzOfgkSQXH+WTxYgW7Au/ZzGEClu5wZhFzNzcWWNXV10jWzYlB9Eb5KNoFKLUZ1fHY2bdaE7+lbBf2+47WbFcw2BJXi4CS+mD2sLB8hoOV9ibylrsy/VBkgdUk49Yns5iCtVL8Z/bNaAcW+lpAnKv0= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567632231336868.9500560342775; Wed, 4 Sep 2019 14:23:51 -0700 (PDT) Received: from localhost ([::1]:40110 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5ckk-0004lm-Fe for importer@patchew.org; Wed, 04 Sep 2019 17:23:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52949) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5c9g-0006Ls-3c for qemu-devel@nongnu.org; Wed, 04 Sep 2019 16:45:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5c9e-0006xH-Hj for qemu-devel@nongnu.org; Wed, 04 Sep 2019 16:45:27 -0400 Received: from mail-pf1-x442.google.com ([2607:f8b0:4864:20::442]:46660) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i5c9e-0006ve-9l for qemu-devel@nongnu.org; Wed, 04 Sep 2019 16:45:26 -0400 Received: by mail-pf1-x442.google.com with SMTP id q5so11663pfg.13 for ; Wed, 04 Sep 2019 13:45:26 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id n66sm8104610pfn.90.2019.09.04.13.45.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 13:45:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1viOu5GL1Auv3D+RvMLd1iNczsL4mRxNizWgcflzx+Q=; b=g97Iw9a4YpDqZkxyCAAjqM0FLF7LhXGIg38+xJ9glbLWbFxnGD1TfdFfQqedu+wXJj U1M87erXHmQhHwTxR6c/CHe/dyzs81/+kBrQeKLsYcBujJp7DC/f/u7zxccrAYc9doUz 048i8exZu6MWQg2DnND2wmfj263Z+wIQ2fDUJhrjL9U5WhHJlocqsPnTAFZxgVaak3ou Wg3rB5KKGhjyalIx5ApvXr+AhCz7K5/V9HefYLvO34Ie+o0hOzbFkewtWfkPhTSjXpHL CY+YZxa10MOh5652fsbYYsaYQOXy1elOlJg9caNmNPr+BlPZWuH/V7tfp8G7q8QgYVSq hhjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1viOu5GL1Auv3D+RvMLd1iNczsL4mRxNizWgcflzx+Q=; b=ZF6MI9NAdctvTINeuofmU2XJ00gPv9oRVJV3Ovuth/HeZ1Rvgrh+qSLQZs9/2fEFCS Qx3YJjqvpKnszLQCW0YaPxj7eYv3jnQawgPP2znjw4DPYk9t0Dz4CclN1MLGreQVyzma bqrNv7bWU/INKJnliOfeK78H8PvYUKhgnq0puoPIaIrOqEnb1crDNJ9MWWJbrldZ+czx K1LciLnnk1Pe733hQHcKBCoDCdGOaAQeW4QvunMo6cEf7xModYDggSIp5xAVimg+2N3Y B9RC93+e9pbcdrZgwS7UpOq0wMomTg7uKsTinm2fh0F4KcyuP00EoW8iOJ21MmlHJ9EX rv8A== X-Gm-Message-State: APjAAAU7ifHQfCvcd6jLZK3wRjdL5G39LpmWqPbvMwzf05czn5y+rVWW s3ie816gMHMt1z+jBVx+MdkbR+e0vMc= X-Google-Smtp-Source: APXvYqzzLG0x7CGWVAZr2STWJ/AJRxbWAlGqePrKZdlICL4faMEAV1gpWZLoDT3q9Thu/DnHn4B3yg== X-Received: by 2002:aa7:9591:: with SMTP id z17mr48833868pfj.215.1567629925120; Wed, 04 Sep 2019 13:45:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 13:45:07 -0700 Message-Id: <20190904204507.32457-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904204507.32457-1-richard.henderson@linaro.org> References: <20190904204507.32457-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PULL 13/13] target/openrisc: Update cpu "any" to v1.3 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Now that the two updates from v1.3 are implemented, update the "any" cpu to enable it. Reviewed-by: Stafford Horne Signed-off-by: Richard Henderson --- target/openrisc/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index f96a69e278..506aec6bfb 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -129,7 +129,7 @@ static void openrisc_any_initfn(Object *obj) =20 cpu->env.vr =3D 0x13000040; /* Obsolete VER + UVRP for new SPRs */ cpu->env.vr2 =3D 0; /* No version specific id */ - cpu->env.avr =3D 0x01010000; /* Architecture v1.1 */ + cpu->env.avr =3D 0x01030000; /* Architecture v1.3 */ =20 cpu->env.upr =3D UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR= _PMP; cpu->env.cpucfgr =3D CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S | --=20 2.17.1