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Wed, 04 Sep 2019 04:21:12 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:21:04 +0100 Message-Id: <20190904112108.2341-2-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190904112108.2341-1-alex.bennee@linaro.org> References: <20190904112108.2341-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::335 Subject: [Qemu-devel] [PATCH v2 1/5] target/arm: handle M-profile semihosting at translate time X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) We do this for other semihosting calls so we might as well do it for M-profile as well. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- v2 - update for change to gen_exception_internal_insn API --- target/arm/m_helper.c | 18 ++++++------------ target/arm/translate.c | 20 +++++++++++++++++++- 2 files changed, 25 insertions(+), 13 deletions(-) diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 884d35d2b02..27cd2f3f964 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -2114,19 +2114,13 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) break; } break; + case EXCP_SEMIHOST: + qemu_log_mask(CPU_LOG_INT, + "...handling as semihosting call 0x%x\n", + env->regs[0]); + env->regs[0] =3D do_arm_semihosting(env); + return; case EXCP_BKPT: - if (semihosting_enabled()) { - int nr; - nr =3D arm_lduw_code(env, env->regs[15], arm_sctlr_b(env)) & 0= xff; - if (nr =3D=3D 0xab) { - env->regs[15] +=3D 2; - qemu_log_mask(CPU_LOG_INT, - "...handling as semihosting call 0x%x\n", - env->regs[0]); - env->regs[0] =3D do_arm_semihosting(env); - return; - } - } armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG, false); break; case EXCP_IRQ: diff --git a/target/arm/translate.c b/target/arm/translate.c index 615859e23c5..816d46b2205 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10931,6 +10931,24 @@ illegal_op: unallocated_encoding(s); } =20 +/* + * Thumb BKPT. On M-profile CPUs this may be a semihosting call which + * we can process much the same way as gen_hlt() above. + */ +static inline void gen_thumb_bkpt(DisasContext *s, int imm8) +{ + if (arm_dc_feature(s, ARM_FEATURE_M) && + semihosting_enabled() && +#ifndef CONFIG_USER_ONLY + s->current_el !=3D 0 && +#endif + (imm8 =3D=3D 0xab)) { + gen_exception_internal_insn(s, s->base.pc_next, EXCP_SEMIHOST); + return; + } + gen_exception_bkpt_insn(s, syn_aa32_bkpt(imm8, true)); +} + static void disas_thumb_insn(DisasContext *s, uint32_t insn) { uint32_t val, op, rm, rn, rd, shift, cond; @@ -11553,7 +11571,7 @@ static void disas_thumb_insn(DisasContext *s, uint3= 2_t insn) { int imm8 =3D extract32(insn, 0, 8); ARCH(5); - gen_exception_bkpt_insn(s, syn_aa32_bkpt(imm8, true)); + gen_thumb_bkpt(s, imm8); break; } =20 --=20 2.20.1