From nobody Wed Nov 12 03:45:30 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1567581362; cv=none; d=zoho.com; s=zohoarc; b=m56dBq8WUTOZg+ROZazYGM5PiE1PNtJSBe15uvvrinySqzqr8Uf3JCKFZ9XPrAKLc0yhPxegdzT3dYovctZk7wXuMsIEu20JykQZjASb/wAEMbHMmL2m8Vwxhbkmw7asKKZhOcKnmhFkH/7cLYpxFlChAG56ly42JzCyRcIqbP4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567581362; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=v9S36bC1nedchqnp/BFCtS9tEZPgVdbIR+y20NwRHNY=; b=n/DXdZCbIqreEvRT5U6JEvcDbwZlmrPFvLOOrTRM9Vq8ud/j9wKEmw1zq63LoPsF/L8FDu1pnzgipGI+oVxvTZlWmshUB8M59MlhT0fFVWUYUdq/2CJjwEUPm63OFUlzxIvZZjxnIXNyLG5pY2v0RbP+wYpg1CcPHjwpS+wPZCU= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567581362730217.5050858069486; Wed, 4 Sep 2019 00:16:02 -0700 (PDT) Received: from localhost ([::1]:54072 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5PWL-0001pU-FW for importer@patchew.org; Wed, 04 Sep 2019 03:16:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47925) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5PMs-000240-LA for qemu-devel@nongnu.org; Wed, 04 Sep 2019 03:06:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5PMr-0006dJ-Bx for qemu-devel@nongnu.org; Wed, 04 Sep 2019 03:06:14 -0400 Received: from 18.mo1.mail-out.ovh.net ([46.105.35.72]:48887) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1i5PMr-0006cG-5y for qemu-devel@nongnu.org; Wed, 04 Sep 2019 03:06:13 -0400 Received: from player690.ha.ovh.net (unknown [10.109.160.253]) by mo1.mail-out.ovh.net (Postfix) with ESMTP id 8265918D63A for ; Wed, 4 Sep 2019 09:06:11 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player690.ha.ovh.net (Postfix) with ESMTPSA id 1E2EC94DCA1C; Wed, 4 Sep 2019 07:06:03 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: Peter Maydell Date: Wed, 4 Sep 2019 09:05:03 +0200 Message-Id: <20190904070506.1052-8-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190904070506.1052-1-clg@kaod.org> References: <20190904070506.1052-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 7089510239021271825 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduvddrudejgedgudduudcutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.105.35.72 Subject: [Qemu-devel] [PATCH 07/10] aspeed/smc: Inject errors in DMA checksum X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jeffery , qemu-devel@nongnu.org, qemu-arm@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Joel Stanley Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Emulate read errors in the DMA Checksum Register for high frequencies and optimistic settings of the Read Timing Compensation Register. This will help in tuning the SPI timing calibration algorithm. Errors are only injected when the property "inject_failure" is set to true as suggested by Philippe. The values below are those to expect from the first flash device of the FMC controller of a palmetto-bmc machine. Cc: Philippe Mathieu-Daud=C3=A9 Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: Joel Stanley --- include/hw/ssi/aspeed_smc.h | 1 + hw/ssi/aspeed_smc.c | 36 ++++++++++++++++++++++++++++++++++++ 2 files changed, 37 insertions(+) diff --git a/include/hw/ssi/aspeed_smc.h b/include/hw/ssi/aspeed_smc.h index 32ce6916f6cc..5176ff6bf95f 100644 --- a/include/hw/ssi/aspeed_smc.h +++ b/include/hw/ssi/aspeed_smc.h @@ -88,6 +88,7 @@ typedef struct AspeedSMCState { =20 uint32_t num_cs; qemu_irq *cs_lines; + bool inject_failure; =20 SSIBus *spi; =20 diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index 7a0cd7607fd0..5c3436db5e8f 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -869,6 +869,36 @@ static void aspeed_smc_dma_calibration(AspeedSMCState = *s) s->regs[s->r_ctrl0 + cs] |=3D CE_CTRL_CLOCK_FREQ(hclk_div); } =20 +/* + * Emulate read errors in the DMA Checksum Register for high + * frequencies and optimistic settings of the Read Timing Compensation + * Register. This will help in tuning the SPI timing calibration + * algorithm. + */ +static bool aspeed_smc_inject_read_failure(AspeedSMCState *s) +{ + uint8_t delay =3D + (s->regs[R_DMA_CTRL] >> DMA_CTRL_DELAY_SHIFT) & DMA_CTRL_DELAY_MAS= K; + uint8_t hclk_mask =3D + (s->regs[R_DMA_CTRL] >> DMA_CTRL_FREQ_SHIFT) & DMA_CTRL_FREQ_MASK; + + /* + * Typical values of a palmetto-bmc machine. + */ + switch (aspeed_smc_hclk_divisor(hclk_mask)) { + case 4 ... 16: + return false; + case 3: /* at least one HCLK cycle delay */ + return (delay & 0x7) < 1; + case 2: /* at least two HCLK cycle delay */ + return (delay & 0x7) < 2; + case 1: /* (> 100MHz) is above the max freq of the controller */ + return true; + default: + g_assert_not_reached(); + } +} + /* * Accumulate the result of the reads to provide a checksum that will * be used to validate the read timing settings. @@ -905,6 +935,11 @@ static void aspeed_smc_dma_checksum(AspeedSMCState *s) s->regs[R_DMA_FLASH_ADDR] +=3D 4; s->regs[R_DMA_LEN] -=3D 4; } + + if (s->inject_failure && aspeed_smc_inject_read_failure(s)) { + s->regs[R_DMA_CHECKSUM] =3D 0xbadc0de; + } + } =20 static void aspeed_smc_dma_rw(AspeedSMCState *s) @@ -1185,6 +1220,7 @@ static const VMStateDescription vmstate_aspeed_smc = =3D { =20 static Property aspeed_smc_properties[] =3D { DEFINE_PROP_UINT32("num-cs", AspeedSMCState, num_cs, 1), + DEFINE_PROP_BOOL("inject-failure", AspeedSMCState, inject_failure, fal= se), DEFINE_PROP_UINT64("sdram-base", AspeedSMCState, sdram_base, 0), DEFINE_PROP_LINK("dram", AspeedSMCState, dram_mr, TYPE_MEMORY_REGION, MemoryRegion *), --=20 2.21.0