From nobody Wed Nov 12 03:45:31 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1567581100; cv=none; d=zoho.com; s=zohoarc; b=iBPfVS65tG9qtEUZHzx9P5NAQKd1Uo0WeeY6PLAoycMMm8OL10Uj5uGglbXX51BwI9zssYTv/3Y7s1VUF/0VoV3NWTbQ+Cm7WOwE+lkgCMEb4kXdEYy2wzb99I1pTMc5g8nCiIsmApDCIKMq+VDAnWQE0dwwNn1QC5QFCF301YE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567581100; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=KZc/b4q1d7k6B4oDiSg8iyuYbln6Ed4s4XB5cm0n9E8=; b=JqRK8owBFZ8qTZLYcjQ6mQaAwAMb96J1ADsaWr0Ru0PF87SzWGHJO+US59Sq7i0YynSiMdIYuRWDtidrARWiUmDCE7L6T7ARWCOiaycL0IIvzOAqOIK0AREcWKsYF08un2I7VWkRW4lE8JzrVsRvgjtHrzCm8NnwMAGCvSTH3Js= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567581100004528.7077036225484; Wed, 4 Sep 2019 00:11:40 -0700 (PDT) Received: from localhost ([::1]:54044 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5PS6-0007Lo-Nt for importer@patchew.org; Wed, 04 Sep 2019 03:11:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47889) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5PMj-0001sb-ST for qemu-devel@nongnu.org; Wed, 04 Sep 2019 03:06:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5PMi-0006X7-KK for qemu-devel@nongnu.org; Wed, 04 Sep 2019 03:06:05 -0400 Received: from 7.mo69.mail-out.ovh.net ([46.105.50.32]:47490) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1i5PMi-0006WE-EZ for qemu-devel@nongnu.org; Wed, 04 Sep 2019 03:06:04 -0400 Received: from player690.ha.ovh.net (unknown [10.108.42.184]) by mo69.mail-out.ovh.net (Postfix) with ESMTP id 28A9C683BC for ; Wed, 4 Sep 2019 09:06:03 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player690.ha.ovh.net (Postfix) with ESMTPSA id 94FA794DC957; Wed, 4 Sep 2019 07:05:56 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: Peter Maydell Date: Wed, 4 Sep 2019 09:05:02 +0200 Message-Id: <20190904070506.1052-7-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190904070506.1052-1-clg@kaod.org> References: <20190904070506.1052-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 7087258442873342737 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduvddrudejgedgudduvdcutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.105.50.32 Subject: [Qemu-devel] [PATCH 06/10] aspeed/smc: Add DMA calibration settings X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jeffery , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-arm@nongnu.org, qemu-devel@nongnu.org, Joel Stanley Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" When doing calibration, the SPI clock rate in the CE0 Control Register and the read delay cycles in the Read Timing Compensation Register are set using bit[11:4] of the DMA Control Register. Signed-off-by: C=C3=A9dric Le Goater Acked-by: Joel Stanley Reviewed-by: Peter Maydell --- hw/ssi/aspeed_smc.c | 64 ++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 63 insertions(+), 1 deletion(-) diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index c1a45c10dc14..7a0cd7607fd0 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -77,6 +77,10 @@ #define CTRL_CMD_MASK 0xff #define CTRL_DUMMY_HIGH_SHIFT 14 #define CTRL_AST2400_SPI_4BYTE (1 << 13) +#define CE_CTRL_CLOCK_FREQ_SHIFT 8 +#define CE_CTRL_CLOCK_FREQ_MASK 0xf +#define CE_CTRL_CLOCK_FREQ(div) \ + (((div) & CE_CTRL_CLOCK_FREQ_MASK) << CE_CTRL_CLOCK_FREQ_SHIFT) #define CTRL_DUMMY_LOW_SHIFT 6 /* 2 bits [7:6] */ #define CTRL_CE_STOP_ACTIVE (1 << 2) #define CTRL_CMD_MODE_MASK 0x3 @@ -112,7 +116,7 @@ #define DMA_CTRL_DELAY_SHIFT 8 #define DMA_CTRL_FREQ_MASK 0xf #define DMA_CTRL_FREQ_SHIFT 4 -#define DMA_CTRL_MODE (1 << 3) +#define DMA_CTRL_CALIB (1 << 3) #define DMA_CTRL_CKSUM (1 << 2) #define DMA_CTRL_WRITE (1 << 1) #define DMA_CTRL_ENABLE (1 << 0) @@ -811,6 +815,60 @@ static uint64_t aspeed_smc_read(void *opaque, hwaddr a= ddr, unsigned int size) } } =20 +static uint8_t aspeed_smc_hclk_divisor(uint8_t hclk_mask) +{ + /* HCLK/1 .. HCLK/16 */ + const uint8_t hclk_divisors[] =3D { + 15, 7, 14, 6, 13, 5, 12, 4, 11, 3, 10, 2, 9, 1, 8, 0 + }; + int i; + + for (i =3D 0; i < ARRAY_SIZE(hclk_divisors); i++) { + if (hclk_mask =3D=3D hclk_divisors[i]) { + return i + 1; + } + } + + qemu_log_mask(LOG_GUEST_ERROR, "invalid HCLK mask %x", hclk_mask); + return 0; +} + +/* + * When doing calibration, the SPI clock rate in the CE0 Control + * Register and the read delay cycles in the Read Timing Compensation + * Register are set using bit[11:4] of the DMA Control Register. + */ +static void aspeed_smc_dma_calibration(AspeedSMCState *s) +{ + uint8_t delay =3D + (s->regs[R_DMA_CTRL] >> DMA_CTRL_DELAY_SHIFT) & DMA_CTRL_DELAY_MAS= K; + uint8_t hclk_mask =3D + (s->regs[R_DMA_CTRL] >> DMA_CTRL_FREQ_SHIFT) & DMA_CTRL_FREQ_MASK; + uint8_t hclk_div =3D aspeed_smc_hclk_divisor(hclk_mask); + uint32_t hclk_shift =3D (hclk_div - 1) << 2; + uint8_t cs; + + /* + * The Read Timing Compensation Register values apply to all CS on + * the SPI bus and only HCLK/1 - HCLK/5 can have tunable delays + */ + if (hclk_div && hclk_div < 6) { + s->regs[s->r_timings] &=3D ~(0xf << hclk_shift); + s->regs[s->r_timings] |=3D delay << hclk_shift; + } + + /* + * TODO: compute the CS from the DMA address and the segment + * registers. This is not really a problem for now because the + * Timing Register values apply to all CS and software uses CS0 to + * do calibration. + */ + cs =3D 0; + s->regs[s->r_ctrl0 + cs] &=3D + ~(CE_CTRL_CLOCK_FREQ_MASK << CE_CTRL_CLOCK_FREQ_SHIFT); + s->regs[s->r_ctrl0 + cs] |=3D CE_CTRL_CLOCK_FREQ(hclk_div); +} + /* * Accumulate the result of the reads to provide a checksum that will * be used to validate the read timing settings. @@ -826,6 +884,10 @@ static void aspeed_smc_dma_checksum(AspeedSMCState *s) return; } =20 + if (s->regs[R_DMA_CTRL] & DMA_CTRL_CALIB) { + aspeed_smc_dma_calibration(s); + } + while (s->regs[R_DMA_LEN]) { data =3D address_space_ldl_le(&s->flash_as, s->regs[R_DMA_FLASH_AD= DR], MEMTXATTRS_UNSPECIFIED, &result); --=20 2.21.0