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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id 127sm28089711pfy.56.2019.09.03.09.09.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Sep 2019 09:09:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=aj30MwE6c+ysYeIySie4exO0JlDEZOZ/8NJJ9sSltgs=; b=a1dYEgil7BWMZ0y29yV6Rp7eVYNeM4fbQF+Vs9785ydIr+aWon7aUlt+zK4+un+QLu 8BVRqpxn/QehlMW0BVarr8N3DVTV6KNlCQE9HnTajORgqKCr3fiUi3XfKrPz6CZNccWx I4L2E1PMMrPxpLfcl7Qveck64QyU3EbYrn9Kqw3qi5Q9VLPN/mPwRmoVp/6F1yhHNvKe S6A5lFRvzL2tMZjqtUZzE/OP0IPr9cKqTolsi2yL7fP4SDufTIHRr5hqraG5+SxXe8ne N25o57zDHK8apUzN6vH0VUZy3V8a+b6D5MLTMiajddVSLdKFMYAAvQVpu8y45DSHpyE3 BFEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=aj30MwE6c+ysYeIySie4exO0JlDEZOZ/8NJJ9sSltgs=; b=r/4ITothvfOQXCyP1XApQrj9tng2aF9p89h6cLbcFnRE6Gfj8t5zmOth+xh0EGH5tl 5kZlSWwDlvpVfk9AlIW2NASgPtMjkRyBmVNW61ftXbUOe9DcSMBSDHBfdC6mbF6cvMQQ pbj592wgx9RJXKG8Zo9RZ9wyP/gJOr9mmU+UgeNA5poN8TY/QTEjZTMD+1bKaW/n2HN6 aeYi+UO3g27uueIKsC3084JjzjJnkToGW9ba23DnxlthWBCthYq8TiSOTrzPzu7KXNmA YtxYGgsk6oBQyCFumPJTcJc3I9AJwSPyGvr9RblPBzs8cBsE4fItEnFpcTftKB2PqVtv OitA== X-Gm-Message-State: APjAAAXD+Ei61DwCEK6YpzJboDlCAXFtEkdcfE+4AQzUhNlRCWXdqdRc ooaAqu5WRPjH1pU6gwSNlw6wXiLbLE4= X-Google-Smtp-Source: APXvYqyx9wXXdzWKfBmHAkceJrGBgkKOL0eGYtOCPhfPLtYGndyx0i0E4ORaVJNsnlO4AtVu8dB0LQ== X-Received: by 2002:a65:5a44:: with SMTP id z4mr31136620pgs.41.1567526982852; Tue, 03 Sep 2019 09:09:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 3 Sep 2019 09:08:57 -0700 Message-Id: <20190903160858.5296-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190903160858.5296-1-richard.henderson@linaro.org> References: <20190903160858.5296-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH 35/36] tcg: Make probe_write() return a pointer to the host page X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, David Hildenbrand Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: David Hildenbrand ... similar to tlb_vaddr_to_host(); however, allow access to the host page except when TLB_NOTDIRTY or TLB_MMIO is set. Reviewed-by: Richard Henderson Signed-off-by: David Hildenbrand Message-Id: <20190830100959.26615-2-david@redhat.com> Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 4 ++-- accel/tcg/cputlb.c | 21 ++++++++++++++++----- accel/tcg/user-exec.c | 6 ++++-- 3 files changed, 22 insertions(+), 9 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index cbcc85add3..a7893ed16b 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -310,8 +310,8 @@ static inline void tlb_flush_by_mmuidx_all_cpus_synced(= CPUState *cpu, { } #endif -void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_i= dx, - uintptr_t retaddr); +void *probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_= idx, + uintptr_t retaddr); =20 #define CODE_GEN_ALIGN 16 /* must be >=3D of the size of a icach= e line */ =20 diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 707adf7631..cb969d8372 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1078,11 +1078,11 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env= , target_ulong addr) /* Probe for whether the specified guest write access is permitted. * If it is not permitted then an exception will be taken in the same * way as if this were a real write access (and we will not return). - * Otherwise the function will return, and there will be a valid - * entry in the TLB for this access. + * If the size is 0 or the page requires I/O access, returns NULL; otherwi= se, + * returns the address of the host page similar to tlb_vaddr_to_host(). */ -void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_i= dx, - uintptr_t retaddr) +void *probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_= idx, + uintptr_t retaddr) { uintptr_t index =3D tlb_index(env, mmu_idx, addr); CPUTLBEntry *entry =3D tlb_entry(env, mmu_idx, addr); @@ -1101,12 +1101,23 @@ void probe_write(CPUArchState *env, target_ulong ad= dr, int size, int mmu_idx, tlb_addr =3D tlb_addr_write(entry); } =20 + if (!size) { + return NULL; + } + /* Handle watchpoints. */ - if ((tlb_addr & TLB_WATCHPOINT) && size > 0) { + if (tlb_addr & TLB_WATCHPOINT) { cpu_check_watchpoint(env_cpu(env), addr, size, env_tlb(env)->d[mmu_idx].iotlb[index].attrs, BP_MEM_WRITE, retaddr); } + + if (tlb_addr & (TLB_NOTDIRTY | TLB_MMIO)) { + /* I/O access */ + return NULL; + } + + return (void *)((uintptr_t)addr + entry->addend); } =20 void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr, diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 625c33f893..5720bf8056 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -188,8 +188,8 @@ static inline int handle_cpu_signal(uintptr_t pc, sigin= fo_t *info, g_assert_not_reached(); } =20 -void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_i= dx, - uintptr_t retaddr) +void *probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_= idx, + uintptr_t retaddr) { g_assert(-(addr | TARGET_PAGE_MASK) >=3D size); =20 @@ -202,6 +202,8 @@ void probe_write(CPUArchState *env, target_ulong addr, = int size, int mmu_idx, retaddr); g_assert_not_reached(); } + + return size ? g2h(addr) : NULL; } =20 #if defined(__i386__) --=20 2.17.1