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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id 127sm28089711pfy.56.2019.09.03.09.09.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Sep 2019 09:09:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=hAFFR1M9tMoqLb7qu+zHNLfEFTvh2xfH9lhfPg3h5oQ=; b=YKHpzxGgT9PU/pv3UVuIZAfaZf8vavsPt3VI4XIXHQLSIGiaXNQ6UAfWot5QEPMNSZ 9q6/+sk0exH+ZZ8YmgeggwCBut0oqmdLz9ERSvZVyB5p+B+N1eFA2d71193oGpbd23T2 5s7VcBgMvoCfWhIDT/jI9khOUODY5RCG5UT3JRzPjlvemE4/HrjFlFF25Aip+hDKtVOc mBBkHYZpSLWhVZRiBACe+68FPhtEtu3H+jxKPn9pWDKoM4l3V2WueFU3oF0DbBkxm+La 7zhUESD4QJsl4RcA7HmvQTLOi8jS16rhmb8duWw25e8zskHieCJkku2b0MD/C6XMrCDc UwrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=hAFFR1M9tMoqLb7qu+zHNLfEFTvh2xfH9lhfPg3h5oQ=; b=STFoscjG83VN3FYkNcSZ1yPRE6JJzd56Zu5AWazTsoe5Q0ErXwr1XYjFyjQt67yGeX 0p4gGidZEx9AuonVQ4SPqFpq3UJIdH3DWubgXu5tRnmMelNg9l8U+BvpuBgw7BD0YoDc bfGnvr+teLM0pbTx+31GDmyHgSCUoTH9Tnypz6BUQTUAht7to0bcCtxQvtVYo71aX4RV hs1aDO7SidYwDWEGS9MNJYgTb15ErApEDYQynf2BUywpEQ9sL1YHj5dorDWXGMU9Uf6h rip/k2DT1X0HDAUNJo6pByX6/xqwzQg08UhHa9P67vCymdHj6knPLLeVdEDds07z+HHB hOlw== X-Gm-Message-State: APjAAAUOEFk21YYAioGgYsMMh2DYXtoHDQi5ySdBapGzPCFwuqhIxDJa DNr8U+BBccYTXHmvchmLjDkl8wuKDtE= X-Google-Smtp-Source: APXvYqxp/1ro1BNtyAXvLpoUAhirjGGbjaZoPiAL9XaddI5NAcnguMfDaAktr/52USDFQ3yHOnt8Rw== X-Received: by 2002:a17:902:be0f:: with SMTP id r15mr13495723pls.287.1567526958406; Tue, 03 Sep 2019 09:09:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 3 Sep 2019 09:08:36 -0700 Message-Id: <20190903160858.5296-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190903160858.5296-1-richard.henderson@linaro.org> References: <20190903160858.5296-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH 14/36] memory: Access MemoryRegion with endianness X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Tony Nguyen Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Tony Nguyen Preparation for collapsing the two byte swaps adjust_endianness and handle_bswap into the former. Call memory_region_dispatch_{read|write} with endianness encoded into the "MemOp op" operand. This patch does not change any behaviour as memory_region_dispatch_{read|write} is yet to handle the endianness. Once it does handle endianness, callers with byte swaps can collapse them into adjust_endianness. Reviewed-by: Richard Henderson Signed-off-by: Tony Nguyen Message-Id: <8066ab3eb037c0388dfadfe53c5118429dd1de3a.1566466906.git.tony.n= guyen@bt.com> Signed-off-by: Richard Henderson --- include/exec/memory.h | 3 +++ accel/tcg/cputlb.c | 8 ++++++-- exec.c | 13 +++++++++++-- hw/intc/armv7m_nvic.c | 15 ++++++++------- hw/s390x/s390-pci-inst.c | 6 ++++-- hw/vfio/pci-quirks.c | 5 +++-- hw/virtio/virtio-pci.c | 6 ++++-- memory.c | 18 ++++++++++++++++++ memory_ldst.inc.c | 24 ++++++++++++++++++------ 9 files changed, 75 insertions(+), 23 deletions(-) diff --git a/include/exec/memory.h b/include/exec/memory.h index 192875b080..c4c86a6ff4 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -2211,6 +2211,9 @@ address_space_write_cached(MemoryRegionCache *cache, = hwaddr addr, } } =20 +/* enum device_endian to MemOp. */ +MemOp devend_memop(enum device_endian end); + #endif =20 #endif diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 6c83878f73..f64c6b1c75 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -906,7 +906,8 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEnt= ry *iotlbentry, qemu_mutex_lock_iothread(); locked =3D true; } - r =3D memory_region_dispatch_read(mr, mr_offset, &val, size_memop(size= ), + r =3D memory_region_dispatch_read(mr, mr_offset, &val, + size_memop(size) | MO_TE, iotlbentry->attrs); if (r !=3D MEMTX_OK) { hwaddr physaddr =3D mr_offset + @@ -947,7 +948,8 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry = *iotlbentry, qemu_mutex_lock_iothread(); locked =3D true; } - r =3D memory_region_dispatch_write(mr, mr_offset, val, size_memop(size= ), + r =3D memory_region_dispatch_write(mr, mr_offset, val, + size_memop(size) | MO_TE, iotlbentry->attrs); if (r !=3D MEMTX_OK) { hwaddr physaddr =3D mr_offset + @@ -1305,6 +1307,7 @@ load_helper(CPUArchState *env, target_ulong addr, TCG= MemOpIdx oi, } } =20 + /* TODO: Merge bswap into io_readx -> memory_region_dispatch_read.= */ res =3D io_readx(env, &env_tlb(env)->d[mmu_idx].iotlb[index], mmu_idx, addr, retaddr, access_type, size); return handle_bswap(res, size, big_endian); @@ -1553,6 +1556,7 @@ store_helper(CPUArchState *env, target_ulong addr, ui= nt64_t val, } } =20 + /* TODO: Merge bswap into io_writex -> memory_region_dispatch_writ= e. */ io_writex(env, &env_tlb(env)->d[mmu_idx].iotlb[index], mmu_idx, handle_bswap(val, size, big_endian), addr, retaddr, size); diff --git a/exec.c b/exec.c index cc9697fe1b..e4652c0e75 100644 --- a/exec.c +++ b/exec.c @@ -3364,8 +3364,13 @@ static MemTxResult flatview_write_continue(FlatView = *fv, hwaddr addr, /* XXX: could force current_cpu to NULL to avoid potential bugs */ val =3D ldn_p(buf, l); + /* + * TODO: Merge bswap from ldn_p into memory_region_dispatch_wr= ite + * by using ldn_he_p and dropping MO_TE to get a host-endian v= alue. + */ result |=3D memory_region_dispatch_write(mr, addr1, val, - size_memop(l), attrs); + size_memop(l) | MO_TE, + attrs); } else { /* RAM case */ ptr =3D qemu_ram_ptr_length(mr->ram_block, addr1, &l, false); @@ -3426,8 +3431,12 @@ MemTxResult flatview_read_continue(FlatView *fv, hwa= ddr addr, /* I/O case */ release_lock |=3D prepare_mmio_access(mr); l =3D memory_access_size(mr, l, addr1); + /* + * TODO: Merge bswap from stn_p into memory_region_dispatch_re= ad + * by using stn_he_p and dropping MO_TE to get a host-endian v= alue. + */ result |=3D memory_region_dispatch_read(mr, addr1, &val, - size_memop(l), attrs); + size_memop(l) | MO_TE, a= ttrs); stn_p(buf, l, val); } else { /* RAM case */ diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 7220940133..8e93e51e81 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -2349,8 +2349,8 @@ static MemTxResult nvic_sysreg_ns_write(void *opaque,= hwaddr addr, if (attrs.secure) { /* S accesses to the alias act like NS accesses to the real region= */ attrs.secure =3D 0; - return memory_region_dispatch_write(mr, addr, value, size_memop(si= ze), - attrs); + return memory_region_dispatch_write(mr, addr, value, + size_memop(size) | MO_TE, attr= s); } else { /* NS attrs are RAZ/WI for privileged, and BusFault for user */ if (attrs.user) { @@ -2369,8 +2369,8 @@ static MemTxResult nvic_sysreg_ns_read(void *opaque, = hwaddr addr, if (attrs.secure) { /* S accesses to the alias act like NS accesses to the real region= */ attrs.secure =3D 0; - return memory_region_dispatch_read(mr, addr, data, size_memop(size= ), - attrs); + return memory_region_dispatch_read(mr, addr, data, + size_memop(size) | MO_TE, attrs= ); } else { /* NS attrs are RAZ/WI for privileged, and BusFault for user */ if (attrs.user) { @@ -2396,8 +2396,8 @@ static MemTxResult nvic_systick_write(void *opaque, h= waddr addr, =20 /* Direct the access to the correct systick */ mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]= ), 0); - return memory_region_dispatch_write(mr, addr, value, size_memop(size), - attrs); + return memory_region_dispatch_write(mr, addr, value, + size_memop(size) | MO_TE, attrs); } =20 static MemTxResult nvic_systick_read(void *opaque, hwaddr addr, @@ -2409,7 +2409,8 @@ static MemTxResult nvic_systick_read(void *opaque, hw= addr addr, =20 /* Direct the access to the correct systick */ mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]= ), 0); - return memory_region_dispatch_read(mr, addr, data, size_memop(size), a= ttrs); + return memory_region_dispatch_read(mr, addr, data, size_memop(size) | = MO_TE, + attrs); } =20 static const MemoryRegionOps nvic_systick_ops =3D { diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c index 0e92a372ca..4b3bd4a804 100644 --- a/hw/s390x/s390-pci-inst.c +++ b/hw/s390x/s390-pci-inst.c @@ -373,7 +373,8 @@ static MemTxResult zpci_read_bar(S390PCIBusDevice *pbde= v, uint8_t pcias, mr =3D pbdev->pdev->io_regions[pcias].memory; mr =3D s390_get_subregion(mr, offset, len); offset -=3D mr->addr; - return memory_region_dispatch_read(mr, offset, data, size_memop(len), + return memory_region_dispatch_read(mr, offset, data, + size_memop(len) | MO_BE, MEMTXATTRS_UNSPECIFIED); } =20 @@ -472,7 +473,8 @@ static MemTxResult zpci_write_bar(S390PCIBusDevice *pbd= ev, uint8_t pcias, mr =3D pbdev->pdev->io_regions[pcias].memory; mr =3D s390_get_subregion(mr, offset, len); offset -=3D mr->addr; - return memory_region_dispatch_write(mr, offset, data, size_memop(len), + return memory_region_dispatch_write(mr, offset, data, + size_memop(len) | MO_BE, MEMTXATTRS_UNSPECIFIED); } =20 diff --git a/hw/vfio/pci-quirks.c b/hw/vfio/pci-quirks.c index a4e1d2abb5..136f3a9ad6 100644 --- a/hw/vfio/pci-quirks.c +++ b/hw/vfio/pci-quirks.c @@ -1074,7 +1074,8 @@ static void vfio_rtl8168_quirk_address_write(void *op= aque, hwaddr addr, =20 /* Write to the proper guest MSI-X table instead */ memory_region_dispatch_write(&vdev->pdev.msix_table_mmio, - offset, val, size_memop(size), + offset, val, + size_memop(size) | MO_LE, MEMTXATTRS_UNSPECIFIED); } return; /* Do not write guest MSI-X data to hardware */ @@ -1105,7 +1106,7 @@ static uint64_t vfio_rtl8168_quirk_data_read(void *op= aque, if (rtl->enabled && (vdev->pdev.cap_present & QEMU_PCI_CAP_MSIX)) { hwaddr offset =3D rtl->addr & 0xfff; memory_region_dispatch_read(&vdev->pdev.msix_table_mmio, offset, - &data, size_memop(size), + &data, size_memop(size) | MO_LE, MEMTXATTRS_UNSPECIFIED); trace_vfio_quirk_rtl8168_msix_read(vdev->vbasedev.name, offset, da= ta); } diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index 82c5e87a44..d89a85bb33 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virtio-pci.c @@ -553,7 +553,8 @@ void virtio_address_space_write(VirtIOPCIProxy *proxy, = hwaddr addr, /* As length is under guest control, handle illegal values. */ return; } - memory_region_dispatch_write(mr, addr, val, size_memop(len), + /* TODO: Merge bswap from cpu_to_leXX into memory_region_dispatch_writ= e. */ + memory_region_dispatch_write(mr, addr, val, size_memop(len) | MO_LE, MEMTXATTRS_UNSPECIFIED); } =20 @@ -577,7 +578,8 @@ virtio_address_space_read(VirtIOPCIProxy *proxy, hwaddr= addr, /* Make sure caller aligned buf properly */ assert(!(((uintptr_t)buf) & (len - 1))); =20 - memory_region_dispatch_read(mr, addr, &val, size_memop(len), + /* TODO: Merge bswap from leXX_to_cpu into memory_region_dispatch_read= . */ + memory_region_dispatch_read(mr, addr, &val, size_memop(len) | MO_LE, MEMTXATTRS_UNSPECIFIED); switch (len) { case 1: diff --git a/memory.c b/memory.c index 3d87908784..d72143a18f 100644 --- a/memory.c +++ b/memory.c @@ -3285,3 +3285,21 @@ static void memory_register_types(void) } =20 type_init(memory_register_types) + +MemOp devend_memop(enum device_endian end) +{ + static MemOp conv[] =3D { + [DEVICE_LITTLE_ENDIAN] =3D MO_LE, + [DEVICE_BIG_ENDIAN] =3D MO_BE, + [DEVICE_NATIVE_ENDIAN] =3D MO_TE, + [DEVICE_HOST_ENDIAN] =3D 0, + }; + switch (end) { + case DEVICE_LITTLE_ENDIAN: + case DEVICE_BIG_ENDIAN: + case DEVICE_NATIVE_ENDIAN: + return conv[end]; + default: + g_assert_not_reached(); + } +} diff --git a/memory_ldst.inc.c b/memory_ldst.inc.c index de658c40c4..809a7e8389 100644 --- a/memory_ldst.inc.c +++ b/memory_ldst.inc.c @@ -38,7 +38,9 @@ static inline uint32_t glue(address_space_ldl_internal, S= UFFIX)(ARG1_DECL, release_lock |=3D prepare_mmio_access(mr); =20 /* I/O case */ - r =3D memory_region_dispatch_read(mr, addr1, &val, MO_32, attrs); + /* TODO: Merge bswap32 into memory_region_dispatch_read. */ + r =3D memory_region_dispatch_read(mr, addr1, &val, + MO_32 | devend_memop(endian), attr= s); #if defined(TARGET_WORDS_BIGENDIAN) if (endian =3D=3D DEVICE_LITTLE_ENDIAN) { val =3D bswap32(val); @@ -114,7 +116,9 @@ static inline uint64_t glue(address_space_ldq_internal,= SUFFIX)(ARG1_DECL, release_lock |=3D prepare_mmio_access(mr); =20 /* I/O case */ - r =3D memory_region_dispatch_read(mr, addr1, &val, MO_64, attrs); + /* TODO: Merge bswap64 into memory_region_dispatch_read. */ + r =3D memory_region_dispatch_read(mr, addr1, &val, + MO_64 | devend_memop(endian), attr= s); #if defined(TARGET_WORDS_BIGENDIAN) if (endian =3D=3D DEVICE_LITTLE_ENDIAN) { val =3D bswap64(val); @@ -224,7 +228,9 @@ static inline uint32_t glue(address_space_lduw_internal= , SUFFIX)(ARG1_DECL, release_lock |=3D prepare_mmio_access(mr); =20 /* I/O case */ - r =3D memory_region_dispatch_read(mr, addr1, &val, MO_16, attrs); + /* TODO: Merge bswap16 into memory_region_dispatch_read. */ + r =3D memory_region_dispatch_read(mr, addr1, &val, + MO_16 | devend_memop(endian), attr= s); #if defined(TARGET_WORDS_BIGENDIAN) if (endian =3D=3D DEVICE_LITTLE_ENDIAN) { val =3D bswap16(val); @@ -346,7 +352,9 @@ static inline void glue(address_space_stl_internal, SUF= FIX)(ARG1_DECL, val =3D bswap32(val); } #endif - r =3D memory_region_dispatch_write(mr, addr1, val, MO_32, attrs); + /* TODO: Merge bswap32 into memory_region_dispatch_write. */ + r =3D memory_region_dispatch_write(mr, addr1, val, + MO_32 | devend_memop(endian), att= rs); } else { /* RAM case */ ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); @@ -451,7 +459,9 @@ static inline void glue(address_space_stw_internal, SUF= FIX)(ARG1_DECL, val =3D bswap16(val); } #endif - r =3D memory_region_dispatch_write(mr, addr1, val, MO_16, attrs); + /* TODO: Merge bswap16 into memory_region_dispatch_write. */ + r =3D memory_region_dispatch_write(mr, addr1, val, + MO_16 | devend_memop(endian), att= rs); } else { /* RAM case */ ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); @@ -524,7 +534,9 @@ static void glue(address_space_stq_internal, SUFFIX)(AR= G1_DECL, val =3D bswap64(val); } #endif - r =3D memory_region_dispatch_write(mr, addr1, val, MO_64, attrs); + /* TODO: Merge bswap64 into memory_region_dispatch_write. */ + r =3D memory_region_dispatch_write(mr, addr1, val, + MO_64 | devend_memop(endian), att= rs); } else { /* RAM case */ ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); --=20 2.17.1