From nobody Wed Nov 12 01:52:18 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1567526111; cv=none; d=zoho.com; s=zohoarc; b=ImE7WRUhP4ILy7DWP1ZLgNTbAItuiuq4gPRD11T1bbkNOd/h4apTNaCG1a6JcjvLU31JCcR8SZpTEjg+NiXHMNpM88qwELEYcVha8GymBhsw+RKNiYpyIhfGPRbOB3yrjScgcpt/mZnwkVTsPkcZasLSpXF2CdpW2YWyK+G+E7A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567526111; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=qj+qIf1GZICziwhwaXKhUbXpA6vXfaT3SXyWmqqosd8=; b=C1vEp4A/A2TajudDQ7CnE1BfdeoCYNdnQQ9Pywan0/GMRnpQm0HAPXOiPI72u+kQJKi4sIKWJb2ydamov0ngF5lvxnbNywIm98xQRUifsQOShl9Rke48bxJCAFXGH4f8nbnc1pWlqjRP24eij51D6yz6eonXHjey8FnCbjGnmvg= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 15675261111281017.6133819161101; Tue, 3 Sep 2019 08:55:11 -0700 (PDT) Received: from localhost ([::1]:47946 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5B9B-0003xD-Dp for importer@patchew.org; Tue, 03 Sep 2019 11:55:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33013) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5B2h-0004sj-9z for qemu-devel@nongnu.org; Tue, 03 Sep 2019 11:48:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5B2f-0005Wa-UV for qemu-devel@nongnu.org; Tue, 03 Sep 2019 11:48:27 -0400 Received: from mx1.redhat.com ([209.132.183.28]:59116) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1i5B2a-0005Pl-Aa; Tue, 03 Sep 2019 11:48:21 -0400 Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 5B3E23082B6D; Tue, 3 Sep 2019 15:48:18 +0000 (UTC) Received: from thuth.com (ovpn-117-51.ams2.redhat.com [10.36.117.51]) by smtp.corp.redhat.com (Postfix) with ESMTP id 4D06D19D7A; Tue, 3 Sep 2019 15:48:17 +0000 (UTC) From: Thomas Huth To: qemu-devel@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Tue, 3 Sep 2019 17:48:08 +0200 Message-Id: <20190903154810.27365-2-thuth@redhat.com> In-Reply-To: <20190903154810.27365-1-thuth@redhat.com> References: <20190903154810.27365-1-thuth@redhat.com> X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.45]); Tue, 03 Sep 2019 15:48:18 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [RFC PATCH 1/3] target/arm: Make cpu_register() and set_feature() available for other files X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Move the common set_feature() and unset_feature() functions from cpu.c and cpu64.c to cpu.h, and make cpu_register() (renamed to arm_cpu_register()) available from there, too, so we can register CPUs also from other files in the future. Signed-off-by: Thomas Huth Reviewed-by: Richard Henderson --- target/arm/cpu.c | 20 ++------------------ target/arm/cpu.h | 18 ++++++++++++++++++ target/arm/cpu64.c | 16 ---------------- 3 files changed, 20 insertions(+), 34 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 2399c14471..f1f9eecdc8 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -614,16 +614,6 @@ static bool arm_cpu_virtio_is_big_endian(CPUState *cs) =20 #endif =20 -static inline void set_feature(CPUARMState *env, int feature) -{ - env->features |=3D 1ULL << feature; -} - -static inline void unset_feature(CPUARMState *env, int feature) -{ - env->features &=3D ~(1ULL << feature); -} - static int print_insn_thumb1(bfd_vma pc, disassemble_info *info) { @@ -2515,12 +2505,6 @@ static void arm_max_initfn(Object *obj) =20 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ =20 -struct ARMCPUInfo { - const char *name; - void (*initfn)(Object *obj); - void (*class_init)(ObjectClass *oc, void *data); -}; - static const ARMCPUInfo arm_cpus[] =3D { #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) { .name =3D "arm926", .initfn =3D arm926_initfn }, @@ -2681,7 +2665,7 @@ static void cpu_register_class_init(ObjectClass *oc, = void *data) acc->info =3D data; } =20 -static void cpu_register(const ARMCPUInfo *info) +void arm_cpu_register(const ARMCPUInfo *info) { TypeInfo type_info =3D { .parent =3D TYPE_ARM_CPU, @@ -2722,7 +2706,7 @@ static void arm_cpu_register_types(void) type_register_static(&idau_interface_type_info); =20 while (info->name) { - cpu_register(info); + arm_cpu_register(info); info++; } =20 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0981303170..c5007edf1f 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3600,4 +3600,22 @@ static inline bool isar_feature_aa64_bti(const ARMIS= ARegisters *id) #define cpu_isar_feature(name, cpu) \ ({ ARMCPU *cpu_ =3D (cpu); isar_feature_##name(&cpu_->isar); }) =20 +static inline void set_feature(CPUARMState *env, int feature) +{ + env->features |=3D 1ULL << feature; +} + +static inline void unset_feature(CPUARMState *env, int feature) +{ + env->features &=3D ~(1ULL << feature); +} + +struct ARMCPUInfo { + const char *name; + void (*initfn)(Object *obj); + void (*class_init)(ObjectClass *oc, void *data); +}; + +void arm_cpu_register(const ARMCPUInfo *info); + #endif diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index d7f5bf610a..869cec13ca 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -29,16 +29,6 @@ #include "kvm_arm.h" #include "qapi/visitor.h" =20 -static inline void set_feature(CPUARMState *env, int feature) -{ - env->features |=3D 1ULL << feature; -} - -static inline void unset_feature(CPUARMState *env, int feature) -{ - env->features &=3D ~(1ULL << feature); -} - #ifndef CONFIG_USER_ONLY static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *= ri) { @@ -396,12 +386,6 @@ static void aarch64_max_initfn(Object *obj) } } =20 -struct ARMCPUInfo { - const char *name; - void (*initfn)(Object *obj); - void (*class_init)(ObjectClass *oc, void *data); -}; - static const ARMCPUInfo aarch64_cpus[] =3D { { .name =3D "cortex-a57", .initfn =3D aarch64_a57_initfn }, { .name =3D "cortex-a53", .initfn =3D aarch64_a53_initfn }, --=20 2.18.1 From nobody Wed Nov 12 01:52:18 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1567527499; cv=none; d=zoho.com; s=zohoarc; b=IsTb+yztrgkj6w6nPLoY2pAoMyUSEHvbBShP3X17RCZ5Iu1WFicCtHiZbQM1QioL5ivWPc75ubZ0XBUojS3vUE2X3kuUQIpQvJKw75DhKAyxso0b7qGrIqj3spuxkvZHIOi9vLuRpx+MGfDEsoOd4bzRna4+EGLdjoWweaikZbg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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Tue, 3 Sep 2019 15:48:18 +0000 (UTC) From: Thomas Huth To: qemu-devel@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Tue, 3 Sep 2019 17:48:09 +0200 Message-Id: <20190903154810.27365-3-thuth@redhat.com> In-Reply-To: <20190903154810.27365-1-thuth@redhat.com> References: <20190903154810.27365-1-thuth@redhat.com> X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.43]); Tue, 03 Sep 2019 15:48:20 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [RFC PATCH 2/3] target/arm: Move cortex-m related functions to m_helper.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The next patch is going to make m_helper.c depend on CONFIG_ARM_V7M, so the cortex-m related CPUs won't be usable anymore if CONFIG_ARM_V7M is not enabled. Thus move the functions that create those CPUs into this file, too, so that we do not have unusable CPUs in the binary anymore. Signed-off-by: Thomas Huth --- target/arm/cpu.c | 146 ------------------------------------- target/arm/m_helper.c | 164 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 164 insertions(+), 146 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index f1f9eecdc8..d5f0d4af61 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -462,31 +462,6 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrup= t_request) return ret; } =20 -#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) -static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) -{ - CPUClass *cc =3D CPU_GET_CLASS(cs); - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - bool ret =3D false; - - /* ARMv7-M interrupt masking works differently than -A or -R. - * There is no FIQ/IRQ distinction. Instead of I and F bits - * masking FIQ and IRQ interrupts, an exception is taken only - * if it is higher priority than the current execution priority - * (which depends on state like BASEPRI, FAULTMASK and the - * currently active exception). - */ - if (interrupt_request & CPU_INTERRUPT_HARD - && (armv7m_nvic_can_take_pending_exception(env->nvic))) { - cs->exception_index =3D EXCP_IRQ; - cc->do_interrupt(cs); - ret =3D true; - } - return ret; -} -#endif - void arm_cpu_update_virq(ARMCPU *cpu) { /* @@ -1881,119 +1856,6 @@ static void arm11mpcore_initfn(Object *obj) cpu->reset_auxcr =3D 1; } =20 -static void cortex_m0_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - set_feature(&cpu->env, ARM_FEATURE_V6); - set_feature(&cpu->env, ARM_FEATURE_M); - - cpu->midr =3D 0x410cc200; -} - -static void cortex_m3_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - set_feature(&cpu->env, ARM_FEATURE_V7); - set_feature(&cpu->env, ARM_FEATURE_M); - set_feature(&cpu->env, ARM_FEATURE_M_MAIN); - cpu->midr =3D 0x410fc231; - cpu->pmsav7_dregion =3D 8; - cpu->id_pfr0 =3D 0x00000030; - cpu->id_pfr1 =3D 0x00000200; - cpu->id_dfr0 =3D 0x00100000; - cpu->id_afr0 =3D 0x00000000; - cpu->id_mmfr0 =3D 0x00000030; - cpu->id_mmfr1 =3D 0x00000000; - cpu->id_mmfr2 =3D 0x00000000; - cpu->id_mmfr3 =3D 0x00000000; - cpu->isar.id_isar0 =3D 0x01141110; - cpu->isar.id_isar1 =3D 0x02111000; - cpu->isar.id_isar2 =3D 0x21112231; - cpu->isar.id_isar3 =3D 0x01111110; - cpu->isar.id_isar4 =3D 0x01310102; - cpu->isar.id_isar5 =3D 0x00000000; - cpu->isar.id_isar6 =3D 0x00000000; -} - -static void cortex_m4_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - set_feature(&cpu->env, ARM_FEATURE_V7); - set_feature(&cpu->env, ARM_FEATURE_M); - set_feature(&cpu->env, ARM_FEATURE_M_MAIN); - set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); - set_feature(&cpu->env, ARM_FEATURE_VFP4); - cpu->midr =3D 0x410fc240; /* r0p0 */ - cpu->pmsav7_dregion =3D 8; - cpu->isar.mvfr0 =3D 0x10110021; - cpu->isar.mvfr1 =3D 0x11000011; - cpu->isar.mvfr2 =3D 0x00000000; - cpu->id_pfr0 =3D 0x00000030; - cpu->id_pfr1 =3D 0x00000200; - cpu->id_dfr0 =3D 0x00100000; - cpu->id_afr0 =3D 0x00000000; - cpu->id_mmfr0 =3D 0x00000030; - cpu->id_mmfr1 =3D 0x00000000; - cpu->id_mmfr2 =3D 0x00000000; - cpu->id_mmfr3 =3D 0x00000000; - cpu->isar.id_isar0 =3D 0x01141110; - cpu->isar.id_isar1 =3D 0x02111000; - cpu->isar.id_isar2 =3D 0x21112231; - cpu->isar.id_isar3 =3D 0x01111110; - cpu->isar.id_isar4 =3D 0x01310102; - cpu->isar.id_isar5 =3D 0x00000000; - cpu->isar.id_isar6 =3D 0x00000000; -} - -static void cortex_m33_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - set_feature(&cpu->env, ARM_FEATURE_V8); - set_feature(&cpu->env, ARM_FEATURE_M); - set_feature(&cpu->env, ARM_FEATURE_M_MAIN); - set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); - set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); - set_feature(&cpu->env, ARM_FEATURE_VFP4); - cpu->midr =3D 0x410fd213; /* r0p3 */ - cpu->pmsav7_dregion =3D 16; - cpu->sau_sregion =3D 8; - cpu->isar.mvfr0 =3D 0x10110021; - cpu->isar.mvfr1 =3D 0x11000011; - cpu->isar.mvfr2 =3D 0x00000040; - cpu->id_pfr0 =3D 0x00000030; - cpu->id_pfr1 =3D 0x00000210; - cpu->id_dfr0 =3D 0x00200000; - cpu->id_afr0 =3D 0x00000000; - cpu->id_mmfr0 =3D 0x00101F40; - cpu->id_mmfr1 =3D 0x00000000; - cpu->id_mmfr2 =3D 0x01000000; - cpu->id_mmfr3 =3D 0x00000000; - cpu->isar.id_isar0 =3D 0x01101110; - cpu->isar.id_isar1 =3D 0x02212000; - cpu->isar.id_isar2 =3D 0x20232232; - cpu->isar.id_isar3 =3D 0x01111131; - cpu->isar.id_isar4 =3D 0x01310132; - cpu->isar.id_isar5 =3D 0x00000000; - cpu->isar.id_isar6 =3D 0x00000000; - cpu->clidr =3D 0x00000000; - cpu->ctr =3D 0x8000c000; -} - -static void arm_v7m_class_init(ObjectClass *oc, void *data) -{ - ARMCPUClass *acc =3D ARM_CPU_CLASS(oc); - CPUClass *cc =3D CPU_CLASS(oc); - - acc->info =3D data; -#ifndef CONFIG_USER_ONLY - cc->do_interrupt =3D arm_v7m_cpu_do_interrupt; -#endif - - cc->cpu_exec_interrupt =3D arm_v7m_cpu_exec_interrupt; -} - static const ARMCPRegInfo cortexr5_cp_reginfo[] =3D { /* Dummy the TCM region regs for the moment */ { .name =3D "ATCM", .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 1, .= opc2 =3D 0, @@ -2518,14 +2380,6 @@ static const ARMCPUInfo arm_cpus[] =3D { { .name =3D "arm1136", .initfn =3D arm1136_initfn }, { .name =3D "arm1176", .initfn =3D arm1176_initfn }, { .name =3D "arm11mpcore", .initfn =3D arm11mpcore_initfn }, - { .name =3D "cortex-m0", .initfn =3D cortex_m0_initfn, - .class_init =3D arm_v7m_class_init }, - { .name =3D "cortex-m3", .initfn =3D cortex_m3_initfn, - .class_init =3D arm_v7m_class_init }, - { .name =3D "cortex-m4", .initfn =3D cortex_m4_initfn, - .class_init =3D arm_v7m_class_init }, - { .name =3D "cortex-m33", .initfn =3D cortex_m33_initfn, - .class_init =3D arm_v7m_class_init }, { .name =3D "cortex-r5", .initfn =3D cortex_r5_initfn }, { .name =3D "cortex-r5f", .initfn =3D cortex_r5f_initfn }, { .name =3D "cortex-a7", .initfn =3D cortex_a7_initfn }, diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 884d35d2b0..9fd675b437 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -2691,3 +2691,167 @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState = *env, bool secstate) =20 return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv); } + +#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) + +static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ + CPUClass *cc =3D CPU_GET_CLASS(cs); + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + bool ret =3D false; + + /* ARMv7-M interrupt masking works differently than -A or -R. + * There is no FIQ/IRQ distinction. Instead of I and F bits + * masking FIQ and IRQ interrupts, an exception is taken only + * if it is higher priority than the current execution priority + * (which depends on state like BASEPRI, FAULTMASK and the + * currently active exception). + */ + if (interrupt_request & CPU_INTERRUPT_HARD + && (armv7m_nvic_can_take_pending_exception(env->nvic))) { + cs->exception_index =3D EXCP_IRQ; + cc->do_interrupt(cs); + ret =3D true; + } + return ret; +} + +static void cortex_m0_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + set_feature(&cpu->env, ARM_FEATURE_V6); + set_feature(&cpu->env, ARM_FEATURE_M); + + cpu->midr =3D 0x410cc200; +} + +static void cortex_m3_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + set_feature(&cpu->env, ARM_FEATURE_V7); + set_feature(&cpu->env, ARM_FEATURE_M); + set_feature(&cpu->env, ARM_FEATURE_M_MAIN); + cpu->midr =3D 0x410fc231; + cpu->pmsav7_dregion =3D 8; + cpu->id_pfr0 =3D 0x00000030; + cpu->id_pfr1 =3D 0x00000200; + cpu->id_dfr0 =3D 0x00100000; + cpu->id_afr0 =3D 0x00000000; + cpu->id_mmfr0 =3D 0x00000030; + cpu->id_mmfr1 =3D 0x00000000; + cpu->id_mmfr2 =3D 0x00000000; + cpu->id_mmfr3 =3D 0x00000000; + cpu->isar.id_isar0 =3D 0x01141110; + cpu->isar.id_isar1 =3D 0x02111000; + cpu->isar.id_isar2 =3D 0x21112231; + cpu->isar.id_isar3 =3D 0x01111110; + cpu->isar.id_isar4 =3D 0x01310102; + cpu->isar.id_isar5 =3D 0x00000000; + cpu->isar.id_isar6 =3D 0x00000000; +} + +static void cortex_m4_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + set_feature(&cpu->env, ARM_FEATURE_V7); + set_feature(&cpu->env, ARM_FEATURE_M); + set_feature(&cpu->env, ARM_FEATURE_M_MAIN); + set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); + set_feature(&cpu->env, ARM_FEATURE_VFP4); + cpu->midr =3D 0x410fc240; /* r0p0 */ + cpu->pmsav7_dregion =3D 8; + cpu->isar.mvfr0 =3D 0x10110021; + cpu->isar.mvfr1 =3D 0x11000011; + cpu->isar.mvfr2 =3D 0x00000000; + cpu->id_pfr0 =3D 0x00000030; + cpu->id_pfr1 =3D 0x00000200; + cpu->id_dfr0 =3D 0x00100000; + cpu->id_afr0 =3D 0x00000000; + cpu->id_mmfr0 =3D 0x00000030; + cpu->id_mmfr1 =3D 0x00000000; + cpu->id_mmfr2 =3D 0x00000000; + cpu->id_mmfr3 =3D 0x00000000; + cpu->isar.id_isar0 =3D 0x01141110; + cpu->isar.id_isar1 =3D 0x02111000; + cpu->isar.id_isar2 =3D 0x21112231; + cpu->isar.id_isar3 =3D 0x01111110; + cpu->isar.id_isar4 =3D 0x01310102; + cpu->isar.id_isar5 =3D 0x00000000; + cpu->isar.id_isar6 =3D 0x00000000; +} + +static void cortex_m33_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_M); + set_feature(&cpu->env, ARM_FEATURE_M_MAIN); + set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); + set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); + set_feature(&cpu->env, ARM_FEATURE_VFP4); + cpu->midr =3D 0x410fd213; /* r0p3 */ + cpu->pmsav7_dregion =3D 16; + cpu->sau_sregion =3D 8; + cpu->isar.mvfr0 =3D 0x10110021; + cpu->isar.mvfr1 =3D 0x11000011; + cpu->isar.mvfr2 =3D 0x00000040; + cpu->id_pfr0 =3D 0x00000030; + cpu->id_pfr1 =3D 0x00000210; + cpu->id_dfr0 =3D 0x00200000; + cpu->id_afr0 =3D 0x00000000; + cpu->id_mmfr0 =3D 0x00101F40; + cpu->id_mmfr1 =3D 0x00000000; + cpu->id_mmfr2 =3D 0x01000000; + cpu->id_mmfr3 =3D 0x00000000; + cpu->isar.id_isar0 =3D 0x01101110; + cpu->isar.id_isar1 =3D 0x02212000; + cpu->isar.id_isar2 =3D 0x20232232; + cpu->isar.id_isar3 =3D 0x01111131; + cpu->isar.id_isar4 =3D 0x01310132; + cpu->isar.id_isar5 =3D 0x00000000; + cpu->isar.id_isar6 =3D 0x00000000; + cpu->clidr =3D 0x00000000; + cpu->ctr =3D 0x8000c000; +} + +static void arm_v7m_class_init(ObjectClass *oc, void *data) +{ + ARMCPUClass *acc =3D ARM_CPU_CLASS(oc); + CPUClass *cc =3D CPU_CLASS(oc); + + acc->info =3D data; +#ifndef CONFIG_USER_ONLY + cc->do_interrupt =3D arm_v7m_cpu_do_interrupt; +#endif + + cc->cpu_exec_interrupt =3D arm_v7m_cpu_exec_interrupt; +} + +static const ARMCPUInfo arm_v7m_cpus[] =3D { + { .name =3D "cortex-m0", .initfn =3D cortex_m0_initfn, + .class_init =3D arm_v7m_class_init }, + { .name =3D "cortex-m3", .initfn =3D cortex_m3_initfn, + .class_init =3D arm_v7m_class_init }, + { .name =3D "cortex-m4", .initfn =3D cortex_m4_initfn, + .class_init =3D arm_v7m_class_init }, + { .name =3D "cortex-m33", .initfn =3D cortex_m33_initfn, + .class_init =3D arm_v7m_class_init }, + { .name =3D NULL } +}; + +static void arm_v7m_cpu_register_types(void) +{ + const ARMCPUInfo *info =3D arm_v7m_cpus; + + while (info->name) { + arm_cpu_register(info); + info++; + } +} + +type_init(arm_v7m_cpu_register_types) + +#endif --=20 2.18.1 From nobody Wed Nov 12 01:52:18 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1567526867; cv=none; d=zoho.com; s=zohoarc; b=V6MSUP1n8QaQGex9OQ/XZhuhqUVa4LsWHN+FKLkc3tBB2oaZr7Lv3pMrC0JOpMnerNGZhFZkKslVy9i616hlCLPnmKqKCJnPuwuWC1Ln7J9WzPMhOHwvTdc64bnDZYX2BorK046DawAkjxDvtBOO2QOZKG8DmZROPEG5gmgeDjc= ARC-Message-Signature: i=1; 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Tue, 3 Sep 2019 15:48:20 +0000 (UTC) From: Thomas Huth To: qemu-devel@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Tue, 3 Sep 2019 17:48:10 +0200 Message-Id: <20190903154810.27365-4-thuth@redhat.com> In-Reply-To: <20190903154810.27365-1-thuth@redhat.com> References: <20190903154810.27365-1-thuth@redhat.com> X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.44]); Tue, 03 Sep 2019 15:48:21 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [RFC PATCH 3/3] target/arm: Make m_helper.c optional via CONFIG_ARM_V7M X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We've already got the CONFIG_ARM_V7M switch, but it currently can not be disabled yet. The m_helper.c code should not be compiled into the binary if the switch is not enabled. We also have to provide some stubs in a separate file to make sure that we still can link the other code without CONFIG_ARM_V7M. Signed-off-by: Thomas Huth --- target/arm/Makefile.objs | 3 +- target/arm/m_helper-stub.c | 58 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 60 insertions(+), 1 deletion(-) create mode 100644 target/arm/m_helper-stub.c diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index 5cafc1eb6c..225e7a70a9 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -36,7 +36,8 @@ obj-y +=3D tlb_helper.o debug_helper.o obj-y +=3D translate.o op_helper.o obj-y +=3D crypto_helper.o obj-y +=3D iwmmxt_helper.o vec_helper.o neon_helper.o -obj-y +=3D m_helper.o +obj-$(CONFIG_ARM_V7M) +=3D m_helper.o +obj-$(call lnot,$(CONFIG_ARM_V7M)) +=3D m_helper-stub.o =20 obj-$(CONFIG_SOFTMMU) +=3D psci.o =20 diff --git a/target/arm/m_helper-stub.c b/target/arm/m_helper-stub.c new file mode 100644 index 0000000000..8ec9de0fb6 --- /dev/null +++ b/target/arm/m_helper-stub.c @@ -0,0 +1,58 @@ +/* + * ARM V7M related stubs. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#include "qemu/osdep.h" +#include "cpu.h" +#include "exec/helper-proto.h" + +void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest) +{ + abort(); +} + +void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest) +{ + abort(); +} + +uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) +{ + abort(); +} + +void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) +{ + abort(); +} + +uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) +{ + abort(); +} + +void HELPER(v7m_preserve_fp_state)(CPUARMState *env) +{ + abort(); +} + +void write_v7m_exception(CPUARMState *env, uint32_t new_exc) +{ + abort(); +} + +void HELPER(v7m_vlldm)(CPUARMState *env, uint32_t fptr) +{ + abort(); +} + +void HELPER(v7m_vlstm)(CPUARMState *env, uint32_t fptr) +{ + abort(); +} + +ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) +{ + abort(); +} --=20 2.18.1