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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a18sm24435188wrt.18.2019.09.03.08.36.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Sep 2019 08:36:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=bIBiqHwLNlw6akaBX7exBs2n/dBWc3wYnn3LUfBBjxw=; b=bJj/rovfgKg8U81FEH4qt3vzVDA/yiq2X0ciAAwJsr0WM1L697GLHT1lvL/+It5ndd CfoG4ejG3laP3spJI9yywP8PV4wTHXEq/8Rh4Bqul7PAVJAPCW65nTDoL1UTlCZaXSW8 A4TpQDaF/j/BUWH/JBBG5Orx2Eel7cQUVTNOJWfyNSVBi6kCMgcrNGthcqLZbCXE1PJt 601FSERVzMYasqGCS3P8Aix1f+oQC1FX1uEcj8K0aF6Axt5Xl2PN210Z1OFSmoVbXVBr yK4cw6AwUnvHCP8qbdskAW3O3/DXY9C7yUDJa8nHkmdfU28oHBnx/LxLfV02bo3Eq5fV 6+NA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bIBiqHwLNlw6akaBX7exBs2n/dBWc3wYnn3LUfBBjxw=; b=k5XS7UF7uAf7XV+UhP5in61d5l8CTcia9RVxmv3+iBhWR30mHMkV9Spmd33c+VTGGF 8mG3ahLo2dgWb92zziVge6c44O0o7zhtLz9po5Yie17ZLUlgaUxybcew+RHGjmlT6Hfd 3QDZ5umiI8nP4v2TcPMuhWAH8mz0znpyikMyGbpeyLuVFPPsw0Q/fCCOQn63999F10UG okt4+o/o6rsQVlQoxeUYegx218dRYDE4KklDGAMqJUUXx80atd35OnA+0O8PX4kMbk97 I1Dv4JwpCMjxxCYlaYllFS6wIK0MevwWm9Q0236HMj6Mt7vvrbAAxSJP+YEwyQQOGkIW CUWQ== X-Gm-Message-State: APjAAAVW9EJfsxNg/cORue9eo9DU1xWoBiMdZaI5o+qKf85HSRZiTgFN q0vLxks7VH5FUCGm93ba+lzHt3iabee8Ew== X-Google-Smtp-Source: APXvYqwgEbh/y8Q2TLB5tRj2LQL1Igw6Rz+iAkN43LOFNFzZwmRIGBiNG4ons3R72Hd8YaHlzKwDQA== X-Received: by 2002:a1c:a404:: with SMTP id n4mr796752wme.41.1567524999788; Tue, 03 Sep 2019 08:36:39 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 3 Sep 2019 16:36:15 +0100 Message-Id: <20190903153633.6651-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190903153633.6651-1-peter.maydell@linaro.org> References: <20190903153633.6651-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 Subject: [Qemu-devel] [PULL 03/21] target/arm: Allow ARMCPRegInfo read/write functions to throw exceptions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Currently the only part of an ARMCPRegInfo which is allowed to cause a CPU exception is the access function, which returns a value indicating that some flavour of UNDEF should be generated. For the ATS system instructions, we would like to conditionally generate exceptions as part of the writefn, because some faults during the page table walk (like external aborts) should cause an exception to be raised rather than returning a value. There are several ways we could do this: * plumb the GETPC() value from the top level set_cp_reg/get_cp_reg helper functions through into the readfn and writefn hooks * add extra readfn_with_ra/writefn_with_ra hooks that take the GETPC() value * require the ATS instructions to provide a dummy accessfn, which serves no purpose except to cause the code generation to emit TCG ops to sync the CPU state * add an ARM_CP_ flag to mark the ARMCPRegInfo as possibly throwing an exception in its read/write hooks, and make the codegen sync the CPU state before calling the hooks if the flag is set This patch opts for the last of these, as it is fairly simple to implement and doesn't require invasive changes like updating the readfn/writefn hook function prototype signature. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Edgar E. Iglesias Message-id: 20190816125802.25877-2-peter.maydell@linaro.org --- target/arm/cpu.h | 6 +++++- target/arm/translate-a64.c | 6 ++++++ target/arm/translate.c | 7 +++++++ 3 files changed, 18 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0981303170a..297ad5e47ad 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2212,6 +2212,9 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpreg= id) * IO indicates that this register does I/O and therefore its accesses * need to be surrounded by gen_io_start()/gen_io_end(). In particular, * registers which implement clocks or timers require this. + * RAISES_EXC is for when the read or write hook might raise an exception; + * the generated code will synchronize the CPU state before calling the ho= ok + * so that it is safe for the hook to call raise_exception(). */ #define ARM_CP_SPECIAL 0x0001 #define ARM_CP_CONST 0x0002 @@ -2230,10 +2233,11 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpr= egid) #define ARM_CP_FPU 0x1000 #define ARM_CP_SVE 0x2000 #define ARM_CP_NO_GDB 0x4000 +#define ARM_CP_RAISES_EXC 0x8000 /* Used only as a terminator for ARMCPRegInfo lists */ #define ARM_CP_SENTINEL 0xffff /* Mask of only the flag bits in a type field */ -#define ARM_CP_FLAG_MASK 0x70ff +#define ARM_CP_FLAG_MASK 0xf0ff =20 /* Valid values for ARMCPRegInfo state field, indicating which of * the AArch32 and AArch64 execution states this register is visible in. diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 9183f89ba39..4d09ae6f424 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1714,6 +1714,12 @@ static void handle_sys(DisasContext *s, uint32_t ins= n, bool isread, tcg_temp_free_ptr(tmpptr); tcg_temp_free_i32(tcg_syn); tcg_temp_free_i32(tcg_isread); + } else if (ri->type & ARM_CP_RAISES_EXC) { + /* + * The readfn or writefn might raise an exception; + * synchronize the CPU state in case it does. + */ + gen_a64_set_pc_im(s->pc_curr); } =20 /* Handle special cases first */ diff --git a/target/arm/translate.c b/target/arm/translate.c index 66311580c05..78d93f63cab 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7191,6 +7191,13 @@ static int disas_coproc_insn(DisasContext *s, uint32= _t insn) tcg_temp_free_ptr(tmpptr); tcg_temp_free_i32(tcg_syn); tcg_temp_free_i32(tcg_isread); + } else if (ri->type & ARM_CP_RAISES_EXC) { + /* + * The readfn or writefn might raise an exception; + * synchronize the CPU state in case it does. + */ + gen_set_condexec(s); + gen_set_pc_im(s, s->pc_curr); } =20 /* Handle special cases first */ --=20 2.20.1